JPS6211753B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address space expansion method for a data processing device.

Conventionally, in a data processing device in which a microprocessor, a memory device, a display device, a keyboard, etc. are connected via an address bus and a data bus, and data is exchanged, the address is transferred using a circuit system as shown in the block circuit diagram of Figure 1. is specified and data is sent and received. In FIG. 1, a microprocessor 11 is connected to a memory package 14, a display device 19, a keyboard (not shown), etc. via an address bus 12 and a data bus 13, and the memory package 14 is connected to a memory device 1.
7 and 18, and registers 15 and 16. The address specified by the microprocessor 11 specifies the address of the memory devices 17 and 18 via the register 16, and data is transferred from the microprocessor 11 to the memory corresponding to the specified address via the data bus 13 and register 15. is stored or read. Devices other than memory devices, such as the display device 19, are addressed directly via the address bus 12 without going through registers.
Data is directly exchanged via the data bus 13.

However, if the address specification method described above is used, for example, if the address bus is 8 bits, the data bus is 8 bits, and the address has a memory capacity of up to 7 bits, then only two memory devices can be used. The problem is that it cannot be used.

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The purpose of the present invention is to take into account the problems of the conventional method described above, and to use a fixed number of address buses and data buses, based on the idea of diverting some of the data bits to address bits. An object of the present invention is to enable a memory device to be provided.

According to the present invention, a microprocessor, an address bus for transmitting a plurality of address bits for addressing a plurality of devices including a memory device that exchanges data with the microprocessor, and a plurality of data bits are provided. A data processing device having a data bus for transmitting data, and in which when one of the memory devices included in the plurality of devices is selected by the address bit, a storage area in the selected memory device is specified. , each device includes two types of memory devices with different unit data bit widths, which are the maximum number of data bits that can be stored, and a portion of the data bits transmitted on the data bus is equal to the difference in unit data bit widths. By taking in part of the data bits as the memory device selection address bits according to the contents of the address bits transmitted on the address bus,
An address space expansion method is provided which is characterized by selecting a memory device with a small unit data bit width.

The following is a second example of a data processing device using an address space expansion method according to an embodiment of the present invention.
This will be explained with reference to the figures. Microprocessor 11
is connected to a memory package 23, a display device 19, a keyboard (not shown), etc. by an address bus 12 and a data bus 13. In addition to the memory package 23, the display device 19, keyboard, etc. connected to the microprocessor 11 by the address bus 12 and data bus 13 are connected to the display device 1.
Since the connection mode similar to 9 is taken, display device 1
Only 9 is illustrated and explained, and the others are omitted. The memory package 23 includes registers 24 and 25, and a decoder 2.
6, memory devices 30, 31, 32, 33, and 34. Address bus 12 is connected to register 25, data bus 13 is connected to register 2
Connected to 4. The address bus 12 and data bus 13 will be explained below assuming that both have 8-bit lines, and FIG. 3 shows the relationship between the numbered addresses and the devices corresponding to the addresses in this embodiment.

The 0th memory device 30 and the 1st to 4th memory devices 31 to 34 in FIG. 2 differ in the unit data bit width, which is the maximum number of bits of data that can be stored. 31 against
34 are 6 bits.

Then, whether the data sent from the data bus is 8 bits and should be treated as data, the top 6
Whether the bits should be treated as data and the lower two bits as extended address bits depends on the contents of the address bits stored in register 25.

That is, if the most significant bit of the address set in the register 25 is 1, an enable signal is supplied to the decoder 26. data bus 13
The eight bits from are provided to register 24. The lower two bits of the register 24 are connected to the decoder 26 and directly to the 0th memory device 30, and when the enable signal is 1 according to the information of the lower two bits,
These two bits determine whether the memory device 31 or 3
4 is selected, and the selected address in the device is designated as one address to be stored by the information of the lower 7 bits of the register 25.
Thereafter, the upper six bits of register 24 are stored as data at a designated address in the selected memory device.

When the most significant bit of the register 25 is 0, the 0th memory device 30 or the display device 19, etc. is selected, and in the case of the memory device 30, the address to be stored in the memory device is determined by the lower 7 bits of the register 25. The 8 bits of register 24 are then stored as data. For devices other than the memory device, such as the display device 19, an address specifying the device and data to be exchanged are supplied from the directly connected address bus 12 and data bus 13, respectively. Data can be exchanged with .

According to the embodiment described above, the number of memory devices that can be provided can be increased without increasing the number of address bus and data bus lines connecting the microprocessor and each device with which it is desired to send and receive data. Can be expanded from 2 to 5.
Note that in the above embodiment, the number of memory devices is increased.
Although this has been described above, it goes without saying that the invention can also be applied to cases where there are a large number of input/output devices.

According to the present invention, by using a fixed number of address buses and data buses, more memory devices can be provided, and the storage capacity of the data processing device can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a data processing device using a conventional addressing and data transfer method, and FIG. 2 is a block circuit diagram of a data processing device using an address space expansion method as an embodiment of the present invention. FIG. 3 is a diagram showing addresses and corresponding devices in the data processing device of FIG. 2. 11... Microprocessor, 12... Address bus, 13... Data bus, 14... Memory package, 15, 16... Register, 17, 18
... Memory device, 19 ... Display device, 23 ... Memory package, 24, 25 ... Register, 26
... Decoder, 30 ... No. 0 memory device, 31
... No. 1 memory device, 32 ... No. 2 memory device, 33 ... No. 3 memory device, 34 ... No. 4 memory device. 〓〓〓〓〓

Claims (1)

[Claims] 1. A microprocessor 11, a plurality of devices 23 and 19 including a memory device that exchanges data with the microprocessor 11, and an address bus that transmits a plurality of address bits for address designation. and a data bus for transmitting a plurality of data bits, and when one of the memory devices included in the plurality of devices 23, 19 is selected by the address bit, the data bus in the selected memory device is In a data processing device in which a storage area is specified, each device includes two types of memory device 30 and memory devices 31, 32, 33, and 34 having different unit data bit widths, which are the maximum number of bits of data that can be stored, and the above-mentioned A part of the data bits transmitted on the data bus 13 can be transmitted as memory device selection address bits having a number of bits equal to the difference in unit data bit width, and depending on the contents of the address bits transmitted on the address bus 12, By capturing part of the data bits as memory device selection address bits, memory device 3 with a small unit data bit width can be used.
An address space expansion method characterized by selecting 1, 32, 33, and 34.