JPS6048620A - Periodic waveform analog-digital converting system - Google Patents

Abstract

PURPOSE:To relax the request of reduction of a segment time by splitting a digital waveform memory and correcting a data of an address of one group at each period of an input analog signal. CONSTITUTION:An address of the digital waveform memory 13 is divided into N groups 131-13N to a sampling time nT (where T is a sampling period) of a digital data in the periodic waveform A/D converting system in which an A/D- converting output is obtained from the digital waveform memory. A demultiplexer 18 and a multiplexer 19 are provided to the input and output side of the digital waveform memory 13 and they are interlocked with a distribution switch 17 so as to correct a data stored in one group address at each period of the input analog signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a periodic waveform A/D conversion method for converting an input analog signal, in which a waveform having an almost identical shape is repeated at a constant cycle, into a digital signal.

[Technical Background of the Invention and Problems Therewith] An A/D converter is generally used to convert a sample value sequence obtained by sampling an analog signal waveform at an Fr interval T into a digital signal sequence. However, A/D converters that can handle high frequencies such as those in the video band are extremely expensive, so they cannot be used for periodic analog waveforms such as the vertical synchronization signal part of a television signal. An A/D conversion method that does not use a normal A/D converter may be adopted.

Figure 1 shows such a periodic waveform A/D conversion method. When viewed in an equilibrium state after the A/D conversion is almost completed, the digital waveform memory 3 stores the input analog input to the input terminal 1. A predetermined interval portion having periodicity of the signal waveform is stored and held as digital data consisting of a plurality of samples. The contents of this digital waveform memory 3 are read out in order of sampling time under the control of a timing circuit 6, and converted into an analog signal by a D/A converter 4. The output signal of the D/A converter 4 and the input analog signal are both input to the comparator 2, and the magnitude relationship between the two levels is determined in a binary manner at each sampling time. According to the comparison and judgment results, the digital data corresponding to each sampling time of the output of the digital waveform memory 3 is converted into Δ(
quantization level) and then returned to a predetermined position in the digital waveform memory 3.

By repeatedly modifying the contents of the digital waveform memory 3 as described above for each cycle of the input analog signal, the contents of the digital waveform memory 3 gradually approach the waveform of the input analog signal, and in an equilibrium state, the contents of the digital waveform memory 3 gradually approach the waveform of the input analog signal, and in the equilibrium state This is an A/D conversion of a human-powered analog signal waveform accompanied by vibrations.

According to this A/D conversion method, a D/A converter is used instead of a normal A/D converter, so even when the sampling frequency is high, the device can be realized at a relatively low cost. It has the advantage of being possible.

However, the conventional A/D conversion method described above has the following female points. That is, in the configuration shown in FIG. 1, the speed of the clock for sequentially reading out the digital data of each sample from the digital waveform memory 3 is 1/T (T is the sampling period), so the D/A converter 4 operates at a clock frequency of 1. /T works perfectly.

In other words, the cycle time (the time required until the transient response settles down) of the D/A converter 4 must be less than or equal to T with a margin. When the settling time exceeds the king, D
The voltage value at each sampling time of the output analog signal of the /A converter 4 does not correspond correctly to the contents of the digital waveform memory 3, and the influence of the sample value one sample time before is mixed in due to leakage, and the voltage value in the comparator 2 Misjudgment. As a result, correct A/D conversion will not be performed. At this time, the allowable inter-sample leakage is determined by the number of bits of the D/A converter 4, and the larger the number of bits, the smaller the allowable value. If we try to shorten the settling time to keep this inter-sample leakage below the allowable value, when the sampling frequency becomes very high, such as in the video band, even D/A converters are not necessarily cheap. Although it is cheaper than an A/D converter with the same number of bits, it is considerably more expensive, and the above-mentioned features of the A/D conversion method are impaired.

[Object of the Invention] An object of the present invention is to provide a periodic waveform A/D that can alleviate the demand for shortening the cell ring time of a D/A converter.
The purpose is to provide a conversion method.

[Summary of the Invention] The present invention is based on the determination results of a comparator that compares the levels of the output of a D/A converter that converts the output signal of a digital waveform memory into an analog signal and the input analog signal to determine the magnitude relationship between the two. When modifying the contents of the digital waveform memory accordingly, set the address of the digital waveform memory to the sampling time of each digital data in the digital waveform memory + 1.
T (T is the sampling interval), n=1.2.・・・
・.

Assuming that KN, that is, data at sampling time +1T is stored in the n-th address, these addresses are (kN+1), (kN+2), . . .

(kN+N) (k=0.1, 2..., -I N
is an integer of 2 or more), and the data stored at the address of one group is modified every cycle of the input analog signal.

In other words, instead of modifying all KN digital data with a sampling interval T in the digital waveform memory simultaneously within one period of the input analog signal as in the past, they are stored in one group of addresses. Only the digital data corresponding to the equivalent sampling interval NT are corrected within one cycle.

[Effects of the Invention] According to the present invention, when A/D converting an analog signal with a periodic waveform, even though the final effective sampling interval is T, D/A conversion is performed for each period of the input analog signal. Since the input period of the digital signal to the device is NT,
The settling time tolerance of the D/A converter is relaxed approximately N times. Therefore, A/D conversion performance equivalent to that of the conventional method can be obtained while using an inexpensive A/A converter with a longer settling time. Also, D/A with the same settling time
When a converter is used, the upper limit of the effective sampling frequency can be increased N times compared to the conventional one, and it becomes possible to A/D convert an analog signal of a higher frequency.

[Embodiment of the Invention] FIG. 2 shows an embodiment of the periodic waveform A/D conversion method according to the present invention.

A periodic input analog signal applied to input terminal 11 is input to one of two input terminals of comparator 12. The output of the D/A converter 14 is connected to the other input terminal of the comparator 12. Digital input to D/A converter 14 is provided from digital waveform memory 13.

The digital waveform memory 13 has N (N22) memory areas 13 each having KN addresses! .

132, . . . , 13N, each memory area 131, 132 . ..., 13N respectively (kN
+1), (kN+2), ..., (kN+N) (k=0
．． 1.2. . . , are assigned addresses expressed in the series -1). That is, each memory area 1.31
, 1132 , . . . , 13N store digital data of sample values of N discrete sample numbers (corresponding to sample values of time intervals of NT). This digital waveform memory 13 is composed of a shift register or a RAM (random access memory), but a case where it is composed of a shift register will be explained here. Note that when the digital waveform memory 13 is configured with a shift register, each memory area 131,
132. . . , 13N is a parallel M-bit (M is the number of quantization bits for A/D conversion, for example 8 bits) XN stage shift register.

The timing circuit 16 controls the operation of each part based on the input analog signal. From this timing circuit 16, N series of clock pulses with a period of NT and phases shifted by 2π/N are sent to each of the digital waveform memories 13. Distribution switch 1 to memory areas 131, 132°..., 13N
7. The distribution switch 17 cyclically traces N positions in synchronization with the period of the input analog signal waveform.

A demultiplexer 18 is connected to the input side and the output side of the digital waveform memory 13 in conjunction with the distribution switch 17, respectively.
and a multiplexer 19 are provided. The demultiplexer 18 transfers the digital data corrected by the correction circuit 15 to each memory area 131, 132 . ..., 13N, and the multiplexer 19 is for supplying the digital data read from each memory area 131, 132°..., 13N to the D/A converter 14 and the correction circuit 15. It is something.

Now, if we consider that in the configuration of FIG. 2, the positions of the distribution switch 17, demultiplexer 18, and multiplexer 19 are fixed to a certain memory area, for example 131,
This is exactly the same as the configuration shown in FIG. 1, only the sampling interval has been changed from T to NT. Therefore, using exactly the same mechanism as explained for the conventional example shown in FIG. 1, the digital data of the sampled values at every NT interval of the input analog signal waveform is taken into the memory area 131 while gradually approaching the true value. The sample number series of the digital data captured at this time is assumed to be (kN+1).

Next, after a sufficient period of time has elapsed and the digital data of the sample number series (kN+1) has been A/D converted, the positions of the distribution switch 17, demultiplexer 18, and multiplexer 19 are moved to the next memory area 132, and the same process is performed. If these operations are continued, the sample values of the sample number series (kN+2) will eventually be A/D converted and the digital data will be stored in the memory area 132. In this way, by sequentially moving the distribution switch 17 around the positions of the demultiplexer 18 and the multiplexer 19, all the sample values of the sampling interval T are finally stored in the digital waveform memory 13 as digital data. It turns out. The digital data thus stored in the digital waveform memory 13 is arranged in the order of sampling time by the processing circuit 20 under the control of the timing circuit 16, and then taken out as an A/D conversion output 21.

Note that the distribution switch 17. The demultiplexer 18 and the multiplexer 19 may be switched by staying in one memory area for a long time and then moving to the adjacent memory area as described above, but a more practical method is to change the input analog signal waveform. In this method, the memory area is moved to an adjacent memory area one after another every cycle in synchronization with the cycle of . This is more convenient in practice because the digital data of all sample values approaches the true value at an even speed.

According to the embodiment described above, the period of digital input to the D/A converter 14 is NT, so if the value of N is appropriately selected depending on the size of the settling period of the D/A converter used,
In any case, the period of the digital input to the D/A converter 14 can be made larger than its settling period, making it possible to A/D convert a periodic analog signal waveform at a desired sampling interval. At this time, it takes N times longer for the A/D converted value to converge to the vicinity of the true value compared to the conventional method, but the target is a steady periodic waveform that does not change except for fluctuations due to noise. , so the convergence time is not a very important issue.

Another embodiment of the invention is shown in FIG. In this embodiment, the digital waveform memory is shifted] ~ RAM instead of registers
This embodiment differs from the first embodiment in that it is configured with a random access memory (random access memory) and that a microprocessor is used instead of a digital adder for control to modify the contents of the digital waveform memory. That is, the digital waveform memory 13 is composed of RAMs 31 and 32,
The correction circuit 15 is composed of a RAM 33 and a microprocessor 34. Further, 35 is an address generation circuit for DMA, 36 is a data bus, and 37 is an address bus.

For convenience of explanation, it is assumed that a sufficient amount of time has already passed since the start of the operation and an equilibrium state has been reached.

The input analog signal waveform is digitized in the RAM 31, and xl, x2, . ....

It is assumed that the data are stored as XxN (X is digitized waveform data). At an appropriate time before the arrival of a predetermined portion of the input analog signal waveform to be A/D converted, the waveform data for each N address of the contents of the RAM 31 is converted under the control of the microprocessor 34. Then, it is moved to the RAM 32. For example, X 1 , XN+
1 + x2N+l l ・・'+x(+<-,1)8
The series is +1. However, that 1ift, RAM3
The same data is written to N consecutive addresses of 2.

That is, ×1. ..., Xt (N pieces) XN+4 + ×N+1' ”” xN+l (N pieces)
×(K-1)N+l 1x(K-1)N+1 ' ””
A total of KN pieces of data are written, such as (K-1)N+1 (N pieces).

The contents of the RAM 32 are read out at a read clock cycle T in synchronization with the input cycle waveform under the control of the address generation circuit 35 and sent to the D/A converter 14. Formally, the period of digital input to the D/A converter 14 is T, but since N pieces of the same digital data are consecutive, the actual period is NT.

The analog output of the D/A converter 14 is compared in level with the input analog signal by the comparator 12 to determine the magnitude relationship, and the determination result is 1 bit 1~ (positive, negative) or 2 bits (positive, O2 negative). It is temporarily stored in the RAM 33 as digital information. The address of RAM33 is interlocked with the address of RAM32.

The judgment results temporarily stored in the RAM 33 are read out by the microprocessor 34 after the comparison 1 judgment is completed for all KN pieces of data, and are used to modify the digital data in the RAM 31. At that time, the number actually provided to the correction performance by the microprocessor 34 is N.
Among the judgment results for every other piece, only the judgment result corresponding to the digital data immediately before the digital input to the D/A converter 14 changes is adopted.

Until the arrival of the next cycle of the input analog signal waveform, the digital data in the RAM 31 is corrected, but then the data in the RAM 31 is changed to a different address from the previous one. Data is transferred to RAM32. Then, N pieces of data are successively written into the RAM 32, but their positions are shifted by one position from the previous time and become as follows.

0, X2 , X2 , ・=, X2 (N pieces) XN+2
・X N-1-2・゛ ・XN+2 (N pieces)
”' + x(+c-1)N+2 (N' pieces) D
The /A converted signal and the input analog signal are compared in level, and the corresponding data in the RAM 31 is modified based on the determination result. At this time, there is a possibility that a valid judgment result will not be obtained for x(K-1)N+2, so
(Corrections are made up to K-2%+2.

In this way, by repeating the same operation while shifting the set of waveform data to be transferred to the RAM 32 and its write address one by one each time an input analog signal waveform arrives, finally ((K -1) N+1) digital data are obtained.

According to the above explanation, RAM32 and RAM33 are required to operate at a fairly high speed;
This is because all of the address selection control is carried out by the microprocessor 34 and executed by rough 1 to software. By complicating the hardware of the address generation circuit 35 and changing the phase of the address generation circuit drive clock every cycle of the input analog signal waveform, the operating speed and capacity of the RAM 32 and RAM 33 can be reduced to 1/H. I can do it.

The present invention is not limited to the embodiments described above, and can be implemented with various other modifications.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional periodic waveform A/D conversion method, FIG. 2 is a diagram showing the configuration of a periodic waveform Δ/D conversion method according to an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of a periodic waveform Δ/D conversion method according to an embodiment of the present invention. It is a figure which shows the structure of the periodic waveform A/D conversion system based on another Example. 11...Analog signal input terminal, 12...Comparator,
13... Digital waveform memory, 14... D/A converter, 15... Correction circuit, 16... Timing circuit, 17... Distribution switch, 18... Demultiplexer, 19... Multiplexer, 20... processing circuit,
21...A/D...Conversion output. Applicant's agent Patent attorney Takehiko Suzue No. 1 Big 1

Claims (1)

[Claims] A digital waveform memory for storing and holding the waveform of a periodically repeated input analog signal as digital data consisting of a plurality of samples, and a D/A for converting the output data of this digital waveform memory into an analog signal. a converter, a comparator that compares the levels of the output signal of the D/A converter and the input analog signal and determines the magnitude relationship between the two, and corrects the contents of the digital waveform memory according to the determination result of the comparator. In the periodic waveform A/D conversion method for obtaining an A/D conversion output from the digital waveform memory, the address of the digital waveform memory is set at a sampling time n T (T is a sampling interval) of each digital data. On the other hand, let n=1°2, . . . , KN, and these addresses are (kN+1). (kN+2), ..., (k N+N) (k = 0.1
゜Divide into N groups of 2, . . . , -1, N is an integer of 2 or more), and modify the data stored at the address of one group every cycle of the input analog signal. A periodic waveform A/D conversion method characterized by: