JPH0139249B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a periodic waveform A/D conversion method for converting an input analog signal in which a waveform of substantially the same shape is repeated at a constant cycle into a digital signal.

[Technical background of the invention and its problems] An A/D converter is generally used to convert a sample value series obtained by sampling an analog signal waveform at regular intervals T into a digital signal series. However, A/D converters that can handle high frequencies such as those in the video band are extremely expensive. In some cases, an A/D conversion method that does not use a normal A/D converter is adopted.

Figure 1 shows such a periodic waveform A/D conversion method. When viewed in an equilibrium state after the A/D conversion is almost completed, the digital waveform memory 3 stores the input analog input to the input terminal 1. A predetermined interval portion having periodicity of the signal waveform is stored and held as digital data consisting of a plurality of samples. The contents of this digital waveform memory 3 are read out in the order of sampling time under the control of a timing circuit 6, and converted into an analog signal by a D/A converter 4. The output signal of the D/A converter 4 and the input analog signal are both input to the comparator 2, and the magnitude relationship between the two levels is determined in a binary manner at each sampling time. According to the comparison and judgment result, the digital data corresponding to each sampling time of the output of the digital waveform memory 3 is increased or decreased by Δ (quantization level) in the correction circuit 5, and then returned to the predetermined position in the digital waveform memory 3. .

By repeatedly modifying the contents of the digital waveform memory 3 as described above for each cycle of the input analog signal, the contents of the digital waveform memory 3 gradually approach the waveform of the input analog signal.
In a balanced state, the input analog signal waveform is A/D converted with vibrations of ±Δ.

According to this A/D conversion method, a D/A converter is used instead of a normal A/D converter, so even when the sampling frequency is high, the device can be realized at a relatively low cost. It has the advantage of being possible.

However, the conventional A/D conversion method described above has the following drawbacks. That is, in the configuration shown in FIG. 1, the speed of the clock for sequentially reading out the digital data of each sample from the digital waveform memory 3 is 1/T (T is the sampling period).
Therefore, the D/A converter 4 must operate completely at a clock frequency of 1/T. In other words, the settling time (the time required for the transient response to settle down) of the D/A converter 4 must be less than or equal to T with a margin. If the settling time exceeds T, the voltage value at each sampling time of the output analog signal of the D/A converter 4 will not correspond correctly to the contents of the digital waveform memory 3.
The influence of the sample value one sample time before is mixed in due to leakage, causing the comparator 2 to make an incorrect determination. As a result, correct A/D conversion will not be performed. The amount of inter-sample leakage that can be tolerated at this time is determined by the number of bits of the D/A converter 4, and the larger the number of bits, the smaller the amount of leakage that can be tolerated. If we try to shorten the settling time to keep this inter-sample leakage below the allowable value, when the sampling frequency becomes very high, such as in the video band, even D/A converters are not necessarily cheap. , A/D with the same number of bits
Although it is cheaper than a converter, it is still quite expensive, and the above-mentioned features of the A/D conversion method are impaired.

[Object of the Invention] An object of the present invention is to provide a periodic waveform A/D conversion method that can alleviate the requirement for shortening the settling time of a D/A converter.

[Summary of the Invention] The present invention is based on the determination results of a comparator that compares the levels of the output of a D/A converter that converts the output signal of a digital waveform memory into an analog signal and the input analog signal to determine the magnitude relationship between the two. When modifying the contents of the digital waveform memory accordingly, the address of the digital waveform memory is set to the sampling time nT (T is the sampling interval) of each digital data in the digital waveform memory, n = 1, 2, ..., KN.
In other words, assuming that the data at sampling time nT is stored in the nth address, these addresses are {kN+1}, {kN+2}, ..., {kN+N}
Data is divided into N groups (k = 0, 1, 2, ..., K-1, N is an integer of 2 or more) and is stored at the address of one group for each period of the input analog signal. It is characterized by correcting.

In other words, instead of modifying all KN digital data with sampling interval T in the digital waveform memory simultaneously within one cycle of the input analog signal as in the past, the equivalent data stored in one group of addresses is K is the sampling interval NT
In this method, only 1 digital data are corrected within one cycle.

[Effects of the Invention] According to the present invention, a periodic waveform analog signal is
When performing D conversion, although the final effective sampling interval is T, the input period of the digital signal to the D/A converter for each period of the input analog signal is NT, so the D/A conversion is The settling time tolerance of the device is relaxed approximately N times. Therefore, A/D conversion performance equivalent to that of the conventional system can be obtained while using an inexpensive D/A converter with a longer settling time. Furthermore, when using D/A converters with the same settling time, the upper limit of the effective sampling frequency can be increased by N times compared to conventional methods, making it possible to A/D convert analog signals with higher frequencies. Become.

[Embodiment of the Invention] FIG. 2 shows an embodiment of the periodic waveform A/D conversion method according to the present invention.

A periodic input analog signal applied to input terminal 11 is input to one of two input terminals of comparator 12. The other input terminal of comparator 12 has D/
The output of the A converter 14 is connected. Digital input to D/A converter 14 is provided from digital waveform memory 13.

The digital waveform memory 13 has (N2) memory areas 13 ₁ , 1 each having KN addresses.
3 ₂ ,..., 13 _N , and each memory area 13 ₁ , 13 ₂ ,..., 13 _N has {kN+
1}, {kN+2}, ..., {kN+N} (k=0, 1,
2, . . . , K-1) are assigned. That is, each memory area 13 ₁ ,
13 ₂ , . . . , 13 _N store digital data of sample values of N discrete sample numbers (corresponding to sample values of time intervals of NT). This digital waveform memory 13
is composed of a shift register or RAM (random access memory), but here we will explain the case where it is composed of a shift register. Note that when the digital waveform memory 13 is configured with a shift register, each memory area 13 ₁ , 13 ₂ ,
. . , 13 _N is a parallel M-bit (M is the number of quantization bits in A/D conversion, for example, 8 bits)×N stage shift register.

The timing circuit 16 controls the operation of each part based on the input analog signal.The timing circuit 16 has a period of NT and a phase difference of 2π/N from each other.
N series of clock pulses shifted by 1 are stored in each memory area 13 ₁ , 13 2 , 13 ₂ of the digital waveform memory 13
..., 13 _N via the distribution switch 17. The distribution switch 17 cyclically traces N positions in synchronization with the period of the input analog signal waveform.
A demultiplexer 18 and a multiplexer 19 are provided on the input and output sides of the digital waveform memory 13, respectively, in conjunction with the distribution switch 17. Demultiplexer 18 is modified circuit 15
The digital data corrected in each memory area 1
3 ₁ , 13 ₂ , ..., 13 _N , and the multiplexer 19 returns each memory area 13 ₁ , 13 ₂ ,
..., _13N to supply the digital data read from the D/A converter 14 and the correction circuit 15.

Now, if we consider that in the configuration of FIG. 2, the positions of the distribution switch 17, demultiplexer 18, and multiplexer 19 are fixed to a certain memory area, for example ₁₃₁ , this is exactly the same as the configuration of FIG. , the sampling interval simply changes from T to NT. Therefore, using exactly the same mechanism as explained for the conventional example shown in FIG. 1, the digital data of the sample values of the input analog signal waveform at every NT interval is taken into the memory area ₁₃₁ while gradually approaching the true value. Let the sample number series of the digital data taken in at this time be {kN+1}.

Next, after a sufficient period of time has passed and the digital data of the sample number series {kN+1} has been A/D converted, the positions of the distribution switch 17, demultiplexer 18, and multiplexer 19 are moved to the next memory area _132. If similar operations are continued, the sample values of the sample number series {kN+2} will eventually be A/D converted and the digital data will be stored in the memory area ₁₃₂ . In this way, the distribution switch 17 is sequentially connected to the demultiplexer 1.
8 and the multiplexer 19, all the sample values at the sampling interval T are finally stored in the digital waveform memory 13 as digital data. The digital data thus stored in the digital waveform memory 13 is arranged in the order of sampling time by the processing circuit 20 under the control of the timing circuit 16, and then taken out as an A/D conversion output 21.

In addition, distribution switch 17, demultiplexer 1
8 and multiplexer 19 can be done by staying in one memory area for a long time and then moving to the next memory area as described above, but a more practical method is to change the frequency of the input analog signal waveform. This is a method of moving the data to adjacent memory areas one after another every cycle in synchronization with . This method is convenient in practice because the digital data of all sample values approaches the true value at an even speed.

According to the embodiment described above, the period of digital input to the D/A converter 14 is NT, so if the value of N is appropriately selected depending on the settling period of the D/A converter used, in any case But D/A
The period of the digital input to the converter 14 can be made larger than its settling time, making it possible to A/D convert a periodic analog signal waveform at a desired sampling interval. At this time, A/
Although it takes N times longer for the D-converted value to converge to the vicinity of the truth than the conventional method, since the target is a steady periodic waveform that does not change except for fluctuations due to noise, convergence is possible. Time is not a major issue.

Another embodiment of the invention is shown in FIG. In this example, the digital waveform memory is configured with a RAM (random access memory) instead of a shift register, and a microprocessor is used instead of a digital adder for control to modify the contents of the digital waveform memory. This embodiment differs from the first embodiment in that That is, the digital waveform memory 13 is composed of RAMs 31 and 32, and the correction circuit 15 is composed of RAM 33 and a microprocessor 34.
It is made up of. Further, 35 is an address generation circuit for DMA, 36 is a data bus, and 37 is an address bus.

For convenience of explanation, it is assumed that a sufficient amount of time has already passed since the start of the operation and an equilibrium state has been reached.
The input analog signal waveform is digitized in the RAM 31, and X ₁ , X ₂ , ..., in the order of sample number.
Assume that the data is stored as X _KN (X is digitized waveform data). At an appropriate time before the arrival of a predetermined portion of the input analog signal waveform to be A/D converted, K waveform data for each N address of the contents of the RAM 31 are transferred under the control of the microprocessor 34. Then, it is moved to RAM32. For example, X ₁ , X _N+1 , X _2N+1 ,..., X _(K-1)N+1
This is the series. However, at that time, the same data is written to N successive addresses in the RAM 32. That is, X ₁ , ..., X ₁ (N pieces) X _N+1 , X _N+1 , ..., X _{N+1 (} N pieces) _... A total of KN pieces of data are written, such as _1)N+1 , ...X _(K-1)N+1 (N pieces).

The contents of the RAM 32 are read out at a read clock cycle T in synchronization with the input cycle waveform under the control of the address generation circuit 35 and sent to the D/A converter 14. Formally, the period of digital input to the D/A converter 14 is T, but since N pieces of the same digital data are consecutive, the actual period is T.
It is NT.

The analog output of the D/A converter 14 is sent to the comparator 12.
The level is compared with the input analog signal to determine the magnitude relationship, and the determination result is 1 bit (positive, negative).
Alternatively, it is temporarily stored in the RAM 33 as 2-bit (positive, 0, negative) digital information. RAM33
The address is linked with the address of RAM32.

The judgment result temporarily stored in RAM33 is KN
After all the data have been compared and judged, the data is read out by the microprocessor 34 and used to modify the digital data in the RAM 31. At that time, the microprocessor 3
In step 4, every N determination results are actually used in the correction calculation, and only the determination results corresponding to the digital data immediately before the digital input to the D/A converter 14 changes are adopted.

The digital data in the RAM 31 is corrected until the next cycle of the input analog signal waveform arrives;
Of the data in 1, K at a different address from the previous time
data is transferred to the RAM 32. Then, N pieces of data are successively written into the RAM 32, but their positions are shifted by one position from the previous time, as shown below.

O, X ₂ , X ₂ ,... _, X ₂ (N pieces) X _{N+2 ,} X _N+2 ,..., _{(K-1)N+2 ,} ...,
Corresponding data in RAM 31 is modified. At this time, since there is a possibility that a valid determination result may not be obtained for X _(K-1)N+2 , corrections are made for up to X _(K-2)N+2 .

In this way, by repeating the same operation while shifting the set of waveform data transferred to the RAM 32 and the write address one by one each time an input analog signal waveform arrives, the final result is { (K-1)N+1} digital data are obtained.

According to the above explanation, RAM32 and RAM33
is required to operate at a fairly high speed, because all address selection control of these RAMs is carried out by software, with the burden placed on the microprocessor 34. By complicating the hardware of the address generation circuit 35 and changing the phase of the address generation circuit drive clock every cycle of the input analog signal waveform, the RAM 32 and
The operating speed and capacity of RAM 33 can be reduced to 1/N.

The present invention is not limited to the embodiments described above, and can be implemented with various other modifications.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional periodic waveform A/D conversion method, FIG. 2 is a diagram showing the configuration of a periodic waveform A/D conversion method according to an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of a periodic waveform A/D conversion method according to an embodiment of the present invention. It is a figure which shows the structure of the periodic waveform A/D conversion system based on another Example. 11...Analog signal input terminal, 12...Comparator,
13... Digital waveform memory, 14... D/A converter, 15... Correction circuit, 16... Timing circuit, 1
7...Distribution switch, 18...Demultiplexer, 1
9... Multiplexer, 20... Processing circuit, 21...
A/D...Conversion output.

Claims (1)

[Claims] 1. A digital waveform memory for storing the periodically repeated waveform of an input analog signal as digital data consisting of multiple samples; a D/A converter for converting the output data of this digital waveform memory into an analog signal; A comparator that compares the levels of the output signal of the D/A converter and the input analog signal and determines the magnitude relationship between the two, and a correction means that modifies the contents of the digital waveform memory according to the determination result of the comparator. In the periodic waveform A/D conversion method for obtaining an A/D conversion output from the digital waveform memory, the modification means sets an address of the digital waveform memory to a sampling time nT (T is a sampling interval) of each digital data. For n = 1, 2, ..., KN, these addresses are {kN+1}, {kN+2}, ..., {kN+
N} (k = 0, 1, 2, ..., K-1, N is an integer of 2 or more) and are stored in one group address for each period of the input analog signal. A periodic waveform A/D conversion method characterized by correcting existing data.