JPS6038030B2 - Manufacturing method for MIS integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a MIS integrated circuit device that is high-speed and has low power consumption.

In general, the performance of MIS integrated circuit devices in terms of switching speed, power consumption, etc. is determined by transistor gm, parasitic capacitance C
plays an important role.

In other words, the larger gm and C are 4.0, the smaller the time constant C/gm becomes, so high-speed operation is possible, and the smaller C is, the lower the power consumption during switching transients. . By the way, the parasitic capacitance C in the MIS integrated circuit device is a collection of parasitic capacitances of various parts.

That is, since the basic circuit of the MIS integrated circuit device is an isoverter circuit, this will be explained next with reference to FIG. In the figure, TRo is the driver transistor, TR is the load transistor, CL is the total capacitance of the gate circuit, and C
os indicates the capacitance between the gate and source, COD indicates the capacitance between the gate and drain, Cos indicates the capacitance between the drain and source, and CM indicates the metal wiring capacitance. The total capacity CL is C...CG
s ten (10 A) Cco ten Cos + CMA: Expressed by the voltage gain of the inverter, the switching speed is CL/blade mL
(gm of load transistor TRL) and the output is proportional to gmLVoo2.

Therefore, the capacity CL affects the speed and power, and the speed/power ratio is CLVDo2.

Incidentally, the most problematic of the capacitances CL is the gate-drain capacitance Cco.

The reason for this is that due to the so-called mirror effect, as is clear from the above equation, it is expanded to (10 A) CGD and converted to the input side. In the early days of MIS integrated circuit devices, aluminum gates were often used, and in that case, the aluminum gate was formed after the source and drain regions were formed.

Therefore, the overlap between the region and the gate becomes large due to the necessity of obtaining a margin for mask alignment, and as a result, the capacitance CGo is also large. Therefore, a silicon process was developed to eliminate this drawback. As is well known, after forming a polycrystalline silicon gate, the source and drain regions are self-circulated using the gate as a mask.
It is formed in alignment. However, although this technology had a remarkable effect of reducing the capacitance CGo in relatively large devices with a gate length L of about 5 to 10 [rm], in recent years, MIS integrated circuit devices are becoming more and more high-speed. Developments are being made to shorten the gate length L with the aim of reducing power consumption and power consumption, and the overlap between the source region and the gate has once again become a problem. That is, no matter how the source and drain regions are formed in a self-aligned manner using a gate mask, the lateral expansion of these regions cannot be avoided. For example, as shown in FIG. 2, a gate oxide film 3 and a polycrystalline silicon gate 4 are formed on a silicon semiconductor substrate 1, and impurities are diffused from the opening 2A using, for example, a vapor phase diffusion method to form a source. When the region 5 and the drain region 6 are formed, an overlap as shown by symbol A occurs with respect to the gate. The length of the overlap A is approximately the same as the depth Xg of the region. The parasitic capacitance caused by such overlap A, especially CGo, is 1 to 2 [French m]
This cannot be ignored for devices that are trying to achieve a gate length of . Note that 2 in FIG. 2 indicates a field oxide film. In the prior art described above, the source region 5 and drain region 6 are also formed by ion implantation using the gate 4 as a mask, but even in that case, due to the characteristics of the ion implantation method, the lateral expansion of the regions 5 and 6 is limited. cannot be avoided.

The present invention makes it possible to obtain a high-speed, low-power consumption device by eliminating the overlap between the gate and drain regions in a short channel MIS integrated circuit device, which will be described below. Explain in detail.

The present invention is based on applying the ion implantation method to form the source region and the drain region, and utilizing the linearity of the ions at that time.

FIGS. 3 to 9 are process diagrams of one embodiment of the present invention, and description will now be made with reference to these figures.

Refer to FIG. 3. For example, a field oxide film 12 is formed on a p-type silicon semiconductor substrate 11 by applying a thermal oxidation method.

Refer to FIG. 4 '21 The field oxide film 12 is patterned by applying a normal photo ring fee.

An element portion entrance 12A is formed. See FIG. 5 Glue A thin oxide film 12' is formed by applying, for example, a thermal oxidation method.

'4' For example, the polycrystalline silicon film 13 is formed by applying chemical vapor deposition.

Refer to FIG. 6 '51 The polycrystalline silicon film 13 is patterned by applying ordinary photolithography to form a silicon gate 13G.

{6) Subsequently, the thin oxide film 12' is patterned to form a gate oxide film 12G.

Refer to FIG. 7 t71 For example, adjacent ions are implanted using an ion implantation method to form a source region S and a drain region D.

In this case, ion implantation is performed obliquely to the substrate surface. In this way, as is clear from the figure, the silicon gate 13G serves as a mask, and it is possible to prevent the drain region ◯ from overlapping the gate portion. See Fig. 8 ■ Heat treatment is performed to activate the implanted phosphorus ions.

This activation temperature is determined as appropriate in consideration of the conditions of ion implantation, but it is usually at a temperature that does not cause diffusion spread in regions S and D, but in some cases it may be set to a temperature that causes slight diffusion. It's okay to be. In this way, even after activation, it is possible to prevent the drain region D and the gate from overlapping each other, and even if the overlap occurs, it is small, so that the parasitic capacitance CGo becomes smaller. On the other hand, although the overlap between the source region S and the gate becomes large and the parasitic capacitance Cos increases, this does not pose much of a problem because the Miller effect does not act on this. '9}
For example, the silicon dioxide insulating film 14 is formed by applying a chemical vapor deposition method.

OQ Insulating film 1 by applying normal photo/linkage photo
4 is patterned to form an electrode contact window.

Refer to FIG. 9 (11) For example, a vapor deposition method is applied to form, for example, an aluminum film.

(12) The aluminum film is patterned by applying ordinary photolithography, and the source electrode 15S,
A drain electrode 15D and a gate electrode 15G are formed.

In the above embodiment, it is important to perform the ion implantation from an oblique direction, so the data will be shown next.

As seen in Figure 10a, the injection angle is a and the overlap is A.
y, phosphorus ions are implanted, and the results are expressed using the implantation energy as a parameter, as shown in FIG. 10b.

In addition, the thickness of the gate part (12G + 113G) is 3000 [
A]. FIG. 11 shows data when implantation of ion implantation is performed, and the conditions are substantially the same as those in FIG. 10. The data show that the implant angle increases with increasing implant energy.

Based on these relationships, it is easy to control so that the overlap Ay does not occur even when the drain region D is completed. By the way, if the present invention is applied to the manufacturing process of an integrated circuit device, care must be taken in designing the mask pattern because ion implantation is performed in an oblique direction.

That is, for example, in the case of an inverter circuit, at least all driver transistors used for amplification must have their gates aligned in the same direction, and the sides on which the sources and drains are formed with respect to the gates must also be the same. If such a design is absolutely difficult, the wafer may be divided into appropriate sections using a mask, and ions may be implanted in each section. In the above example, polycrystalline silicon was used as a mask for ion implantation, but other materials,
For example, a high melting point metal such as molybdenum may be used.

As can be seen from the above explanation, according to the present invention, the overlap between the gate and the drain can be reduced to zero or significantly reduced, so that parasitics that have a large effect on the deterioration of device characteristics due to the mirror effect can be reduced. Capacity CG. There are very few M
An IS integrated circuit device can be obtained.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram explaining the generation of parasitic capacitance, Figure 2 is an explanatory diagram of the conventional example, Figures 3 to 9 are process diagrams of the present invention-embodiment, and Figures 10 and 11 are diagonal diagrams. FIG. 3 is a diagram showing data when ion implantation is performed. In the figure, 11 is a substrate, 12 is an oxide film, 12G is a gate oxide film, 13G is a silicon gate, 14 is an insulating film,
S represents a source region, D represents a drain region, 15S represents a source electrode, 150 represents a drain electrode, and 15G represents a gate electrode. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 11 Figure 10

Claims (1)

[Claims] 1. A step is included in which ions are implanted from an oblique direction into a semiconductor substrate on which a gate electrode and windows for source and drain regions are formed, so that at least the edges of the drain region do not overlap with the gate portion. A method for manufacturing an MIS integrated circuit device, characterized in that: