JP3007765B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to element isolation of a semiconductor device.

[0002]

2. Description of the Related Art The realization of a large-capacity VLSI depends on the realization of a highly integrated circuit within a limited chip area. That is, in order to improve the degree of integration, it is dependent on how to miniaturize the elements constituting the integrated circuit, and it is necessary to realize not only fine transistors but also particularly fine element isolation.

Usually, a selective oxidation method (LOCOS method) is used to form an element isolation region. In this method, after forming an oxide film and a nitride film on a silicon substrate, patterning is performed, the nitride film on the element isolation region is removed, and the silicon substrate is selectively oxidized to be relatively thick. This is a method for forming a silicon oxide film (LOCOS film).

On the other hand, as another element isolation method, there is a field shield isolation method. In this method, after forming an oxide film and a conductive film on a silicon substrate, patterning is performed, and the conductive film is left on the element isolation region to form a shield electrode, and a desired voltage is applied to the shield electrode. This is a method in which a parasitic transistor between elements is not operated.

[0005]

However, in element isolation by the selective oxidation method, the silicon substrate is oxidized to a region covered with the nitride film during the selective oxidation, and a silicon oxide film called a bird's beak spreads. However, the size after patterning was larger than that after patterning, and was not suitable for fine element isolation.

Further, in the element isolation by the field shield isolation method, there is no problem of the pattern shift due to the bird's beak, but a voltage must be constantly applied to the shield electrode on the element isolation region.
A power supply circuit for element isolation must be formed on a silicon substrate, and there is a problem that power consumption increases or a chip area increases accordingly.

[0007]

According to the present invention, in order to solve the above-mentioned problems, a ferroelectric film polarized in a direction to increase the inversion voltage is formed on a semiconductor substrate in an element isolation region. This is due to the characteristic semiconductor device.

Further, the present invention is the above-mentioned semiconductor device, wherein the semiconductor device has an electrode on the ferroelectric film and a means for externally applying a voltage to the electrode. .

Further, according to the present invention, in the above semiconductor device, an electrode is provided on the ferroelectric film, a voltage generating circuit for applying a voltage to the electrode is provided, and a voltage is intermittently applied to the electrode. It is characterized by the following.

Further, according to the present invention, in the method for manufacturing a semiconductor device, after the step of forming a transistor having a source, a drain region, and a gate electrode on the semiconductor substrate, After depositing a dielectric film, depositing a conductive film on the ferroelectric film and processing the conductive film to form the electrode, a desired voltage is applied to the electrode to increase the inversion voltage. And a step of polarizing the ferroelectric film.

Further, the present invention is characterized in that in the method of manufacturing a semiconductor device, the time order of the steps is changed.

Further, according to the present invention, in the method of manufacturing a semiconductor device, after the step of forming a transistor having a source, a drain region, and a gate electrode on the semiconductor substrate, After depositing a dielectric film, depositing a conductive film on the ferroelectric film, applying a desired voltage to the conductive film and polarizing the ferroelectric film in a direction to increase the inversion voltage, The method includes a step of processing the film to form the electrode.

Further, the present invention is characterized in that in the above-described method for manufacturing a semiconductor device, the time order of the steps is changed.

[0014]

According to the present invention, there is no pattern shift due to a bird's beak, and a device can be isolated by applying a voltage to the ferroelectric film to polarize the film and increasing an inversion voltage in the device isolation region.

Further, even if the power supply circuit for element isolation becomes unnecessary or the power supply circuit for element isolation is provided, it is not necessary to always operate the power supply circuit.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment in which the present invention is applied to an NMOS transistor will be described below with reference to FIGS. FIG. 1 is a cross-sectional view in each manufacturing process according to the present embodiment, and FIG. 2 is a diagram illustrating a planar structure of a resist pattern according to the present embodiment. In addition, A- in FIG.
The cross section of A 'corresponds to the cross section in each manufacturing step in FIG.

First, on a P-type silicon substrate 10 whose surface concentration is controlled so as to obtain a desired transistor threshold voltage, a gate oxide film 11 (100 °) by thermal oxidation and a gate made of polysilicon in which impurities are diffused. Electrode film 12
After forming (1000 °), a resist pattern 13 defining a gate electrode is formed by a photo process (FIG. 1).
(A), FIG. 2 (a)).

Next, using the resist pattern 13 as a mask, the gate electrode film 1 is exposed until the gate oxide film 11 is exposed.
2, anisotropic etching is performed to form a gate electrode 14, the resist pattern 13 is removed after the etching, and a resist pattern 15 defining an NMOS transistor formation region is formed by a photo process. Thereafter, using the gate electrode 14 and the resist pattern 15 as a mask, arsenic ions, which are N-type impurities, are implanted under the conditions of, for example, an energy of 50 KeV and an implantation amount of 3 × 10 ¹⁵ cm ⁻² to form the source and drain regions 16 (Fig. 1 (b), Fig. 2
(B)).

Next, after removing the resist pattern 15, an insulating film 17 (3000 °) is deposited on the entire surface, and a resist pattern 18 is formed by a photo process so as to cover the NMOS transistor region (FIG. 1C, FIG. 2
(C)).

Next, using the resist pattern 18 as a mask, the insulating film 17 and the gate oxide film 11 on the P-type silicon substrate 10 are removed, and a ferroelectric film 19 (3000 °) of Bi ₄ Ti ₃ O _{12 is} formed. , And conductive film 2 made of Pt
0 (1500 °) is deposited. Then, on the conductive film 20,
A negative voltage, for example, -12 V (400 V / cm) is applied to polarize the ferroelectric film 19, and the P-type silicon substrate 10
Above, the element isolation region is set to the accumulation state, and the inversion voltage is increased. Thereafter, the resist pattern 21 is formed by a photo process.
Is formed (FIGS. 1D and 2D).

Next, using the resist pattern 21 as a mask, the conductive film 20 on the NMOS transistor region and
The ferroelectric film 19 is removed, and the shield electrode 22 is formed (FIG. 1E).

Thereafter, the gate electrode 1 is formed by a conventional process.
4. If wiring is provided to the source / drain region 16 and the shield electrode 22, a semiconductor device using a ferroelectric film in the element isolation region can be formed. In this embodiment,
The element isolation forming step is a later step than the transistor forming step.

Next, a second embodiment of the present invention will be described with reference to FIG.

First, on a P-type silicon substrate 30, Bi ₄
Ferroelectric film 31 of Ti ₃ O ₁₂ (3000 °), P
t, a conductive film 32 (1500 °), an insulating film 33 (1
After forming the resist pattern 34, a resist pattern 34 is formed by a photo process (FIG. 3A).

Next, using the resist pattern 34 as a mask, the ferroelectric film 31, the conductive film 32, and the insulating film 33 are etched until the P-type silicon substrate 30 is exposed, thereby forming a shielding electrode 35, After removing the pattern 34, an insulating film 36 (about 500 °) is deposited (FIG. 3B). After the shield electrode 35 is formed, a hole is formed in the insulating film 33 on the shield electrode 35 (not shown), and a negative voltage, for example, −12 is applied to the shield electrode 35.
V (400 V / cm) is applied to polarize the ferroelectric film 31 so that an element isolation region is formed on the P-type silicon substrate 30.
In the accumulation state, increase the inversion voltage.

Next, after implanting a P-type impurity so as to obtain a desired transistor threshold voltage, the entire surface is etched back to form a side wall 37 on the side wall portion of the shield electrode 35 (FIG. 3 ( c)).

Next, a gate oxide film 38 (100 °) is formed on the P-type silicon substrate 30 by thermal oxidation, and a gate electrode film 39 (1000) made of polysilicon in which impurities are diffused.
After forming Å), a resist pattern 40 defining the gate electrode of the NMOS transistor is formed by a photo process (FIG. 3D).

Next, using the resist pattern 40 as a mask, the gate oxide film 3 on the NMOS transistor formation region is formed.
Until 8 is exposed, the gate electrode film 39 is anisotropically etched to form the gate electrode 41, and after the etching, the resist pattern 40 is removed. After that, the gate electrode 41
And the shielding electrode 35 as a mask, for example, under the conditions of an energy of 50 KeV and an injection amount of 3 × 10 ¹⁵ cm ⁻² ,
Arsenic ions, which are mold impurities, are implanted to form source and drain regions 42 (FIG. 3E).

Thereafter, the gate electrode 4 is formed by a conventional process.
1. If a wiring is formed on the source / drain region 42 and the shield electrode 35, a semiconductor device using a ferroelectric film in the element isolation region can be formed. In this embodiment,
The element isolation forming step is a step before the transistor forming step.

The timing of applying the voltage to the shield electrode is naturally not limited to the above embodiment. For example, from the pad connected to the shield electrode immediately before the wafer test, or from the pin after assembly. A voltage can be applied as appropriate. The application of the voltage can naturally be performed not only once but also intermittently. Alternatively, a power supply circuit for element isolation for generating a voltage applied to the shield electrode can be provided on the same semiconductor substrate as the semiconductor device, and the voltage can be intermittently applied to the shield electrode.

The method of forming the ferroelectric film may be any of a sol-gel method, a sputtering method, and a CVD method, and other materials may be used as long as they exhibit ferroelectricity, and are not limited to the above materials. In order to stabilize the dielectric constant of the ferroelectric film, it is preferable to perform annealing in N ₂ , O ₂ , or an inert gas after the formation of the ferroelectric film. Further, in this embodiment, the electrode or the conductive film remains in the semiconductor device, but after increasing the inversion voltage by applying a voltage, the electrode or the conductive film is removed. Is also good.

Further, the present invention relates to the NM shown in the above embodiment.
The present invention can be applied not only to the OS transistor but also to the PMOS transistor, and the polarity of the voltage applied to the electrode at that time is opposite to that of the above embodiment. That is, in the case of a PMOS transistor on an N-type silicon substrate, a positive voltage is applied to make the surface of the N-type silicon substrate below the shield electrode an accumulation state, and the inversion voltage is increased.

In order to adjust the amount of holes or electrons in the accumulated state on the surface of the silicon substrate, an impurity may be introduced into the surface of the silicon substrate.

The present invention can be variously modified within the scope of the claims, and is not limited to the conditions during the steps in the above-described embodiment.

[0035]

As described above in detail, according to the present invention, since there is no pattern shift due to bird's beak and there are no defects and interface states at the LOCOS end by the selective oxidation method, it is possible to reduce the junction leakage. Can be.

Furthermore, during the manufacturing process, the ferroelectric film is polarized, the surface of the silicon substrate is accumulated, and the inversion voltage of the element isolation region can be increased, so that a power supply circuit for element isolation becomes unnecessary. In addition, the power supply circuit for element isolation can be operated intermittently, and low power consumption and high integration can be easily achieved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view in each manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a planar structure of a resist pattern according to a first embodiment of the present invention.

FIG. 3 is a cross-sectional view in each manufacturing process according to a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 P-type silicon substrate 11 Gate oxide film 12 Gate electrode film 13 Resist pattern 14 Gate electrode 15 Resist pattern 16 Source / drain region 17 Insulating film 18 Resist pattern 19 Ferroelectric film 20 Conductive film 21 Resist pattern 22 Shielding electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/76 H01L 29/78

Claims (7)

(57) [Claims] 1. A semiconductor device, comprising: a ferroelectric film polarized in a direction to increase an inversion voltage on a semiconductor substrate in an element isolation region. 2. The semiconductor device according to claim 1, further comprising an electrode on said ferroelectric film, and means for externally applying a voltage to said electrode. 3. The semiconductor device according to claim 1, further comprising an electrode on said ferroelectric film, a voltage generating circuit for applying a voltage to said electrode, and intermittently applying a voltage to said electrode. A semiconductor device characterized by the above-mentioned. 4. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a transistor having a source, a drain region, and a gate electrode on the semiconductor substrate; Depositing a ferroelectric film, depositing a conductive film on the ferroelectric film, processing the conductive film,
A method of manufacturing a semiconductor device, comprising a step of applying a desired voltage to the electrode and polarizing the ferroelectric film in a direction to increase an inversion voltage after the electrode is formed. 5. The method for manufacturing a semiconductor device according to claim 4, wherein a time sequence of the steps is changed. 6. The method of manufacturing a semiconductor device according to claim 1, wherein after the step of forming a transistor having a source, a drain region, and a gate electrode on the semiconductor substrate, After depositing a ferroelectric film, depositing a conductive film on the ferroelectric film, applying a desired voltage to the conductive film, and polarizing the ferroelectric film in a direction to increase the inversion voltage, A method for manufacturing a semiconductor device, comprising a step of processing a conductive film to form the electrode. 7. The method for manufacturing a semiconductor device according to claim 6, wherein a time sequence of the steps is changed.