JP2940034B2 - Charge transfer device and method of manufacturing the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a charge transfer device, and more particularly, to a structure of a channel stop region that defines a charge transfer region of a charge transfer device.

[Prior Art] FIG. 5 is a cross-sectional view of a conventional buried channel type charge transfer device. As shown in the figure, an n-well region 2 constituting a charge transfer region is provided in a surface region of a p-type semiconductor substrate 1, and on both sides of the n-well region 2.
A p ⁺ type channel stop region 3a is provided. Also,
A gate electrode 5 is provided on the surface of the semiconductor substrate via gate oxide film 4 so as to cover n-well region 2.

In the charge transfer device having such a structure, by appropriately applying an appropriate transfer pulse to the plurality of gate electrodes 5 sequentially, the potential depression (potential well) formed in the n-well region 2 is sequentially moved. The signal charges input into the n-well region can be moved together with the movement of the potential well. In this case, in the p ⁺ -type channel stop region 3a, since this region is a region in which p-type impurities are doped at a high concentration, a voltage applied to the gate electrode 5 causes a potential on the surface of this region. No depression occurs. Therefore, the charge transfer region can be electrically separated from other regions by the p ⁺ type channel stop region 3a.

[Problem to be Solved by the Invention] In a solid-state imaging device or the like using a plurality of charge transfer devices in parallel, it is required to increase the density of the device in order to improve the resolution. It is necessary to reduce the width of the charge transfer region and the channel stop region. Therefore, in order to reduce the channel stop region without deteriorating the channel stop function, the impurity concentration in the region must be increased.
However, as the impurity concentration in the channel stop region is increased, crystal defects are induced, so that the characteristics of the element are deteriorated due to an increase in leak current, an increase in noise signal, and the like.

Further, an increase in the concentration of the channel stop region causes a decrease in the effective channel width of the charge transfer region. The reason is,
As shown in the substrate surface potential diagram of FIG. 6, the potential on both sides of the n-well region is raised by the p ⁺ -type channel stop region. However, when the impurity concentration of the channel stop region increases, the potential of the n-well region becomes higher. This is because the wells that are lifted up and formed therein become shallower.

The ratio of the effective channel width to the n-well region is:
It decreases as the width of the n-well region decreases. Therefore, as described above, when the density of the element is increased and the width of the n-well region is reduced, the effect of the higher concentration of the channel stop region is apt to be exerted, the effective channel width is reduced, and the charge is reduced. The transferable charge amount of the transfer device decreases.

[Means for Solving the Problems] A charge transfer device according to the present invention includes a channel stop region formed on a surface of a semiconductor substrate and a channel region (charge transfer region) separated by the channel stop region. The stop region is composed of a portion having a relatively low impurity concentration in contact with the charge transfer region and a portion having a high impurity concentration other than the portion, and the low impurity concentration portion is made deeper than the high impurity concentration portion. I have.

The method for manufacturing a charge transfer device according to the present invention includes the steps of: a. Forming a thin first silicon oxide film on a main surface of a first conductivity type semiconductor substrate, and forming a silicon nitride film on the first silicon oxide film; B. Selectively etching away the silicon nitride film to form an opening having a predetermined width in a region surrounding a second conductivity type well to be formed in the future; c. The silicon nitride film Forming a low-impurity-concentration channel stop region by ion-implanting a first conductivity type impurity into the main surface at a low concentration using the mask as a mask; d. Forming a second silicon oxide film on the main surface Forming a sidewall film made of a second silicon oxide film on a side surface of the silicon nitride film by etching back; e. Using the silicon nitride film and the sidewall film as a mask, forming a first conductivity type on the main surface. The impurity is ion-implanted at a high concentration, and the low impurity concentration channel is implanted. Forming a high impurity concentration channel stop region in the stop region; f. Forming a third silicon oxide film on the main surface and exposing the surface of the silicon nitride film to expose the third silicon oxide film; Embedding the silicon oxide film in the opening, g. Removing the silicon nitride film by etching, h. Forming a resist film so as to cover the third silicon oxide film, i. Using a resist film and the second and third silicon oxide films as masks, ions of a second conductivity type are ion-implanted to form the first and second silicon oxide films in a region surrounded by the second and third silicon oxide films.
Forming a second conductivity type well in the surface region of the conductivity type semiconductor substrate.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing one embodiment of the present invention. In this figure, the same parts as those of the conventional example of FIG. 5 are denoted by the same reference numerals, and the duplicate description will be omitted. The difference between this embodiment and the conventional example is that the channel stop region formed on the surface of the semiconductor substrate has a p-type channel stop region 6 in contact with the n-well region 2 which is a charge transfer region, The point is that it has a double structure with the p ⁺ -type channel stop region 3 having a higher impurity concentration than this region formed in conformity.

Next, the manufacturing method of the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 2A, a p-type semiconductor substrate 1 is formed.
A thin silicon oxide film 7 is formed to a thickness of about 50 nm on the surface of the substrate, and a nitrogen silicon film 8 is grown thereon to a thickness of about 100 nm. The silicon nitride film 8 is patterned so as to open a channel stop formation portion, and boron is ion-implanted at a dose of about 5 to 10 × 10 ¹² / cm ² to form a p-type channel stop region 6.

Next, as shown in FIG. 2 (b), a silicon oxide film 9 having good covering properties is grown to a thickness of about 100 nm by using a high-temperature low-pressure chemical vapor deposition method. Subsequently, when the silicon oxide film 9 is etched by the anisotropic RIE method, a side wall silicon oxide film 9a is formed on the side wall of the silicon nitride film 8 as shown in FIG. In this state, further dose boron 5-10 ×
A p ⁺ -type channel stop region 3 is formed by ion implantation at about 10 ¹³ / cm ² .

Next, a silicon oxide film 10 is grown to a thickness of about 200 nm and etched by the RIE method. As shown in FIG. 2E, the silicon oxide film 9a is formed between the patterns of the silicon nitride film 8. , 10 can be embedded.

Next, as shown in FIG. 2 (f), the silicon nitride film 8 is removed with an etching solution having a high selectivity to the silicon oxide film.
After patterning the photoresist 11, phosphorus is ion-implanted to form the n-well region 2.

Finally, the silicon oxide films 7, 9a, and 10 are removed with an etchant, and a gate oxide film 4 is formed by a thermal oxidation method.
Is formed, the device shown in FIG. 1 can be obtained.

As described above, since the p ⁺ -type channel stop region 3 is separated from the n-well region, it can be a region having a sufficiently high impurity concentration without bothering the problem of an increase in leakage current to the channel region. it can. Therefore,
Even if the width of the p ⁺ type channel stop region is reduced, the necessary channel stop function can be maintained. In this case, since the width of the p ⁺ type channel stop region 3 is regulated by the thickness of the side wall silicon oxide film 9a if the above-mentioned manufacturing method is used, the width is set extremely small to a size less than the limit of the lithography technique. be able to. Furthermore, according to the above-described manufacturing method, the n-well region 2 can be formed in a self-aligned manner with respect to the channel stop regions 3 and 6, so that its dimensions can be accurately controlled.

Further, in the charge transfer device having the above structure, the n-well region has p ⁺
Since it is not in contact with the mold channel stop region, the effective channel width is not reduced.

FIG. 3 is a sectional view showing another embodiment of the present invention.
In this embodiment, the p-type channel stop region 6a is formed deep and surrounds the n-well region 2 and the p ⁺ -type channel stop region 3. Also in this embodiment, n
Since the well region is in direct contact with the p ⁺ -type channel stop region 3, the same effect as in the previous embodiment can be obtained, and a higher smear reduction effect can be expected as compared with the previous embodiment. .

Next, the manufacturing method of the present embodiment is described with reference to FIGS.
This will be described with reference to FIG.

First, as shown in FIG. 4 (a), the p-type semiconductor substrate 1
A thin silicon oxide film 7 is formed to a thickness of about 50 nm on the surface, and a nitrogen silicon film 8 is deposited thereon to a thickness of 100 nm. The silicon nitride film 8 is patterned so as to open at the locations where the channel stop region and the n-well region are to be formed, ion-implanted, and then heat-treated to form the p-type channel stop region 6a.

Next, as shown in FIG. 4B, a polysilicon film 12 is deposited to a thickness of 100 nm, and is patterned so as to remain in a portion where an n-well region is to be formed.

Next, as shown in FIG. 4C, a side wall silicon oxide film 9a is formed on the side walls of the silicon nitride film 8 and the polysilicon film 12 by deposition of a silicon oxide film and anisotropic etching. Then, using these films as a mask, boron ions are implanted.
The p ⁺ type channel stop region 3 is formed.

Next, as shown in FIG. 4D, the voids between the side wall silicon oxide films are filled with the silicon oxide film 10 by the deposition of the silicon oxide film 10 and anisotropic etching. Subsequently, the silicon nitride film 8 and the polysilicon film 12 are removed by wet etching, and a necessary portion is covered with a photoresist 11, and then ion implantation is performed to form an n-well region 2.

Finally, the photoresist 11 and the silicon oxide films 7, 9a,
If the gate oxide film 4 and the gate electrode 5 are formed by removing the layer 10, the charge transfer device shown in FIG. 3 can be obtained.

[Effects of the Invention] As described above, the present invention provides a p-type channel stop region having a relatively low impurity concentration between a well region and a p ⁺ -type channel stop region that constitute a charge transfer region of a charge transfer device. Since the n-well region is interposed, the n-well region does not directly contact the p ⁺ -type channel stop region, so that the potential rise at the boundary of the n-well region is eliminated. Therefore, the effective channel region does not become narrower as in the case of the conventional example shown in FIG. 6, and the effective channel region width can be increased substantially equal to the n-well region width. Then, the width of the effective channel region for accumulating the signal charge is not reduced with respect to the n-well region.
A large transferable charge amount can be secured, and the transferable charge amount of the charge transfer device is significantly increased compared to the conventional type by reducing the effect of the short channel effect that becomes apparent with miniaturization and high density. Can be increased. In addition, there is an effect that the influence of crystal defects is eliminated at the boundary of the n-well region. Therefore, according to the present invention, the impurity concentration of the p ⁺ -type channel stop region can be sufficiently increased, and the required channel stop function can be maintained even if the size is reduced. Therefore, when the charge transfer device of the present invention is used for a fixed imaging device, high density and high image quality can be achieved without increasing the chip area.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention, FIGS. 2 (a) to 2 (f) are sectional views for explaining a manufacturing process thereof, and FIG. 3 is another embodiment of the present invention. Sectional view showing an example, fourth
5 (a) to (d) are cross-sectional views for explaining the manufacturing process, FIG. 5 is a cross-sectional view of a conventional example, and FIG. 6 is an operation explanatory diagram thereof. 1 ... p-type semiconductor substrate, 2 ... n-well region, 3 ... p ⁺
Channel stop region, 4 ... gate oxide film, 5 ...
Gate electrode, 6, 6a... P-type channel stop region,
7, 9, 10: silicon oxide film, 9a: sidewall silicon oxide film, 8
... silicon nitride film, 11 ... photoresist, 12 ... polysilicon film.

Claims (2)

(57) [Claims] A charge transfer region is provided in a semiconductor substrate of a first conductivity type surrounded by a channel stop region of a first conductivity type, and a charge transfer electrode is provided on the charge transfer region via an insulating film. In the charge transfer device, the channel stop region has a double structure of a high impurity concentration channel stop region and a low impurity concentration channel stop region having a depth greater than the depth of the high impurity concentration channel stop region. A charge transfer device, wherein a portion of the channel stop region that is in contact with the charge transfer region is a low impurity concentration channel stop region. A. Forming a thin first silicon oxide film on a main surface of a first conductive type semiconductor substrate, and forming a silicon nitride film on the first silicon oxide film; b. Selectively etching away the silicon film to form an opening having a predetermined width in a region surrounding the second conductivity type well to be formed in the future; c. Forming a second opening on the main surface using the silicon nitride film as a mask; Forming a low impurity concentration channel stop region by ion-implanting one conductivity type impurity at a low concentration; d. Forming a second silicon oxide film on the main surface and etching back the silicon nitride film; Forming a sidewall film made of a second silicon oxide film on the side surface of the film; and e. Ion-implanting a first conductivity type impurity into the main surface at a high concentration using the silicon nitride film and the sidewall film as a mask. Thus, the high impurity concentration channel is located in the low impurity concentration channel stop region. Forming a flannel stop region; and f. Forming a third silicon oxide film on the main surface, etching back to expose the surface of the silicon nitride film and opening the third silicon oxide film to the opening. Burying the silicon nitride film by etching; h. Forming a resist film so as to cover the third silicon oxide film; i. Forming the resist film and the second and third silicon oxide films; Using the third silicon oxide film as a mask, an impurity of a second conductivity type is ion-implanted to form the first silicon oxide film in the region surrounded by the second and third silicon oxide films.
Forming a second conductivity type well in a surface region of the conductivity type semiconductor substrate.