JPS6037249U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6037249U
JPS6037249U JP1983129572U JP12957283U JPS6037249U JP S6037249 U JPS6037249 U JP S6037249U JP 1983129572 U JP1983129572 U JP 1983129572U JP 12957283 U JP12957283 U JP 12957283U JP S6037249 U JPS6037249 U JP S6037249U
Authority
JP
Japan
Prior art keywords
heat sink
semiconductor element
semiconductor equipment
resin material
bent part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983129572U
Other languages
Japanese (ja)
Inventor
繁 清水
Original Assignee
関西日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 関西日本電気株式会社 filed Critical 関西日本電気株式会社
Priority to JP1983129572U priority Critical patent/JPS6037249U/en
Publication of JPS6037249U publication Critical patent/JPS6037249U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Cooling Or The Like Of Electrical Apparatus (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示す横断面図、第　　　′
２図は第１図の側断面図、第３図は樹脂材による　。 モールド被覆方法を説明するための側断面図、第４図は
本案の他の実施例を示す側断面図である。 図中、１は放熱板、１ａは表面、１ｂは裏面、２は屈曲
部、３は半導体素子、４はリード、６は樹脂材、７，１
２は樹脂材６の未充填部である。Fig. 1 is a cross-sectional view showing an embodiment of the present invention;
Fig. 2 is a side sectional view of Fig. 1, and Fig. 3 is a resin material. FIG. 4 is a side sectional view for explaining the mold coating method, and FIG. 4 is a side sectional view showing another embodiment of the present invention. In the figure, 1 is a heat sink, 1a is a front surface, 1b is a back surface, 2 is a bent part, 3 is a semiconductor element, 4 is a lead, 6 is a resin material, 7, 1
2 is an unfilled portion of the resin material 6.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 放熱板の表面に半導体素子を固定すると共に、半導体素
子の電極とリードとを電気的に接続し、かつ半導体素子
、放熱板の裏面を含む主要部分を樹脂材にてモールド被
覆したものにおいて、上記放熱板の一部に屈曲部を、表
面側に突出するように形成すると共に、それの裏面側に
樹脂材の未充填部を形成したことを特徴とする半導体装
置。A semiconductor element is fixed to the surface of a heat sink, the electrodes and leads of the semiconductor element are electrically connected, and the main parts including the semiconductor element and the back surface of the heat sink are molded and coated with a resin material. 1. A semiconductor device characterized in that a bent part is formed in a part of a heat sink so as to protrude toward the front side, and an unfilled part of a resin material is formed on the back side of the bent part.
JP1983129572U 1983-08-22 1983-08-22 semiconductor equipment Pending JPS6037249U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983129572U JPS6037249U (en) 1983-08-22 1983-08-22 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983129572U JPS6037249U (en) 1983-08-22 1983-08-22 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS6037249U true JPS6037249U (en) 1985-03-14

Family

ID=30293549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983129572U Pending JPS6037249U (en) 1983-08-22 1983-08-22 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6037249U (en)

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