JPS603126A - Formation of insulating layer - Google Patents
Formation of insulating layerInfo
- Publication number
- JPS603126A JPS603126A JP11135083A JP11135083A JPS603126A JP S603126 A JPS603126 A JP S603126A JP 11135083 A JP11135083 A JP 11135083A JP 11135083 A JP11135083 A JP 11135083A JP S603126 A JPS603126 A JP S603126A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- substrate
- succession
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 239000001301 oxygen Substances 0.000 claims abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 10
- 239000003990 capacitor Substances 0.000 abstract description 7
- 238000005468 ion implantation Methods 0.000 abstract description 6
- -1 hydrogen ions Chemical class 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 4
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract description 3
- 230000002349 favourable effect Effects 0.000 abstract 1
- 239000001257 hydrogen Substances 0.000 abstract 1
- 229910052739 hydrogen Inorganic materials 0.000 abstract 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 10
- 229910052715 tantalum Inorganic materials 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 241001092070 Eriobotrya Species 0.000 description 2
- 235000009008 Eriobotrya japonica Nutrition 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 210000004907 gland Anatomy 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、電極膜の内部に絶縁層をうめこみ形成する方
法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of embedding and forming an insulating layer inside an electrode film.
従来、容量の形成は、半導体もしくはｉｔ体などの基板
表面に、又は也惧層を表面に設けた半導体もしくは絶縁
体基板辰面に、杷線繰を形成し、次いで該絶に、膜表面
に亀儒を形成することによ９行われていた。即ち、基板
表面に絶は腺、−毬を順次つみ重ねることにより形成さ
れていた。Conventionally, to form a capacitor, a loquat wire is formed on the surface of a substrate such as a semiconductor or an IT body, or on the bottom surface of a semiconductor or insulator substrate with a layer provided on the surface, and then a layer is formed on the surface of the film. It was carried out in 9 by forming Kame Confucianism. That is, it was formed by sequentially stacking glands and balls on the surface of the substrate.
本発明は、かかる従来法とは全く異る手法を用いて容量
を形成する手法を提供するものでめり、その要旨は、Ｔ
ａｚ Ｔ Ｉ ％ Ａｌ／などの金属膜、又は多結晶
シリコンなどの電極膜の表面〃・らば素、窒素などのイ
オンをイオン打込みすることにより、当該金属膜又は電
極膜の内部に絶縁層をうめこみ形成するものである。The present invention provides a method of forming a capacitor using a method completely different from such conventional methods, and the gist thereof is as follows:
az T I % The surface of a metal film such as Al/ or an electrode film such as polycrystalline silicon - An insulating layer is formed inside the metal film or electrode film by implanting ions of rubber, nitrogen, etc. It forms a bulge.
以下、本発明を用いて容量を形成する工程を実施例を用
いて詳細に説明する０
第１図は、本発明を用いて容量を形成する一実施例を示
しており、その製作工程を説明するための断面構造を示
している。図において、１は半導体基板、２は絶縁膜、
２５は悪、３は高濃度不純物領域、４．４１．４２、は
１を極、４５は絶縁膜、５として金属タンタルを用いる
こととして工程を１１１４を追って説明する。１ず、−
４心型を有するシリコン基板１の表面に、ＳｉＯ□なと
の絶縁膜２を設け、続いて当該絶縁膜２の一部を選択除
去し窓２５を形成する（第１図ａ）。Hereinafter, the process of forming a capacitor using the present invention will be explained in detail using an example. FIG. 1 shows an example of forming a capacitor using the present invention, and the manufacturing process will be explained. It shows the cross-sectional structure for In the figure, 1 is a semiconductor substrate, 2 is an insulating film,
The process will be explained in accordance with step 1114, assuming that 25 is a bad region, 3 is a high concentration impurity region, 4, 41, and 42 are poles, 45 is an insulating film, and metal tantalum is used as 5. 1zu, -
An insulating film 2 made of SiO□ is provided on the surface of a four-core silicon substrate 1, and then a portion of the insulating film 2 is selectively removed to form a window 25 (FIG. 1a).
次に、絶縁膜２をマスクとして窓２５からシリコン基板
１０表面に不純物を導入し、該基板】と逆の導屯型全市
する不純物領域３を形成し、続いてタンタル１換４を真
空蒸着法などの手段ｒ用いて形成する（第Ｊ図ｂ）。自
該不７１屹物の導入は、熱拡散法を用いても、あるいは
イオン打込法を用いても良く、その蔵択は自由である。Next, using the insulating film 2 as a mask, impurities are introduced into the surface of the silicon substrate 10 through the window 25 to form an impurity region 3 having a conductive shape opposite to that of the substrate. (Fig. Jb). The material may be introduced by thermal diffusion or by ion implantation, and the choice is free.
該７′踏部領域３は覗甑として用いるため、高凝度に形
、す・必要がある。また、タンタル族４はその−２分は
電極としても用いるため、厚く形成される必要がめｐｌ
その好ましい厚さは０３〜０．６ミクロンである。Since the 7' tread area 3 is used as a peephole, it needs to be shaped with high precision. In addition, because the tantalum group 4 is used as an electrode, it needs to be formed thickly.
Its preferred thickness is 0.3 to 0.6 microns.
次に、当該膜４に、酸素イオン５がイオン打込みされ、
続いて、−Ｉ不活性ガス雰囲気中で熱処理することによ
シ当該膜４の内部にＴａ２Ｏ，Ｎ４５が形成される（第
１図Ｃ）。当該イオン打込みは、Ｔａ２鵠膜４５が前記
タンタル族４の内部に形成されるようにまたＴａ２（Ｊ
６の組成となるように５＋：π１−を迅ぶ必要があシ、
その好ましい条件１−を電圧が５０〜１５０ＫｅＶ、打
込み量が１０′−１０ｃＩｎである。当該イオン打込み
によυ５００〜１５００ オングストロームの膜厚のＴ
ａ２０５膜が形成される。かかる条件で当該Ｔａ２０５
膜に接して上側にタンタル膜４２１Ｘ−ト側にタンタル
膜４１が炊シ、これら膜は電極として利用される。Next, oxygen ions 5 are implanted into the film 4,
Subsequently, Ta2O and N45 are formed inside the film 4 by heat treatment in a -I inert gas atmosphere (FIG. 1C). The ion implantation is also carried out with Ta2 (J
It is necessary to accelerate 5+:π1- so that the composition becomes 6,
The preferable condition 1- is that the voltage is 50 to 150 KeV and the implantation amount is 10' to 10 cIn. The ion implantation results in a film thickness of υ500 to 1500 angstroms.
A205 film is formed. Under these conditions, the Ta205
A tantalum film 421 is placed on the top side in contact with the membrane, and a tantalum film 41 is placed on the top side, and these films are used as electrodes.
イオン打込み後の熱処理はＡｒ、Ｎ２Ｈｅなどの不活性
ガス雰囲気中で７０υ〜９００°Ｃで行うのが好ましい
。The heat treatment after ion implantation is preferably performed at 70υ to 900°C in an inert gas atmosphere such as Ar or N2He.
当該雰囲気中に微霊の酸素、水分が含まれていた場合に
は、タンタル１極４２の表面が劇化されるため、当該電
極４２が薄くなるなど好ましい結果が得られない。かか
る時は、イオン打込みの前にもしくはイオン打込みの後
にＳ ｉ ０２などの絶縁膜を前記タンタル膜４の表面
に設け、タンタル膜を面にマスク拐料を設け、選択的に
行っても良い。If the atmosphere contains trace oxygen and moisture, the surface of the tantalum single electrode 42 will become dramatic, resulting in undesirable results such as the electrode 42 becoming thinner. In such a case, an insulating film such as S i 02 may be provided on the surface of the tantalum film 4 before or after the ion implantation, and a masking material may be provided on the surface of the tantalum film.
また、イオン（’］込みの１県に抽板１を加熱せしめ、
熱処理と同時に行っても良くその選択は自由でるる・
次にタンタル膜４２を選択的に除去し、電極ノく極４１
はこのあとの工程で選択的に除去しても良いし、Ｉたけ
第１図（ｂ）でタンタル膜４が形成された佐に選択的に
除去しておいても良くその選択は自由である。当該実施
例では、タンタル族４１と高濃度不純物領域３とはオー
ム接地であるため、該不純物領域３と電極４２との１ｉ
ｊ１に電圧を印加することで容量として動作させること
かでさる特長を持つ。Also, heat the drawing plate 1 in one prefecture including ion ('),
It may be performed at the same time as the heat treatment, and the selection is free. Next, the tantalum film 42 is selectively removed, and the electrode 41 is removed.
may be selectively removed in a subsequent step, or may be selectively removed after the tantalum film 4 is formed as shown in FIG. 1(b), and the choice is free. . In this embodiment, since the tantalum group 41 and the high concentration impurity region 3 are ohmic grounded, the 1i between the impurity region 3 and the electrode 42 is
It has a special feature in that it operates as a capacitor by applying a voltage to j1.
上記した実施例では、電＆４としてＴａを用い絶縁膜４
５としてＴａ２０５をを形成することとして説明したが
、該電極４として他の金属例えばＡ、ｇ、Ｍｇ、 ’Ｉ
’ ｉ、 Ｎ ｂ ｉどを用い絶縁膜４５ トＬテ谷々
ＡＺ、ｏ３、ＭｇＯ，’ｌ’１ｏ２Ｎｂ２０． などを
形成する場曾にも１２本発明は通用できる。さらに亀［
４として不純物をドープしたポリシリコン膜を用い、絶
縁［４５として５ｉｎ２もしくはＳｉ３Ｎ４ を形成す
る場合も本発明は適用できる。In the above embodiment, Ta is used as the electrode &4, and the insulating film 4
Although Ta205 is formed as the electrode 4, other metals such as A, g, Mg, 'I
'i, Nb i, etc. are used to form the insulating film 45. The present invention can also be applied to a field where a structure such as the like is formed. Furthermore, the turtle [
The present invention can also be applied to the case where a polysilicon film doped with impurities is used as 4 and 5in2 or Si3N4 is formed as insulator 45.
第１図は本発明の一実施例を説明するだめの図で各工程
図における半導体装置の概略断面を示す。
図において、１は半樽体基板、２は杷線腺、２５は窓、
３は高濃度不純物領域、４．４１．４２、は電極膜、４
５は絶縁膜、５はイオ／の飛来方向をそれぞれ示す。
第１図
２５
（ｄ）FIG. 1 is a diagram for explaining one embodiment of the present invention, and shows a schematic cross section of a semiconductor device in each process diagram. In the figure, 1 is a half-barrel body board, 2 is a loquat gland, 25 is a window,
3 is a high concentration impurity region, 4.41.42 is an electrode film, 4
Reference numeral 5 indicates an insulating film, and 5 indicates the flying direction of ions. Figure 1 25 (d)
Claims (1)
オン打込みし続いて熱処理を行うこと区より、もしくは
基板を加熱した状態で酸素もしくは璧累をイオン打込み
することによシ、当該眠極膜の内部に絶縁層をうめこみ
形成することを特許とした絶縁層の形成方法、The electrode film formed on the substrate can be ion-implanted with oxygen or nitrogen and then subjected to heat treatment, or by ion-implanting oxygen or nitrogen into the electrode film while the substrate is heated. A patented method for forming an insulating layer by embedding the insulating layer inside the
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11135083A JPS603126A (en) | 1983-06-21 | 1983-06-21 | Formation of insulating layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11135083A JPS603126A (en) | 1983-06-21 | 1983-06-21 | Formation of insulating layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS603126A true JPS603126A (en) | 1985-01-09 |
Family
ID=14558962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11135083A Pending JPS603126A (en) | 1983-06-21 | 1983-06-21 | Formation of insulating layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS603126A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6816355B2 (en) | 2001-09-13 | 2004-11-09 | Seiko Epson Corporation | Capacitor, semiconductor device, electro-optic device, method of manufacturing capacitor, method of manufacturing semiconductor device, and electronic apparatus |
| JP2008273230A (en) * | 2007-04-25 | 2008-11-13 | Toyota Motor Corp | Vehicular seat |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5331971A (en) * | 1976-09-06 | 1978-03-25 | Nippon Telegr & Teleph Corp <Ntt> | Forming method of metal oxide film or semiconductor oxide film |
| JPS54153575A (en) * | 1978-05-25 | 1979-12-03 | Seiko Instr & Electronics Ltd | Manufacture for semiconductor device |
| JPS556291A (en) * | 1978-06-26 | 1980-01-17 | Contraves Ag | Digital interporation system for three pahse analog signal period |
-
1983
- 1983-06-21 JP JP11135083A patent/JPS603126A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5331971A (en) * | 1976-09-06 | 1978-03-25 | Nippon Telegr & Teleph Corp <Ntt> | Forming method of metal oxide film or semiconductor oxide film |
| JPS54153575A (en) * | 1978-05-25 | 1979-12-03 | Seiko Instr & Electronics Ltd | Manufacture for semiconductor device |
| JPS556291A (en) * | 1978-06-26 | 1980-01-17 | Contraves Ag | Digital interporation system for three pahse analog signal period |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6816355B2 (en) | 2001-09-13 | 2004-11-09 | Seiko Epson Corporation | Capacitor, semiconductor device, electro-optic device, method of manufacturing capacitor, method of manufacturing semiconductor device, and electronic apparatus |
| JP2008273230A (en) * | 2007-04-25 | 2008-11-13 | Toyota Motor Corp | Vehicular seat |
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