JPS6028388B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to an integrated circuit device having a buried collector layer.

Conventionally, a collector layer or an inter-element isolation layer is formed,
Furthermore, the structure of an integrated circuit device using the so-called epitaxial diffusion method, in which an element is formed in an epitaxial layer provided on a high-resistance semiconductor substrate, is known for the purpose of improving the electrical characteristics of the element.

However, according to this structure, the epitaxial layer has
Defects such as crystal dislocations occur at a high density, and damage to the photomask due to protrusions of several mm such as mounts and bits formed on the surface of the epitaxial layer is rarely transferred as is onto the substrate. Therefore, it was difficult to improve walking speed. SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit device that eliminates the above-mentioned drawbacks.

The present invention is characterized in that an element is formed on the other main surface layer of a semiconductor substrate having an epitaxial layer on one main surface, and the epitaxial layer is used only for forming the collector buried layer.

Next, a description will be given with reference to the drawings. 1 to 5 are cross-sectional views showing an embodiment of the present invention in the order of steps. First, an oxide film 3 with a thickness of approximately 1 French meter is formed on one principal surface 2 of a single-crystal n-type silicon substrate 1. A predetermined portion is selectively removed, and an n-type impurity such as antimony is diffused to a depth of several meters from the main surface 2 to form an n+ collector buried layer 4 with a high impurity concentration. During the impurity diffusion, an oxide film 3' having a thickness of about 0.2 to 0.3 m is formed on the n+ diffusion layer 4 (FIG. 1).
Thereafter, when the oxide film 3' is removed, the oxide film 3 remains with a thickness of 0.7 to 0.8 rm.

Next, the silicon substrate surface of the exposed n+ diffusion layer 4 is etched by 1 to 2 Am with a nitric acid-hydrofluoric acid based etching solution, and the oxide film 3 is completely removed, thereby removing the n+ diffusion layer 4 on the silicon substrate 1. Since the surface 2' is recessed from the main surface 2 by about 1 to 2 meters, a pattern step 4' of the n+ diffusion layer 4 is formed at the boundary between the silicon surfaces 2 and 2' (see Fig. 2). ). Subsequently, the silicon substrate surfaces 2 and 2' are treated with high-temperature hydrogen chloride gas, and then 200 to 300 A P-type silicone epitaxial layer 5 having a thickness of 1.5 m is formed. In this process, the pattern step 4' shown in FIG.
does not disappear by treatment with hydrogen chloride gas,
A pattern step 5' is then formed on the main surface 6 of the epitaxial layer 5 at a position corresponding to 4'. next,
The other main surface 7 of the n-type silicon substrate 1 is etched using an etching solution using a hydrofluoric acid-nitric acid type chemical or gas plasma of a mixed gas of freon gas and oxygen, and then mechanically precision polished to form an n-type silicon substrate 1. The mold silicon substrate 1 is thinned to a desired thickness of several to several tens of mm (FIG. 3). Next, the P-type impurity is diffused from a predetermined portion of the other main surface 7' of the n-type silicon substrate until it reaches the P-type epitaxial layer 5, thereby forming the element isolation layers 8, 8' and 8^. form (Figure 4).

At this time, the alignment between the element isolation layers 8, 8' and 8'' and the n+ collector buried layer 4 is achieved by using red light or near-infrared light with a wavelength of 0.7 to 0.9 rm as a light source during masking. For example, there is no problem because the pattern step 5' formed by the n+ buried layer 4 on the epitaxial layer surface 6 can be easily seen through the n-type silicon substrate 1 and the p-type epitaxial layer 5.Finally, the n-type silicon substrate P-type impurity layers 9, 9' and n-type impurity layers 10, 10' are sequentially formed on the other main surface 7' of 1 to form a P-type resistance layer and an npn
The process is completed by forming elements such as transistors (Fig. 5).

According to the present invention, since all the elements such as transistors and resistors are formed on the other main surface of the semiconductor substrate on which the epitaxial layer is formed on one main surface, the diffusion method is applied to the secondary epitaxial layer. Compared to integrated circuit devices in which elements are formed using the same method, the yield is lower due to the fact that there are no chip defects caused by damage to the photomask due to crystal defects, mounts on the surface of the epitaxial layer, or protrusions such as bits. Significantly improved.

Furthermore, since a buried collector layer is formed as in the conventional case, the electrical characteristics of the transistor, such as high frequency and high output, are not impaired at all.

As described above, the present invention is extremely effective in providing an integrated circuit device with high reliability by forming an element group on the other main surface of a semiconductor substrate having an epitaxial layer formed on one main surface. It is.

[Brief explanation of the drawing]

1 to 5 are cross-sectional views showing an embodiment of the present invention in the order of steps. 1... N-type silicon substrate, 2... One main surface of n-type silicon substrate, 2'... Surface of n+ collector buried layer, 3, 3'... Oxidation Membrane, 4...
n+ collector buried layer, 5...P type epitaxial layer,
4', 5'... Pattern step of n+ collector buried layer 4, 6... Surface of P-type epitaxial layer 5, 7, 7'...
...to the other main surfaces of the n-type silicon substrate, 8, 8', 8.
. . . Inter-element isolation layer, 9, 9' . . . P-type impurity layer, 10, 10' . . . N-type impurity layer. Code map Z map Winter map group 4 Leopard map

Claims (1)

[Claims] 1. A step of introducing an impurity of the same conductivity type into one main surface of a semiconductor substrate of one conductivity type to form a buried layer and removing a small portion of the surface of the buried layer to form a step; forming an epitaxial layer of opposite conductivity type on the main surface, and using a step on the surface of the epitaxial layer formed based on the step of the substrate as an alignment mark from a predetermined location on the other main surface of the substrate; A semiconductor device comprising the steps of: forming an inter-element isolation layer that reaches the epitaxial layer by introducing impurities of opposite conductivity type; and forming an element group on the other main surface of the substrate. Production method.