JPS60257668A - Encoder for compression code - Google Patents

Abstract

PURPOSE:To eliminate synchronizing shift of decoding operation by fetching the next compression code after the end of reproduction of decoded data. CONSTITUTION:The compression code from a recording circuit 101 is head- located via a multiplexer 102 and fetched to a register 103. Then the code is decoded a decode logic 104 and a code table ROM105 and the run length is set to a run length counter 108. A reproducing signal is outputted from an FF109 to a printer 111 in response to the value of the counter 108. The next compression code is fetched to the register 103 after the end of reproduction of the preceding decoded data. Then the synchronizing shift of the decoding is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a decoding device for compressed codes using band compression encoding used for facsimiles, image electronic files, and the like.

Conventional image transmission devices such as facsimiles and recent semi-transmission devices:
By compressing image data and handling it,
The aim is to reduce the amount of data and increase the speed and efficiency of transmission or storage operations.

Such image compression is a type of so-called code conversion operation, and is a typical compression method, Modified Hoffman (MH)/? Regarding f-coding, bit blocks of continuous white or black pixels in an image are expressed in correspondence with different compression codes. At this time, pixel focus blocks with a high frequency of occurrence are associated with a compression code with a short code length, while pixel bit blocks with a low frequency of occurrence are associated with a compression code with a long code length. This method utilizes the bias in the frequency of occurrence of the combinations to express the entire image using a different code string with a smaller number of hits.

Incidentally, the correspondence of compressed codes to pixel bit blocks is determined based on empirical rules, and the coat lengths of the compressed codes are irregular.

Furthermore, since the number of pixels each encoded code represents differs, the image reproduction time corresponding to the encoded code also differs. Therefore, it is difficult to obtain the timing for inputting the encoded code to be decoded next into the decoding circuit. However, for example, if a printer or the like that cannot be driven intermittently is used as an image reproducing device, the decoding circuit must supply decoded data to the printer without interruption, and decoding of continuous encoded codes also corresponds to this. There is a need to.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a compressed code decoding device that adapts the capture and decoding of the compressed code to be decoded to the playback operation and enables high-speed decoding processing. .

/ /′ / /// / / /// -7 / A detailed description of the invention follows.

First, an outline of an embodiment of the present invention will be explained using the circuit block diagram shown in FIG. 1. In FIG. This method is obtained by compressing and encoding an image signal using a separate means, which is input from a receiver that receives image information via a transmission path such as a telephone line. A circuit that stores MH (Modified Hoffman) codes in a 16-bit (1A standing word) single Z format that can be read out sequentially, and can be realized by, for example, RAM, (random access memory), or a latch circuit. It is. Furthermore, the storage format of MW Coco in the memory circuit 101 is shown in FIG.
An example is shown in a). That is, as MH Coco is an original broker, the code lengths are not uniform (minimum 2 bits to maximum 15 bits), but regardless of the code length, there is no blank bit, and the serial code is not uniform as shown in Figure 2 (b). This is a format in which a series of bit strings are converted and arranged in parallel every 16 bits.

, In FIG. 2(b), WB and DB are MH codes indicating white and black pixels, respectively, and the numbers after WB and BB indicate the run lengths indicated by the codes.For example,
This is MH Coco showing white with WB84'i run length 8. In this format, MH Coco's delimiter and word (1
It does not necessarily match the 6-bit) delimiter. or,
The memory circuit 101 has a function of sequentially outputting subsequent words in parallel depending on external control.

In FIG. 1, 102 is a so-called multiplexer (data processor). It is also a register having 103 28-bit parallel inputs and outputs, and the memory circuit 101
from, via multiplexer 102, to register 103.
Temporarily store MH coco in input 111 of 4
1! The Ml code decode logic 104 and the MH coco decode table ROM (to be described later) output the function and the MH coco already stored in the register 103.
(read-only memory) 105, etc.

The multiplexer 102 and the register 103 form a so-called bit shifter capable of 7-real shifting and n-bit jump shifting of data. This bit
The shifter is MU Coco Decode Logic 10, which will be described later.
4 and the output of the MH code decode ROM 105, etc., and by the method described above, the memory times @ 101 are stored in the register 103 regardless of the boundaries of the MH code.
It functions to shift and store the lAH code stored in the memory by the necessary number of bits. FIG. 5 (details will be described later) is a diagram showing the detailed configuration of this bit shifter, and the MH code string exemplified in the register 105 is the MH code exemplified in the storage circuit 101 shown in FIG. is moved into register 103 through appropriate controls,
Furthermore, M, HD-do WBI (
10011) is at a position where it can be decoded. That is, the output C! of the register 103 shown in FIG. That is, the LSB output is called Ml (the state in which the first bit of the code is output is the decodable position, and the next one is completed.) Therefore, the code arrangement in the register 105 in FIG. 3 is a white run length. MH code WB indicating 8
8 indicates that the state is "cueing completed".

In FIG. 1, there are 104 MH code decode logics (hereinafter referred to as logic 104), and the run length of the MH code is shorter than the code length of the M'H code. That is, the white run length j
(MU Coco 000111, code length = 6> gin length = 1), white 2 length 2 (Mul code 01
11, K) 'Length = 4 > ? length = 2),
White run length 5 (Ml (1000 in code, code length = 4> run length = 3) and black run length 1 (
MHL code 010, code length = 3> run length = 1
). In addition, in the following explanation, the above-mentioned four types of M, which respectively indicate white run length 1, white run length 2, white run length 3, and black run length 1, will be used.
Hl code together J (So here and save K.

In Figure 1, 105 is MH, code, decode, RO
M (hereinafter referred to as ROM 105), and the above-mentioned logic 104 is in charge of decoding. This is a circuit that mainly decodes all MH codes including the M)l code.

The logic 104 and the ROM 105 are different from each other in MHL code processing speed and method.
Each time these two decoders complete the beginning of one MHL code in the register 103, the MHL code run length, code length, black or white image color, and makeup are classified.・It outputs whether there is an up code or a terminate code, and whether it is present or not.

112#'1EliOL detection circuit, the code for line synchronization in the MU code stored bit serially in the register 105, that is, end of line (BOL)
Detect whether the code exists and its storage location.

In Figure 1, numeral 108 is a run length counter, which is a binary counter that can count from 6"o" to the maximum make-up code run length, Nil, or more than "2560". This run-length counter 108 outputs a count end signal (ripple carry OR of the counter in this example) every time it finishes counting the run length of the M1 code output from the logic 104 or i-iR1-1RO.

It has 109 clips and 70 tubes, and receives the count end signal (ripple signal jJOR) from the aforementioned run length counter 108, and inverts the output each time. However, as will be described later, the output is controlled so as not to be inverted by the count end signal of the make-up code. The output of this flip 70 tube 109 is the memory circuit 1
This is an image signal obtained by decoding the 9MT1 code.

The 107-digit code length counter is a binary counter that can count over 15", which is the maximum code length of the MH code, and can be used to serially shift or jump the MH code that was "!Xi output completed" in register 7 (105). By shifting, the amount of shift is counted and controlled as a decoded code.

It is a 106-bit, 4-bit accumulator.

As described above, once the MHL code taken into the register 103 from the storage circuit 101 has been decoded, it is sequentially flushed out of the register 103, thereby creating an empty bit in the register 103. Therefore, the accumulator 106 counts the number of empty bits in the register 103, and writes a new MHL code every time there are 16 empty bits.
One word (16 bits) is replenished from the f circuit 101 to empty bits in the register 105 in parallel. As a result, the MHL code string applied from the register 103 to the logic 104 or the ROM 105 is controlled so as not to be interrupted, and a high-speed decoding operation can be performed at 0T. This is a diagram illustrating a control circuit that controls input/output signals.

As described above, MH Coco is converted into an image signal, that is, MH
Coco decoding is done. The decoded image signal is supplied to the printer 111, and the image is recorded on the recording material. Note that the printer 111 sends a horizontal synchronization signal HS! which is a synchronization signal for each scan. No is output and used at the timing of this H8YNO decoding operation.

Next, embodiments of the present invention will be described in more detail.

In this embodiment, so-called 1 is used to directly output an image signal that is the result of decoding an image compression code Mucoco to a high-speed printer such as a laser beam printer without providing any image memory. High speed, real time,
MH-decoder. Therefore, ME・
The processing speed of the decoder is high, the image output of the Ml/decoder (in this example, the image frequency is 20-odd MH2) and the high speed of laser beam printers (the problem of synchronization with the Nido printer has been solved). Must be.

Therefore, in order to solve these problems, the desired "high-speed, real-time, Mu,
Realize a decoder.

(1) Synchronization between the MH decoder and the printer is performed using FF0L of the MH coco and a horizontal synchronization signal which is a synchronization signal for each line of the printer.

(2) In the J112 register 105, as a method of sweeping out the MH code that has been decoded with "cueing completed" and shifting the subsequent MH code to the position tR of "cueing completed", depending on the code to be swept out. A specific configuration for achieving these two points using either of the two methods of jump shift and serial/sevento will be described with reference to the drawings.

FIG. 8 is a perspective view showing the structure of an embodiment of the laser beam printer shown in FIG. 1 as an example of the output section.

This printer is based on the Nariko photographic system using Raded light, and 201 is a photosensitive drum rotatably supported in a housing Ha. 202 is a semiconductor Raded that emits laser light IJa. The laser beam is made incident on the beam expander 203, and becomes a laser beam with a predetermined beam diameter. Further, the laser beam is incident on a polygonal mirror 204 having a plurality of mirror surfaces, and the polygonal mirror 204 is rotated at a predetermined speed by a constant speed rotation motor 205. The laser light emitted from the beam expander 203 by the polyhedral mirror 204 is scanned in a substantially horizontal direction. Then, by the imaging lens 206 having f-θ characteristics, the light is imaged as a spot light by the charger 216 onto the photosensitive drum 201 which has a predetermined polarity K[[.

A beam detector detects the laser light reflected by the reflector 207 and 208, and this detection signal determines the timing of the modulation operation of the semiconductor laser 202 in order to provide desired optical information on the photosensitive drum 201. .

A high-resolution static layer latent image is formed on the photosensitive drum 201 by the laser beam that is scanned in 7r15 images on the photosensitive drum 2 . After this latent image is developed by a developing device 209, it is transferred to a recording material stored in either of the cassettes 210 and 211, and when the recording material passes through a fixing device 212, an image is formed. is fixed on the recording material and discharged as a hard copy to a PL output section (not shown).

FIG. 9 shows an embodiment of a printer circuit for modulating the semiconductor laser shown in FIG. 8 with a predetermined image (fi number).

Image signal V that has been decoded and input from the input 4 child factory N
The IDJCO includes a 2P, 1-line buffer 301, and a 22-bit shift register having a number of bits equal to at least the number of pixels for one scan for each group of image signals for one scan.
In buffer 302, buffer switch side leg circuit 30
It is alternately input by Igll(2) of 3.

Furthermore, the image signals input to the second line buffer 301 and the second line buffer 302 are transmitted to the beam detector 604.
The beam detection signal from the laser beam detection signal is read out alternately every scanning minute as a trigger signal, and is applied to the laser driver 505.

Laser driver 305 modulates and controls the semiconductor laser 506 based on the input image signal to control the emission of V'i laser light.

By having two line buffers, while inputting image signals that are input one after another to one of the twin buffers, both image signals already stored in the other line buffer can be sent to the laser driver 505. Since it outputs, it can handle high-speed input of image signals.

The beam detection signal from the beam detector 304 is also transmitted to the decoding processing circuit as a horizontal synchronizing signal H8YNO, and is used for synchronizing the decoding processing and the printer operation as described later.

Note that the image signal decoded in this printer is inputted via a double-buffer configuration consisting of two line buffers, that is, a twelfth in-buffer 301 and a second line buffer 302. Decrypt using this double buffer lattice! :・Persimmon corrective action when there is a mistake in the production.

In other words, the @ image signal signaled by the decoding circuit is stored in one line buffer for 7 days (if an error occurs in the decoding operation, printing operation using the image signal of the current fin with the error is prohibited). , performs a sibling operation using the image signal of the previous line already stored in the other two in-buffers.

As a result, printing is not performed using an image signal that has been erroneously decoded, so that the influence on the reproduced image can be eliminated.

Note that this correction operation will result in images based on the same image signal being duplicated by at least 22 inches; It doesn't affect the image that much.

In FIG. 4, the Ml/code table ROM 105#i shown in the first diagram is actually constructed by a plurality of ROMs (read-only memories). The contents of ROM 105 are schematically explained below, and AD'111. ~AD 15 is the address of ROM105
7th Mizuko, also 0'1J-1j11 ROM 10
Chill at output terminal 5. Format of storage contents of ROM 105 Align the LSB bit of the MH code to be decoded supplied from the 1 inch register 105 to the address terminal ADQ of the ROM 105, and then write each bit of each MH code below.
It is applied sequentially to the address terminals ADl to ADll of the ROM 105 in the SB direction. Address terminal AD13 M
Signal indicating the color of H Coco B/W-1'lOM (Black-
1. Assume that white = \) is given. In addition, MH Coco is 1
If it is shorter than 2 bits, the missing bits are ignored (D
Turn on (3ARff). Also, the EOL code is treated as a makeup code. Also, color bits (ADl5) of makeup codes with run lengths of 1792 or more are ignored (DON'T 0ARJ!i).ROM 10
5, write the contents of the ME coco given each address as the memory data of the address determined above, and send the output corresponding to each M T (code) to the output terminals 00 to 5.
011, that is, output terminal 0'vL is "1" when the decoded EMH code is a makeup code.
, the signal Ml becomes 1-0 when it is a terminate code.
111 times of dryness. The output terminal 61 is the decoded M H
The code is a white code with run length 0 (ootlotof
) or a black code with run length 0 (00001fol
11), it outputs 10, and at other times it outputs a signal TO which is 1-1.

Output terminals 02 to 05) 4-bit output OLD in which the code length (number of bits) of each MH coco is expressed as two's complement.
~Output OLB. The output terminal 05 is L8B of the code length. Output 1 and 1 child 06 to 011 are each Ml (
It outputs 6-bit outputs RLO to RL5 in a two's complement representation of the code run length. However, output terminal 01
1 is a 6 cran length TJEB. J+￥l,
For the make-up code, only the upper 6 bits of the binary representation of the run length are assigned to output terminals 06-011. This is because the make-up code in the 1-bit H code can express its run length using only the upper 6 bits. 402 in Figure 4 shows the outputs O\ to 11 of the ROM j (15) decoded with MH Coco WB8 (10011), which shows white with run length 8, as an example. (Used in this example) MH Coco surface CC engineering TT
YJ! J, LOW-BOOK Faacicle■,
2 ReC, T, 4 TABLJ! i1/'r, 4 and TABIJ 2/T, 4 K. ) 1 in Figure 4
04 is the Ml code decoding logic shown in the first diagram, and in this embodiment, it is a detection logic configured with an AND gate and an OR gate. The H8O signal which is the output of the logic 104 becomes "0" when detecting the H8O code, that is, the MH coco indicating white with run lengths 1, 2 and 3, and the MH coco indicating black with run length 1. 8FQ to SF2 i- to the above four types of MH Coco (H
8O code) is expressed in binary numbers, inverted, and output. , MH Coco White I WBI (00
0111) is decoded.

The operation of the bit footer shown in Figure 3 is explained in Shigeru 1 and Table 2, because the current ROM addressing method cannot sufficiently handle the high-speed processing using a logic circuit for decoding the H8O code. The 9th explanation will be explained with reference to .

FIG. 5 No. 102 is the multiplexer shown in FIG.
tri-state multiplexers 1021 and 10
Consists of 22. When the control input from the accumulator 106 to the multiplexer 102 is "0", the output A7 from the multiplexer 1022f+11 to the register 103
All ~A27 bits become tristate 70-ting and become invalid, and the output Ao~A27 from the multiplexer 1021 side becomes valid in the register 105, and the output Co~027 of the register 103 becomes the multiplexer 1021 bit. Table 1 shows how to select the input signal ao""027 from the register 103 through the input line S port 82.
o=S.

=j, 52=Q, outputs 05 to 0 of register 103
27 are taken in and selectively output as outputs A1 to A2S, respectively.

Next, the allocation to multiplexer 102? When the +11 line @ is "moon," the output An of the multiplexer 102 and the sixth digit fil gl (a) are selectively given to the input lines so~82 from the multiplexer 1021 in the same way as when they are "0". It will be done. Outputs A7-A from multiplexer 102
Of the 27, those other than those indicated by Y in Table 2 are multiplexers 102.
2 side is enabled, and the output A of the multiplexer 1021 side
Among 7 to A27, those other than those indicated by Y in Table 2 are 70-T/G and are invalid. In addition, as shown in Table 2, the outputs A7 to A27 given from the multiplexer 1022 to the register 105 are the input lines Σ0 to Σ2 to the multiplexer 1022.
However, the bit indicated by Y in Table 2 is selected from the multiplexer 1021 side. This Y
The number of is set by controlling the tri-state state of the multiplexer 1o21 by the input lines ST7-5T11 output corresponding to the input lines Σa-Σ2 to the multiplexer 1022. Note that the circuits of multiplexers 1021 and 1022 in FIG.
1, etc.) and a gate circuit. or,
The output selected by the multiplexer 102 as An''-427 as the output to the register 103 is the clock O.
K is latched in the register 103.

The above-mentioned combination constitutes the Bit N7 evening, memory episode 1 101
It is possible to shift an arbitrary number of bits to the MH Coco signal input in six-bit parallel. As a result, M)l chords with uneven chord lengths can be turned into the above-mentioned [starting complete r, 1 state].

/ 27 / /' / / Table 1 Table 2 However, the movement method is the bit shifter 102.
Serial shift and H8 that move one bit at a time, etc.
A jump shift of up to 6 bits occurs when an MH code, which is treated as a 0 code, is detected. That is, the code string in register 103 is controlled so that at most no more than 6 bits can be moved in one clock time.

Therefore, when the EfOL code (000000000001) is moved in register 103, its L8B bit is always in register 103 even if it is moved incorrectly due to the previous progress.
It is C that will appear in O, ~05 of 3.

Now, in general, when decoding ME Coco, it is extremely important to detect the PJOL code due to its code system. The EOL detection circuit 112 shown in the first diagram will now be described in detail.

That is, the EOL code is a delimiter code for each 12'in of the image, and at the same time has the role of indicating the position of the 3J (, Ml code), so when decoding, f
If the f1OL code is detected incorrectly, each subsequent M
The delimitation of the H-coco became unclear, making it impossible to decode one line of both sides, and depending on the detection method used, the gOL of each subsequent image line could no longer be detected, so in the end, the printed image was mostly used. I can do it,') m fd I
This will spread to lj.

bt means that even if the MH code is slightly 8 due to a transmission error etc. in the ME Coco row, the IfiOL detection method that prevents the code from collapsing as much as possible is the electric equipment. It becomes.

The EOL code is reliably detected and the tf error can be recovered within one line.

FIG. 10 is a diagram showing the detailed configuration of the FiEOL detection circuit 112. 12-bit jK as shown in Figure 10)
At least a shiftable sheet Ji of the register 103 at least can be placed so that the TJEIB of the L code (ooooooooooool) can be placed anywhere in the register 103 Co, C5.
iii] 6 types of detection gates 1001 with a ratio of 1υ to 6
are installed in parallel. This prevents failure to detect the J100L code by monitoring the data stored in the register 106. Then, the detection group that detected the BOL code) From 1001, respectively OJI: OL ~ 5g0
An output signal, such as L, indicating the position of the EOL code in the register 103 is output.

With this method, gOL detection will not be erroneously detected unless the 1nOL code itself contains an erroneous bit. Therefore, image code errors can always be recovered within one line. Also, the probability that an erroneous bit is included in a JDOL code is extremely low compared to the probability that an erroneous bit is included in an image code, considering the ratio of the number of bits, and can be ignored in practical terms.

Figure εd11 shows the details of the detection gate for detecting the 1inOL code. As shown in the figure, it is configured to import 12 pit data in parallel, and 11 pit data excluding the MOB.
The bit data is inverted via the GOUTE NV, and the MO
Apply it to Goo 002 (a 12-person NAND game) along with B. As a result, the jflOL code is decoded. Once the EOL code has been decoded, the output of the NAND game 002 becomes low level.

FIG. 10 FOL detection circuit 112 output 01! :Oh
~5 EOL is transmitted to code length counter 107 and accumulator 106. Accumulator 106+
-t This signal causes the register 105 to shift the long code hand of the gOL code.

That is, from the position of the output of the FiOL detection circuit 112 shown in FIG. 10, the register 103 K41! :MOL may already be detected before OL Coco in the autumn period when the MH code or Fill bit still remains.

Therefore, when a signal (other than IEOL, I!; OL coco detection signal, that is, [01 to 5 FiOL) is detected among the EOL codes output by the BOL output output circuit 112, the EOL code in the accumulator 106 register 103 is detected. After the previous residual code is cleared from the register 103 by the aforementioned 77 bits, the code long hand + 4 + 1 of the JeOL code is shifted by 12 bits into the register 105.
let history do it.

As a result, the jUOL code has been swept out, and the state of ``cueing completion'' is reached for the image MH Coco at the beginning of the next line to be number 14. Also, this allows EO that is not image information to
It is also possible to eliminate wasted time due to decoding +9 processing of the L code in the same way as other compressed codes.

Next, see page 9 for details of the entire block diagram shown in FIG. Clarify using Figure @5 etc. Since the operation of the circuit shown in Fig. 5 is complicated, we will set some conditions to make the explanation easier, and we will also explain the basics of the circuit by using the MH Coco decoding operation, which is considered to be common, as an example. The operation will be explained, and then the establishment of the setting conditions will be explained.

Figure 2 (1
)) will be used. The operating principle of this circuit is that before the printer's horizontal periodic signal HEYNO arrives,
IOL Koko iE-+5 appearing ahead of Figure 2(b)
3. The white run length 8 is flushed out of the illustrated register 103 by the bit shift operation described above and is the ME coco (ill) of the first image signal of the line to be decoded from the EOL. MH indicating
Assume that Coco WB 8 is in the register 103 in the state of [Cueing completed - 4] and is waiting for [YNO] from the printer.

FIG. 6 is a time chart of the main parts of the HFJ<s diagram circuit. ; H8YNO601 Kemae Maru I in ear 6 figure (
This is a synchronization signal in the main scanning direction of the printer and is generated for each main scanning line. This is set as Are on the time chart, and this time is set as +6. The clock is 0K600K, and its frequency is the same as the image frequency. V brother N
The 602-digit main run is the section Iβ that defines the effective image section within the line. In addition, the iNi 603 has a section signal VJit
Pulse 1 clock (1 bit) before the start of N, [08
604 is the final clock (bit) pulse of the IK signal vEN.

Note that when a laser beam printer performs a recording operation based on both signals decoded from the compressed code (MH Coco) in the trench described above, the horizontal synchronization signal H8YNO is placed at a predetermined position on the scan line of the rask scan by the laser beam. This is based on the beam detection signal that detects the arrival of the laser beam, and the interval signal VHN is used to scan the photoreceptor (drum) on which a latent image is formed by scanning with the laser beam.
L/-Based on the section that the light is scanning.

As is clear from these, each signal 600 in FIG.
The temporal relationship between 604 and 604 should generally be fixed at a constant value. In this example, the length between HEIYNO 601 and iNi 605 (0 is 64 pixels).Also, the section of VBN 602 is the number of pixels in one line, but in this example, it is 4096 bits (1g of pixels). .

In FIG. 6, at time tQ, the circuit of FIG. 5 is set to the initial state for each main scan of image output. That is, as mentioned above, the MH coco of the first image for each 2-in (in this example, WB8 (10011) indicating a white run length of 8)
) is stored in the register 105 as "unloading complete", and the outputs 1 to Cl2 of the register 103 (in this example, 10011.
00010.0OO) is logic 104% ROM 10
It is given to 5th prize.

Similarly, the value of the code length counter 107 is (-1
)=(1111B). In this case, (-1) is “
It is defined to mean ``9j release completed''. Also, each 7
Lip 70 knob 510, 109° 515 is in set state, 7 lip flop 509 F'i is in set state.

Flip-flop 509 is set to fully indicate that it is in a completed state. Further, the state in which the clip-flop 510 is set (Q=1) indicates that the run-length latch 513 is busy (Bu8Y), as will be described later. The clip flop 515 outputs the ROM signal as the output Q.
When the output Q of 5 is equal to 1, the B/S-ROM signal indicating that the color of the M1 code to be decoded is black is generated.

Similarly, when the output Q is 0, it indicates that the output is white.

Also, assume that the run length counter 108i''j is stopped and its value is 0.The fact that this is 1 on the 5pTiu6os control line means that the register 105 can make 77 bits of data (Ml code). For simplicity, the output signals Σ0 to Σ of the accumulator 106
2 and @signal 0. That is, based on this assumption, all 28 bits of register 103 are valid MH Coco strings, indicating a state with no emptiness.

The state on μ is the state at time t6.

Now, at time t1, when the HEIYN (3 signal 601 shown in the sixth figure falls), the clip shown in the fifth figure 70
09 is reset and 11! is shown as 613 in FIG. OL
When F signal is 1, 5FT is passed through AND gate 508.
J! :N signal 605 becomes 1. SFT ordinary N signal 605
When is 1, the counter 107 shown in .86 is enabled for counting. At the same time, at time t1, the ROM 105
At the address, the output C\~0 held by the register 103 is stored.
12 is given. , (in this example, 10011 xxxx
xxxx) and the code ° out of the output of ROM 105
Length ab\~OL5 I:j is applied to code length counter 107 via gate 503 and gate 504. At the same time, since the 0JJD signal 607 is 0, the counter 107 enters the load mode, and CL\~OL3 (direct) is loaded into the counter 107 by the clock of tl.
) 1 code WB8 code length 5 divided by two's complement (-5
) is loaded.

Father, ROM105 output J'lti-RL5 and person (
It is given as an input to lgin length latch 513.

Run length latch 51 at 1st time! +Nike 7 Rinov“
The Q output of the flop 515 is also input as a ROM signal 620. At this time, the RLOH signal 608 controls the latch 513 to latch enable by setting it to 1, and the values of DO to D7 are latched into the latch 513 by the clock of tl.

[same] At time t1, a 7-return flop is set to 510 and 1. Also, slip 70 tsug 5151 is reversed. +3 USY, which is the Q output of the clip-flop 510
(H"j No. 609 is 1 only if the latch 515 is '
fr Indicates five latching effective run lengths. Father, B bar ROM which is the Q output of flip-flop 515
The fact that the signal 620 is 1 means that the register 103 then writes “
(And the color indicated by the un code that should be changed to "1 output completed" is black. (Also, if D/IIF-, ROM620 is 0, the color is white) SFTh:N 4pf No. 605 d Goo) 505, Gooto 50
Multi-7 lexer 102V as SO signal via 6
This error causes the data in register 106 to change by 1 bit.
Since the necessary data has been sent to the subsequent stage from the MH code in 3, the MH code has been used and the 5FTJ
The CN signal 605 indicates that the counter 107, which has become Sikarant town ffi'l, is 1. b) Carried signal O from the counter 107 as shown in the time chart in Figure 6.
Bit 77 is performed until RO606 occurs.
The used Mu code or V-) is swept from the star 103 (68), which is the counter 107 set to 11-5 in this example.
The register 10301 pin/ft is returned for one line until the value becomes (-1) 1j.'Jl'i:.

When the value of the counter 107 becomes (-1), the threshold value has now been used. 4'r+Sil of +M11 code (in this example, gin length 8, full white?, lH code WB8)
L is completed, and the next M H code (14 indicating black with run length 6)■Code 13J36) is placed in register 105VC.
In this case, ``σ, 4 photons j are output, but the latch 513 is still in the clip 70 tube 5106''i set, just in case the run length of the MH code (WB8) of IY■ is increased by q'. pt is the output of the gate 511 when the ORO i and X- of the counter 107 become 1.
When the signal 605 becomes 0, the counter 107 stops. ] S to Mr. 1
When the M-N signal 605 becomes 0, SO~B 24
The M numbers also become all \'', the register 103 stops shifting, and the data is held.
)'s condition is 2% until time t2.
U, RI and D signals 610 are set to 0 due to No. 4 603, and the run length held by the latch 515 (+
8 bits of white at I+11) are transferred to f) UNOTA 108 by RI and D signals 610 via multiplexer 514. At the same time 7 lip 70 tsugu 510 uhp 4B
Shiratsuchi 513 is set by No. 610.
becomes empty and busy (BσEIY) becomes iW? *Medium. Therefore, the output of the gate 511 becomes 1, the S FTEN number 605 becomes 1'', and the run length obtained by the code is set to 1'' in the register 103. After that, the MH code is sequentially decoded in the same manner.

Based on the gin length (-5 in this example) loaded into the counter 108 at time t2, the counter 1081-i starts counting by the IN signal 602 generated from the next bit at time t2, and the first shift of the counter 108 starts. (−
1) (time t3 in this example) ORI bias +4f
Issue 611. Also, the B/W signal 62 from the latch 515
Flip-flop 10 for each color of the image specified by 1
Set 9 and then set the first M1.
This means that the i code can be changed from both flights V to I (white 8 bits in this example).

Nae, VE, H (after the launch of No. 602, iN
i signal 603Vi11i Tana I (BYNC601 is ul
It remains 0 until t comes. Therefore, ■ Translation signal 602
For example, at time t5, #? Then, instead of the 1NiQ number 603, the CR Koshinke 611 indicating the count up of the counter 108 sends 7 resob 70 tsug 510.
and reset its busy state to Vp,
- By decoding the 7 so < 18 H code, the run length of 17 can be taken into the latch 515.

Now, at the cape here, in the light, ('i, the chord length of the MH chord is long/the length is φ, etc., or the short 45th chord is υ,) (one H chord is taken out. The used MH code to be flushed out from the register 106 is given to the multiplexer 102 from the time of completion Y.
By serially shifting by setting 1.51=82=: 0, the MH code can be continuously decoded without interruption.

However, on the other hand, if the run length base of the Ml code is shorter than the code length, when the code is serially shifted as described above, at 11η (during shift) when the code is being flushed out from the register 103, the 2
The length count ends up being T. At this point, in order to eliminate image discontinuity, it is necessary to change the next run length from 2 bits 513 to counter 108 by 1) or b.
Ru.

However, in register 103, r for the next MH code is
The latch 51 is not in the "pf4 output complete" state.
In 3, the run length to be captured is not outputted to the ROM 105. In this case, it is recorded in the printer: 11ii The image will not be interrupted, and the image cannot be output in real time. This inconvenience occurs when decoding the H8C code mentioned above, namely the M)l code which indicates white with run lengths 1, 2 and 5, and the MH code which indicates black with run length 1. In such a case, only the MW code, which is the above-mentioned 4-bit HFl0 code, should be subcoded by adding +6 to the MH code decode logic 104 and 1 (code length data OLD to CL5 from the OM 105). Equivalent to serially shifting the code, create the next stage of circuit! + Make a phrase. Hit, counter 07A
In order to be able to load a load value (-1), the counter 07 is loaded via the gate 504 which generates a load value (-1) according to the intoxication signal of the logic 104.

Also, this @ output from ROM 105 CLO~CL
4 #1 risC signal is inhibited by the signal 503, and the output 8fI'1 from the logic 104 and the shampoo that corresponds to the code length of the MH code decoded to 872 are outputted as SFO~8F2.
2, the multi-prefunner 102 is operated. This makes it possible to shift multiple bits in one bit of time, and by converting it, it is possible to "complete cueing" of the next code to be decoded at 17 disks 105 in one bit of time. Become.

Further, this jump lth is input to the accumulator 106 and cumulatively added to the 4t bit number of the register 05.

The software method for the above two bends 1. According to the table [! - IC-1 Output Photon" Kara [Run Length Latch - 1 history, a series of "Run Length Count" baits are brought back to life at high speed, and the images supplied to the printer section are executed without interruption. 112 is the output co of the gOL output circuit register 103
- When the EOL code appears in C++ and detects running, it outputs the signal 0ffiOL f. When the KOL code indicating the end of one line is produced by the ff1OL production circuit 112, the signal 0ffiOL is outputted via the timing adjustment 161 and approximately 523.
The signal -+40xob from the ICOL detection circuit 112 sets the clip flop 509 and the EOLF signal 613 becomes 0. As a result, the 5FTJIDN signal 605 becomes 0, and the register 103 stops until the next H8YNO comes. It will wait for HF3YNC in the state of Ml (one code has been put out).

In this way, the 111th period of alignment between the printer and the work of Ago SIb can be obtained well.

As mentioned above, ((The flea! return check progresses for each line and a poor image is formed.) Next, we will discuss the decoding error detection method using Fig. 7. The circuit shown in 87 is shown in Fig. Also, 1.1 in Figure 5 of 1-j
be kept in a suitable position. (4% In Figure 7H, 80
6 with 1 lt inverter, 6 +, (302#- is adder, 80!+ is latch, 804 is comparator,
805i latches, 806 and 807 are flip frogs.

820 in FIG. 5 is the same signal as the signal 820 output from the latch 513 via the multiplexer 514 in FIG. (As stated in ``M. H. Cor.

The run length of the door that unlocked the door is expressed as a two's complement number.The add fi 58o2 and the latch 803 constitute an accumulator. The carry from the LSB of adder 17 ao2 is 82944 (1) set to 1, and the output of adder 802 8211-j: the complement of 2 of run length 820 becomes If. . j+'Q is output 821-
Also, the addition to the latch 803 is shown in Fig. 6 FjLDtS.
At the timing of 10, the force is applied at the timing of loading the 2 length to be counted into the counter 108 shown in the figure. Iη continues. Also, the lunch 803 is cleared at the HEIYNO 601 signal 601 in FIG. 6 which is output to each line of the main 71-scanner. , that is, the output 8 of latch 803
22i-j The cumulative value of the run length of each input fU is expressed in binary. On the other hand, the latch 805 has a constant run length for each line (in this example, 409 pixels corresponds to one line of pixel convergence).
6) from apU4 by signal 824. The comparator 804 calculates the run length 822 (denoted as A) currently accumulated in the latch 803 and the correct answer bts2g (denoted as n) from the latch 805. This is a comparator circuit for comparison.

7 rib frog 806 is the gos signal 60 shown in FIG.
4, when the signal 831 indicating that A=B is not output from the comparator 804 at the Me 4% bit of each line, the AND gate 808
is set by the output 825 of . That is, setting the clip frog 806 indicates that it is equal to (-4 in the case of 1''/11), and indicates that 11 is equal to the M)I code or its decoding.

Clip 70 tube 807 has a shape of A>E 1-
), the comparator 804 outputs (j495
It is immediately set by the output 826 of the AND gate 809 which operates 852 manually even in the middle of accumulating the silane length.

, +'411, the Q output 82B of the flip-flop is 1 of the run length.
This indicates that the pixel Pl) in the interval jN 6t12 has been crocodile, and this indicates that a huge decoding error has occurred in the middle of decoding one line, as shown in Table 1.

Also, flip 70 knobs 806 and 807 t-j Fig. 6 1ijOLF 15 is 60-j, iii FiOL
(Eudof 1iue) /+(J!!L roasted by OL detection circuit 522H)IYNC! It will not be reset until the human power of 610 is applied, and it will be reset by the input of the signal 6010 and the output of the signal 6010.
Output of 807] 3827 or output 826 and separate f
f1OL (by Q output circuit 522, I for ff0L detection
By reminding the user of the timing, synchronization errors due to decoding R14, etc. can be minimized.

In this example, the silane length is cumulatively weighted γ using an accumulator, but this is replaced by a method in which 2 length values are sequentially subtracted from a single count, for example, 4096, and borrows from the subtraction counter are detected. You can also do that.

If a decoding error occurs in the above i/p and the flip-flop 806 or 807 is set, its output 1-1
σ↓9 is transmitted to the buffer switch control circuit 303 of the illustrated printer circuit.

The buffer switch control circuit 505 has the above-mentioned 51 points.
This buffer selection operation is performed to alternately select the input and output of the line buffer of a printer having a double buffer configuration. And clip 70 tube 806
Or, when inputting the cent signal from 807, that is, the decode Ra maυ detection signal, invalidates the image signal of the current line where the decoding error occurred, and replaces the line with the error with the previous line 1i-1ii. In order to reuse the image signal, the line buffer 7 is set so that the line buffer in which the 1+I line image signal is stored is reread.
Performs one-choice control. That is, for example, if a decoding error occurs while an image signal being decoded is being stored in the 12th in-buffer 301, the image signal currently being stored in the first in-buffer 501 is left unused, and the current image signal is 51 of the 2-line buffer 302 containing the bladder.
After the reading is completed, the same image signal is read out from the second line buffer 602 again.

As a result, the influence on the recorded image can be removed without printing 41+ based on the image signal in which the decoding error has occurred. Note that even if the number of line buffers in the printer is two or more, the process can be carried out as shown in jr, ].Also, a line buffer for NQ correction may be provided on the decoding circuit side.

Now, as mentioned above, in this example, when decoding an MU coded image, the first EOL of the MW code is added, and 1...? from the code following that f+. Image 41
As a line, decoding is started and the image at the end of k is reproduced. This is because, although not shown in the present case, the MH-encoded image is stored in, for example, an image memory, which exists before the storage circuit 101 shown in the first diagram, and is stored therein by apU, etc. 91 Specify the start address of the image memory and save the IAkl encoded image to Ns'
; is output and applied to the decoder circuit via the memory circuit 101.

At this time, if the MH code read from the image memory is kept, the EOL code will not necessarily come at the beginning if it is extracted from the middle of the image page. In order to start decoding correctly even in this case, the i1 memory circuit 101 is cleared before the start of decoding, and then the i1 memory circuit 101 is filled with the MH code read from the memory (the second
(state in the figure), and then input f into the decoder.
-p (Starts sending M'l (code). Then, until the first generation 4COL code is detected, it is not treated as an image code and sends data one after another) Continue sending F:OI- code 4・q Dedicate yourself to issuing the code, and then proceed to the ff0L code (if you are able to produce it, treat the subsequent code as an image 1 blue report, and decode it while controlling the code length etc.) In this way, the AOL code for the first city is changed to the above-mentioned I!i0L.
+(By finding it with the Q output circuit 112, it is possible to determine the delimiter of the MH code and to perform synchronous reproduction of the surface image.

Then, after the aforementioned decoding operation j4;1 starts, when the operation of finding the first jDOL code to be input for the first time starts from 1A1, data is sent from the memory circuit 101 to the first komaji register 103, but before that start. Everything in register 103”
0" exists, it is connected to a part (in the middle) of the MH code or M)I code that actually came from the memory circuit 101, and the JGOL code (000000000001)
This will result in a false positive detection. In order to avoid failure, the initial states of the registers 103 are all set to 1''. That is, the On ``'''' 027 of the register 105 are all set to ``1''.

Will this cause the above-mentioned OL error detection? ij, I can kick.

We will now explain how to preset all registers 103 to 1''.
+1η is formed by the 7 lip-flops F/11', therefore, a preset pulse 901 is inputted from an OPU or the like to the preset terminals of all the 7 lip-flops ψ, and the Q outputs of all the 7 lip-flops 70 are set to 1. Here, the clip 70 Tsug ψ is, for example, 5N748 made by American company T1.
74N etc. can be used.

Above, the main supercurrent side was passed using MH code No. 4 as an example,
It can also be applied to decoding codes using other compression methods. In addition, the image signal of Iga separation is a laser beam,
In addition to printing both images hF'rH with a printer such as a printer, λ:l can be used for various purposes such as displaying on a display such as a CRT or filing as a bit image. Furthermore, the numerical value used in this embodiment is not limited to this, and may be selected appropriately depending on the application, environment, etc.

It is possible to execute the 9-minute operation of 1 code in 7(), and it is also possible to execute 1" operation (in 1") with both high-speed processing requiring 1 ri. Real-time decoding) iii works in 6 units.It also effectively decodes and supplies compressed codes to output units such as printers that require high-speed and high-quality image recording. This becomes IjTfig.

First, the pressure I-, 1 code can be decoded and processed to detect A4'k related to f scale feed, and also,
The impact caused by this can be minimized.

Also, when printing is performed based on the double-mail signal obtained by decoding the compressed code, the synchronization between the printer and No. 4 processing unit is 9
It's a good thing to get.

``Cs 4.N ''I will reliably detect the line 1st part 1 code, which is the standard for the masterpiece, and 1st issue 41
It's something that can eliminate the inconvenience of B work's four shouts and one difference.

Furthermore, even if the compressed code is supplied to the i-th circuit from the middle of one page or one line, the de-split 1' It can prevent nausea.

[Brief explanation of drawings]

・(r Figure 1 is a circuit block diagram showing the fence of one embodiment of the present invention, approximately 1?\\\ Figure 2 (a) #'i is a diagram showing the storage format of the ME code in the circuit 101 ,・13
Figure 2 (b) is a diagram showing the continuous state of multiple MJ (codes); Figure 3 shows the configuration of a 1-inch bit/77 data (four-way block diagram, μII Figure 4); Figure 85 is a circuit block diagram showing the configuration; Figure 11 is a detailed circuit diagram of the circuit block diagram shown in Figure 1. Figure 6 is a timing chart diagram showing the operation timing of each part of the circuit shown in JR5. 8 is a circuit block diagram showing the configuration of a decoding error ejection circuit, FIG. 8 is a diagram showing an example of the configuration of the printer, and FIG. 9 is a block diagram showing the circuit configuration for recording operation of the printer shown in FIG. Figure 1 EOL
A circuit block diagram showing the configuration of the detection circuit, FIG.
0 is a circuit diagram showing the configuration of the 1 production gate shown in FIG.・Decoding logic,
11)4BM)] code table ROM. 7jQ Person Keyanon Stock Reisha Procedures Amendment (Method) October 24, 1980 ['' Manabu Shiga, Commissioner of the Patent Office 1, Indication of the Case 1982 Patent Application $ 114836 No. 2, Decoding of Compressed Code of Title of Invention Device 3, relationship with the case of the person making the amendment Patent applicant address 3-30-2 Shimomaruko, Ota-ku, Tokyo Name (100
)Representative of Canon Co., Ltd. Ryu Kaku 3 Department 4, Agent address: Canon Co., Ltd. 3-30-2 Shimomaruko 3-30-2, Ota-ku, Tokyo 146 (telephone 75B-2111) 5, date of amendment order September 1980 25th (shipment date) 6. Drawings to be amended: Plane 7 Figure 5 of the drawing first reviewed in the supplementary IF content application form is attached as shown in the attached sheet.
Write one letter (no changes to the content). Furthermore, in order to clearly display the characters, etc. in the drawing, we have divided Figure 5 at the time of filing into Figure 5 Part 1 and Figure 5 Part 2 and reprinted it.

Claims (1)

[Claims] A circuit that captures a compressed code to be decoded from continuously input compressed codes, a circuit that decodes the compressed code captured by the capture circuit, and reproduces pixel information based on the decoded data from the decoding circuit. and a circuit for generating an end signal indicating that the reproducing circuit has finished reproducing the image information based on the given decoded data, the capturing circuit A compressed code decoding device is characterized in that it takes in a compressed code to be decoded next.