JPH0584697B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a decoding device for compressed codes using band compression encoding used for facsimiles, image electronic files, and the like. In conventional image transmission devices such as facsimiles and recent image file devices using optical disks and magnetic disks, image data is compressed and handled to reduce the amount of data and speed up transmission or storage operations. We are trying to improve efficiency. Such image compression is a type of so-called code conversion operation, and in the case of Modified Hoffman (MH) encoding, which is a typical compression method, bit blocks of continuous white or black pixels in an image are converted to a different compression code. It is expressed in correspondence with . At this time, pixel combinations are created by associating compressed codes with short code lengths with pixel bit blocks that occur frequently, and by associating compressed codes with long code lengths with pixel bit blocks that occur less frequently. This method utilizes the bias in the frequency of occurrence to express the entire image using a different code string with a smaller number of bits. Incidentally, the correspondence of compressed codes to pixel bit blocks is determined based on empirical rules, and the code lengths of the compressed codes are irregular. Further, as a rule of MH encoding, an EOL (end of line) code is used together with the above compression code to indicate synchronization or separation of images on a line-by-line basis. Then, on the receiving device, this
A configuration in which line synchronization is performed based on EOL codes is generally used. Therefore, if data from the middle of a line or from the middle of a certain code is transmitted to the decoding circuit for some reason, the decoding circuit detects the EOL code that will be input afterwards,
According to the detection operation, a decoding operation is started. In this way, the EOL code plays an important function in the decoding operation, and if the EOL code is detected incorrectly, the subsequent decoding operation will be disrupted and accurate image reproduction will not be possible. Become. The present invention has been made in view of the above points, and it is possible to avoid erroneously identifying compressed codes other than EOL codes stored in a storage means as EOL codes.
The purpose is to accurately detect the EOL code and ensure synchronization of the decoding operation of the compressed code.
A compressed code decoding device that sequentially decodes compressed codes of undefined length including an EOL code, comprising a storage means for successively storing a plurality of compressed codes that are input continuously, and a plurality of compressed codes stored in the storage means. a shift means for setting the compressed code to be decoded next at a predetermined position in the storage means by shifting the run length data and the compressed code by decoding the compressed code set in the predetermined position in the storage means; a decoding means for outputting code length data; a shift control means for controlling a shift amount of a plurality of compressed codes executed by the shifting means according to the code length data output from the decoding means; a detection means for detecting whether or not the EOL code exists; a decoding control means for causing the decoding means to decode the compressed code following the EOL code based on the detection of the EOL code by the detection means; and the memory. Storage means for storing in the storage means, prior to storing the compressed code in the means, specific data that is not detected as the EOL code by itself and that is not detected as the EOL code even when combined with another compressed code. The present invention provides a compressed code decoding device having the following. A detailed description of the invention follows. First, an outline of an embodiment of the present invention will be explained using the circuit block diagram shown in FIG. In FIG. 1, reference numeral 101 denotes a memory circuit, for example, a reader that photoelectrically reads images, an electronic file that files images, or a receiver that receives image information via a transmission path such as a telephone line. A circuit that stores a so-called MH (Modified Hoffman) code obtained by compressing and encoding an image signal using a separate means in a form that can be read out sequentially in units of 16 bits (1 word), for example. This is a circuit that can be implemented using RAM (random access memory) or a latch circuit. or,
An example of the storage format of the MH code in the storage circuit 101 is shown in FIG. 2a. That is,
The inherent nature of the MH code is that its code length is uneven (minimum 2 bits to maximum 13 bits), but regardless of the code length, there is no empty bit, and the length is as shown in Figure 2b.
This is a format in which serially connected bit strings are exchanged in parallel every 16 bits. In Figure 2b, WB and BB indicate white and black pixels, respectively.
In the MH code, the numbers after WB and BB represent the run length of the code; for example, WB8 is an MH code that represents white with a run length of 8. In this format, the MH code delimiter and the word (16 bit) delimiter do not necessarily match. Furthermore, the memory circuit 101 has a function of outputting subsequent words sequentially in parallel under external control. In FIG. 1, 102 is a so-called multiplexer (data selector). Also, 103 is
It is a register having 28-bit parallel input and output, and is connected from the storage circuit 101 to the multiplexer 10.
2 and is applied to the input side of register 103.
The function of temporarily storing the MH code and the role of outputting the MH code already stored in the register 103 to the MH code decode logic 104 and MH code decode table ROM (read-only memory) 105, etc., which will be described later. It has properties. The multiplexer 102 and the register 103 form a so-called bit shifter capable of serially shifting data and n-bit jump shifting. This bit shifter is connected to the MH code decode logic 104 and the MH code decode logic 104, which will be described later.
Controlled by the output of the decode RM 105, etc., the storage circuit 101 functions to shift and store the MH code stored in the register 103 by the required number of bits, regardless of the boundary between the MH codes, using the method described above. FIG. 3 (details will be described later) is a diagram showing the detailed configuration of this bit shifter.
In the code string, the MH code illustrated in the storage circuit 101 shown in the first diagram is moved to the register 103 through appropriate control, and then the white run length 8
The diagram shows a state in which the MH code WB1 (10011) indicating the MH code WB1 (10011) has reached a decodable position. That is, the output C0 of the register 103 shown in the third diagram, that is, the LSB output.
The state in which the first bit of the MH code is output is defined as a decodable position, and will be referred to as ``completion of cueing'' from now on. Therefore, the code arrangement in the register 103 in FIG. 3 is an MH code indicating a white run length of 8.
This shows that WB8 is in the "cueing complete" state. In FIG. 1, 104 is an MH code decode logic (hereinafter referred to as logic 104), and the following four types of codes have a run length shorter than the code length of the MH code.
i.e. white run length 1 (in MH code)
000111, code length = 6 > run length = 1), white run length 2 (0111 in MH code, code length = 4 > run length = 2), white run length 3
(1000 for MH code, code length = 4 > run length = 3) and black run length 1 (for MH code
010, code length=3>run length=1). In the following explanation, the above four types of MH codes that indicate white run length 1, white run length 2, white run length 3, and black run length 1 will be collectively referred to as the HSC code. . In FIG. 1, 105 is an MH code decode RM (hereinafter referred to as RM105),
The above-mentioned logic 104 handles the decoding of four types.
This circuit mainly decodes all MH codes including MH codes. The logic 104 and the ROM 105 are responsible for decoding the MH code, which is divided into sections depending on the processing speed and method of the MH code.
Every time the MH code completes cueing,
It outputs the run length of the MH code, the code length, whether the image is black or white, whether it is a make-up code or a termination code, and whether it is present or not. Reference numeral 112 denotes an EOL detection circuit which detects whether or not a code for line synchronization, that is, an end-of-line (EOL) code exists in the MH code stored in bit serial form in the register 103, and the location where the code is stored. In FIG. 1, reference numeral 108 is a run length counter, which is a binary counter capable of counting from the count number "0" to the maximum make-up code run length, that is, "2560" or more. This run length counter 108 is a logic 10
4 or every time the run length of the MH code output from the ROM 105 is finished counting, the count end signal (in this example, the ripple/carry signal of the counter
CR) is output. A flip-flop 109 inverts its output each time it receives a count end signal (ripple/carry CR) from the run-length counter 108 mentioned above. However, as will be described later, the output is controlled so as not to be inverted by the count end signal of the make-up code. The output of flip-flop 109 is an image signal obtained by decoding the MH code read from memory circuit 101. 107 is the chord length counter.
By serially or jump shifting the MH code that has been "cueing completed" in the register 103 with a binary counter that can count over "13", which is the maximum code length of the code, it can be converted into a decoded code. When the MH code is swept out from the 103rd register and the subsequent MH code is shifted to the "cue completion" position, the shift amount is counted and controlled. 106 is a 4-bit accumulator.
As described above, the memory circuit 10 is stored in the register 103.
When the MH code taken in from 1 is decoded, it is sequentially flushed out from the register 103, thereby creating an empty bit in the register 103. Therefore, the accumulator 106 counts the number of empty bits in the register 103, and stores a new MH code in the memory circuit 101 every time 16 empty bits are created.
1 word (16 bits) from register 1 in parallel.
Replenish the empty bits in 03. This controls the MH code sequence fed from the register 103 to the logic 104 or RM 105 so as not to be interrupted, thereby enabling high-speed decoding operation. In addition, 110 is the blocks 101 to 10 shown in the first diagram.
9 is a diagram illustrating a control circuit that controls input/output signals between 9 and 9. Convert the MH code to an image signal as described above,
That is, the MH code is decoded. The decoded image signal is supplied to the printer 111, and the image is recorded on the recording material. Note that the printer 111 outputs a horizontal synchronization signal, which is a synchronization signal for each scan.
HSYNC is output, and this HSYNC is used for the timing of the decoding operation. Next, embodiments of the present invention will be described in more detail.
This embodiment uses a so-called "" It provides a high-speed, real-time, MH decoder. Therefore, the problems of high processing speed of the MH/decoder and synchronization of the image output of the MH/decoder (in this example, the image frequency is assumed to be + several MHz) with a high-speed printer such as a laser beam printer are solved. Must be. Therefore, in order to solve these problems, we will realize the desired "high-speed, real-time, MH decoder" based on the processing method described below. (1) Synchronization between the MH decoder and the printer is performed using the EL of the MH code and the horizontal synchronization signal, which is a synchronization signal for each line of the printer. (2) In the register 103 in FIG. 1, the MH code that has been decoded with "cueing completed" is swept out, and the subsequent MH code is shifted to the "cueing completed" position. Therefore, one of two methods is used: jump shift and serial shift. A specific configuration for achieving these two points will be explained using the drawings. FIG. 8 is a perspective view showing the configuration of one embodiment of the laser beam printer shown as an example of the output section in FIG. 1. This printer uses an electrophotographic method using laser light, and 201 is a photosensitive drum rotatably supported within a housing Ha. 202 is a semiconductor laser that emits laser light La, and the emitted laser light La is transmitted to the beam expander 20.
3 and becomes a laser beam with a predetermined beam diameter. Further, the laser beam is incident on a polyhedral mirror 204 having a plurality of mirror surfaces. The polyhedral mirror 204 is rotated at a predetermined speed by a constant speed rotation motor 205. The laser light emitted from the beam expander 203 is scanned substantially horizontally by the polyhedral mirror 204. The photosensitive drum 201 is charged to a predetermined polarity by a charger 213 using an imaging lens 206 having f-θ characteristics.
An image is formed above as a spot light. A beam detector 207 detects the laser beam reflected by the reflecting mirror 208, and uses this detection signal to determine the timing of the modulation operation of the semiconductor laser 202 in order to provide desired optical information onto the photosensitive drum 201. A high-resolution electrostatic latent image is formed on the photosensitive drum 201 by the laser light that is imaged and scanned on the photosensitive drum 201 . After this latent image is developed by the developing device 209, it is transferred to the recording material stored in either the cassette 210 or 211, and then the image is fixed on the recording material by passing through the fixing device 212. The hard copy is ejected to an ejecting unit (not shown). FIG. 9 shows an embodiment of a printer circuit for modulating the semiconductor laser shown in FIG. 8 with a predetermined image signal. The image signal VIDEO inputted from the input terminal IN after being decoded is sent to a first line buffer 301 consisting of a shift register or the like having a number of bits equal to the number of pixels for at least one scan for each group of image signals for one scan; The signals are alternately input to the second line buffer 302 under the control of the buffer switch control circuit 303. Further, the image signals inputted to the first line buffer 301 and the second line buffer 302 are read out alternately for each scan using the beam detection signal from the beam detector 304 as a trigger signal, and are applied to the laser driver 305. The laser driver 305 controls the anticonductor laser 3 based on the input image signal to control the emission of laser light.
06 is modulated and controlled. By having two line buffers, while inputting image signals that are input one after another to one of the line buffers, the laser driver 305 transfers the image signals already stored in the other line buffer.
Since it outputs to The beam detection signal from the beam detector 304 is also transmitted to the decoding processing circuit as a horizontal synchronizing signal HSYNC, and is used for synchronizing the decoding processing and the printer operation as described later. Incidentally, the image signal decoded in this printer is inputted through a buffer having a double buffer configuration including two line buffers, that is, a first line buffer 301 and a second line buffer 302. This double buffer configuration is used to perform a correction operation when an error occurs in the decoding operation. In other words, if an error occurs in the decoding operation while the image signal decoded by the decoding circuit is being stored in one line buffer, printing operation using the image signal of the current line containing the error is prohibited, and the image signal already stored in the other line buffer is Printing is performed based on the stored image signal of the previous line. As a result, printing is not performed using an image signal with a decoding error, so that the influence on the reproduced image can be eliminated. Note that this correction operation will cause at least two lines of the image to be duplicated based on the same image signal, but in the high-resolution (for example, 16 pel/mm) recording operation used in this example, it will not have much of an effect on the reproduced image. isn't it. In FIG. 4, 105 is the MH code table ROM shown in FIG.
It is composed of OM (read only memory). To schematically explain the contents of RM105 below, AD0 to AD13 are RM10
5 is the address terminal, and 0 to 011 are R
This is the output terminal of M105. The format of the memory contents of the ROM 105 is determined by inputting the LSB bit of the MH code to be decoded from the register 103.
Align with address terminal AD0 of OM105 and each below.
Each bit of the MH code is sequentially transferred to ROM1 in the MSB direction.
05 address terminals AD1 to AD11. Address terminal AD13 has a signal B/-ROM indicating the color of the MH code (black = 1, white = 0)
shall be given. If the MH code is shorter than 12 bits, the missing bits are ignored (DONT CARE). Also, the EL code is treated as a make-up code. Also run length 1
Color bits (AD13) of make-up codes of 792 or higher are ignored (DON'T CARE). The contents of the MH codes given each address are written in the ROM 105 as storage data for the addresses determined above, and outputs corresponding to each MH code are output to the output terminals O0 to O11.
That is, output terminal 0 outputs a signal M/ which becomes "1" when the decoded MH code is a make-up code, and becomes "0" when it is a termination code. Output terminal 1 is a signal that outputs "0" when the decoded MH code is a white code with run length 0 (00110101) or a black code with run length 0 (0000110111), and becomes "1" in other cases.
Output TO. Output terminals 2 to 5 output 4-bit outputs CL0 to CL3 in which the code length (number of bits) of each MH code is expressed in two's complement. However, the output terminal 5 is the LSB of the code length. Output terminal 6~
O11 outputs 6-bit outputs RL0 to RL5 in the form of two's complement representation of the run length of each MH code. However, the output terminal 11 is
It is LSB. For the make-up code, only the upper 6 bits of the binary representation of the run length are assigned to the output terminals 6-11. this is
Top 6 makeup codes in MH code
This is because the run length can be expressed using only bits. 402 in FIG. 4 illustrates outputs 0 to 11 of the ROM 105 when the MH code WB8 (10011) indicating white with a run length of 8 is decoded. (The MH code table used in this example is CCITT
YELLOW-BK Fascicle. 2 Rec.
T.4 According to TABLE 1/T.4 and TABLE 2/T.4. ) In FIG. 4, reference numeral 104 is the MH code decoding logic shown in FIG. 1, which in this embodiment is a detection logic composed of an AND gate and an OR gate. is the output of logic 104.
The HSC signal is a code, i.e. run length 1,
When the MH code indicating white with run length 2 and 3 and the MH code indicating black with run length 1 are detected, it becomes "0". Further, outputs 0 to 2 are the code lengths of the four types of MH codes (HSC codes) described above expressed in binary numbers, inverted and output.
FIG. 4 404 shows an example of the output when decoding the MH code white 1WD1 (000111) indicating white with a run length of 1. Note that a logic circuit is used to decode the HSC code because the current ROM addressing system cannot adequately handle the time required for high-speed processing. Tables 1 and 2 show the operation of the bit shifter shown in Figure 3.
Explain with reference to. FIG. 3 102 is the multiplexer shown in FIG. 1, with two tri-state multiplexers 10
21 and 1022. multiplexer 10
When the control line from the accumulator 106 to 2 is "0", all outputs A ₇ to A ₂₇ from the multiplexer 1022 side to the register 103 become tri-state floating and become invalid. Multiplexer 1
The outputs A ₀ to _{A 27} from the 021 side become valid and become the outputs C ₀ to _{C 27} of the register 103. At that time, multiplexer 1021 selects input signals C ₀ -C ₂₇ from register 103 using input lines S ₀ -S ₂ .
Table 1 shows how the selection is made. For example, S ₀ =S ₁ =
1, if S ₂ = 0, the output C ₃ of register 103 ~
C ₂₇ is taken in and selectively output as outputs A ₀ to A ₂₄ , respectively. Next, when the control line to the multiplexer 102 is "1", the output A ₀ ~
_A6 is selectively given by the input lines S0 to _S2 from the multiplexer 1021 in the same way as when the control line is " ₀ ". Output A ₇ from multiplexer 102
~A Among ₂₇ , except those indicated by Y in Table 2, the multiplexer 1022 side is enabled, and the multiplexer 10
Among the outputs A ₇ to _{A 27} on the 21 side, the outputs other than those indicated by Y in Table 2 are floating and are invalid. Further, the outputs A ₇ to _{A 27} given from the multiplexer 1022 to the register 103 are selected by the input lines Σ ₀ to _{Σ 2} to the multiplexer 1022, as shown in Table 2, but the bits indicated by Y in Table 2 are It is selected from the multiplexer 1021 side. The number of Y is set by controlling the tri-state state of the multiplexer 1021 using the input lines ST7 to ST11 output corresponding to the input lines Σ ₀ to _{Σ 2} to the multiplexer 1022. In addition,
The circuits of multiplexers 1021 and 1022 in FIG. 3 can be easily realized using commercially available multiplexers (eg, IC.F251 manufactured by Fairchild, Inc., USA), gate circuits, and the like. Also, multiplexer 10
2, A ₀ ~ as output to register 103
The output selected by _A27 is latched into register 103 by clock CK. By configuring the bit shifter as described above, it is possible to shift the 16-bit parallel MH code signal inputted from the memory circuit 101 by an arbitrary number of bits. As a result, MH codes with uneven code lengths can be brought into the above-mentioned "cue completion" state.

【table】

【table】

【table】

[Table] As mentioned above, the MH code is determined by monitoring the code string moving within the register 103, and the movement method is to move the code one bit at a time using the bit shifter 102 or the like. Treated as serial shift and HSC code
A jump shift of up to 6 bits occurs when an MH code is detected. In other words, the code string in register 103 is controlled so that at most no more than 6 bits can be moved in one clock time. Therefore, when the EOL code (000000000001) moves within the register 103, its LSB bit will always appear in _C0 to _C5 of the register 103 even if the amount of movement is incorrect due to the previous code. Generally, when decoding an MH code, detection of an EL code is extremely important due to its code system. Below, the EOL detection circuit 11 shown in FIG.
2 will be explained in detail. In other words, the EOL code is a delimiter code for each line of the image, and at the same time has the role of indicating the position of the MH code that follows it. The boundaries of the MH code become unclear, making it impossible to decode one line of the image.
Furthermore, depending on the detection method used, the EOL of each subsequent image line cannot be detected, and eventually the printed image is distorted to the extent that it is almost unusable. Therefore, it is important to develop an EOL detection method that minimizes errors in EOL code detection even if the MH code in the MH code string is slightly incorrect due to transmission/reception errors. If the MH code is reliably detected, code errors can be recovered within one line of the image. FIG. 10 is a diagram showing a detailed configuration of the EOL detection circuit 112. As shown in FIG. 10, so that the LSB of the 12-bit EL code (000000000001) can be placed anywhere from _C0 to _C5 of the register 103, at least the shift amount that can be shifted at one time in the register 103, that is, 6, corresponds to 6. Seed detection gates 1001 are provided in parallel. This prevents failure to detect an EL code by monitoring the data stored in the register 103. Then, from the detection gate 1001 that detected the EOL code, 0 to
A detection signal indicating the position of the EOL code in the register 103, such as 5EOL, is output. This method prevents errors in EL detection unless the EOL code itself contains error bits. Therefore, image code errors can always be recovered within one line. Furthermore, the probability that an error bit is included in an EOL code is extremely low compared to the probability that an error bit is included in an image code, considering the ratio of the number of bits, and can be ignored in practical terms. FIG. 11 shows details of the detection gate for EOL code detection. As shown in the figure, the configuration is such that 12-bit data is imported in parallel, and the MSB
The 11-bit data excluding the above is applied to the 12-input NAND gate 1002 along with the aforementioned MSB via the inverting gate INV. This decodes the EOL code. When the EOL code is decoded, the output of NAND gate 1002 becomes low level. Output 0EOL~ of the EOL detection circuit 112 in Fig. 10
5EOL is transmitted to the code length counter 107 and the accumulator 106. The accumulator 106 uses this signal to cause the register 103 to shift by the code length of the EOL code. That is, the EL detection circuit 112 shown in FIG. 10 may already detect EOL in a state where the MH code or Fi11 bit still remains in the register 103 before the EOL code, considering its detection position.
Therefore, when the EOL detection circuit 112 detects an EOL code detection signal other than signal 0, that is, an EOL code detection signal 1 to 5 among the EOL codes detected, the accumulator 106 detects the EL in the register 103.
After the remaining code in front of the code is flushed out from the register 103 by the shift operation described above,
The register 103 is caused to further shift by the code length of the code, that is, 12 bits. As a result, the EOL code has been swept out, and the state of "cueing completion" for the image MH code at the beginning of the next line to be decoded is reached. Furthermore, this also eliminates wasted time caused by decoding an EOL code that is not image information in the same way as other compressed codes. Next, a detailed explanation of the entire block diagram shown in FIG. 1 will be given using FIG. 5 and the like. Since the operation of the circuit shown in Figure 5 is complex, we will set some conditions to make it easier to explain, and we will also explain the basics of the circuit using the MH code decoding operation, which is considered to be common, as an example. The operation will be explained, and then the establishment of the setting conditions will be explained. Let us use FIG. 2b as an example of the MH code string to be decoded. The operating principle of this circuit is that, before the printer's horizontal synchronization signal HSYNC arrives, the EL code that appears earlier in FIG. 2b is swept out of the register 103 shown in FIG. next to
The MH code WB8 indicating white run length 8, which is the MH code (that is, the MH code of the first image signal of the line to be decoded), is stored in the register 103 in the state of "starting complete" as described above, and is sent from the printer. Assume that it is waiting for HSYNC. FIG. 6 is a time chart of the main parts of the circuit of FIG. In FIG. 6, HSYNC 601 is a synchronization signal in the main scanning direction of the printer described above, and is generated for each main scanning line. This is used as the reference for the time chart, and this time is set as t ₀ . CK600
is the fundamental clock, whose frequency is the same as the image frequency. VEN 602 is a section signal that defines an effective image section within the main scanning line. Also, iNi
603 is one clock (1 clock) at which the section signal VEN starts.
bit) previous pulse, EOS604 is interval signal
This is the final clock (bit) pulse of VEN.
As mentioned above, when a laser beam printer performs a recording operation based on an image signal decoded from a compressed code (MH code), the horizontal synchronization signal
HSYNC is based on a beam detection signal that detects that the laser beam has reached a predetermined position on the scan line of the raster scan using the laser beam.
The section signal VEN is based on the section in which the laser beam scans the photoreceptor (drum) on which the latent image is formed. As is clear from this, the temporal relationships among the signals 600-604 in FIG. 6 should generally be fixed at constant values. And in this example,
The length between HSYNC601 and iNi603 is a fixed length of 64 clocks. Also, the section of VEN 602 has the number of pixels of one line, and in this example, it is 4096 bits (pixels). In FIG. 6, at time _t0 , the circuit of FIG. 5 is set to the initial state for each main scan of image output. That is, as mentioned above, the MH code of the first image for each line (in this example, WB8 (10011) indicating white run length 8) is stored in the register 103 as "starting complete", and the outputs of the register 103 are C0 to C12.
(10011.0010.0001 in this example) is Logic 104,
It is given to ROM105 etc. Similarly, the value of the code length counter 107 is (-1)=(1111B). At this time (-
1) is defined to mean "completion of cueing." Also, each flip-flop 510, 109, 5
15 is in a reset state, and flip-flop 509 is in a set state. The fact that the flip-flop 509 is set (Q=1) means that after detecting the EOL of the MH code,
This indicates that the EOL code has been completely cleared from the register 103. Further, the state in which flip-flop 510 is set (Q=1) indicates that run-length latch 513 is busy, as will be described later. Flip-flop 515 outputs the B/-ROM signal as output Q. The output Q of this flip-flop 515
is a B/-ROM signal which indicates that the color of the MH code to be decoded is black when it is 1. Similarly, when the output Q is 0, it indicates white. It is also assumed that the run-length counter 108 is stopped and its value is zero. SFTEN6
05 is a control line, and the fact that it is 1 indicates that the register 103 can shift data (MH code). Also, for simplicity, it is assumed that the output signals Σ ₀ to Σ ₂ and the signal of the accumulator 106 are zero. That is, with this assumption, register 1
All 28 bits of 03 are valid MH code strings, indicating a state with no emptiness. The above is the state at time _t0 . Now, at time _t1 , the flip-flop 509 shown in FIG. 5 is reset by the fall of the HSYNC signal 601 shown in FIG. becomes 1. SFTEN
When the signal 605 is 1, the counter 1 shown in FIG.
07 becomes count enable. time at the same time
At t ₁ , the address of ROM105 is register 10.
The outputs C0 to C12 held by the controller 3 are given. (10011XXXXXXXX in this example) and RM105
Of the outputs, code lengths CL0 to CL3 are provided to a code length counter 107 via gates 503 and 504. At the same time, since the signal 607 is 0, the counter 10
7 is in load mode and by the clock of _t1
The values of CL0 to CL3 are loaded into the counter 107. In this example, it is the two's complement of the code length 5 of the MH code WB8 indicating white with a run length of 8 (-5).
is loaded. In addition, the outputs RL0 to RL5 and M/ of the ROM105
Provided as input to T run length/latch 513. At the same time, the Q output of the flip-flop 515 is also applied to the run-length latch 513.
It is input as a ROM signal 620. At this time, the RLCH signal 608 controls the latch 513 to latch enable with a ₁ , and the D
The values 0 to D7 are latched in latch 513. At the same time, flip-flop 510 is set to 1 at time _t1 . Also flip flop 515
is reversed. A 1 on the BUSY signal 609, the Q output of flip-flop 510, indicates that latch 513 is latching a valid run length. Also, the fact that the B/-ROM signal 620, which is the Q output of the flip-flop 515, is 1 indicates that the register 103 should indicate "cue completion".
Indicates that the color indicated by the MH code is black. (Also, if B/-RM620 is 0, the color is white) SFTEN signal 605 is gate 505, gate 5
06 to the multiplexer 10 as the S signal.
2 and controls the data in register 103 to be shifted by 1 bit. As a result, the transfer of the necessary data from the MH code in the register 103 to the subsequent stage has been completed, and the MH code is now used.The time chart in FIG. Bit shifting is performed until the carry-out signal CRO 606 is generated from the counter 107, as shown in FIG. That is, in this example, the value of the counter 107 set to -5 is (-
1) of the register 103 until it reaches the value 1).
Continue repeating the shift. When the value of the counter 107 becomes (-1), the cleaning of the currently used MH code (in this example, the MH code WB8 indicating white with run length 8) is completed, and the next MH code (run length 6) is cleared. show black
MH code BB6) is “cueing complete” in register 103, but latch 513 still contains the previous data.
Since the run length of the MH code (WB8) remains, the flip-flop 510 remains set. Therefore, the CRO signal of counter 107 is 1.
As a result, the output of the gate 511 becomes 0, and as a result, the SFTEN signal 605 becomes 0, and the counter 107 stops. Similarly SFTEN
When the signal 605 becomes 0, the S0 to S2 signals also all become 0, the register 103 stops shifting, and the data is held. Therefore, "cueing complete"
The state (BB6) continues until time t ₂ . At time _t2 , the iNi signal 603 causes the signal 610 to become 0, and the run length held in the latch 513 (white 8 bits in this example) is transferred to the counter 108 by the signal 610 via the multiplexer 514. At the same time, flip-flop 510 is set by signal 610. This empties the latch 513 and eliminates the BUSY condition. Therefore, gate 511
The output of becomes 1, and the SFTEN signal 6 becomes 1 as described above.
05 becomes 1, and the run length obtained by the MH code indicating "cue completion" in the register 103 is latched into the latch 513. Thereafter, the MH codes are sequentially decoded in the same manner. Based on the run length (-5 in this example) loaded into the counter 108 at time _t2 , the counter 108 starts counting by the VEN signal 602 generated from the next bit at time _t2 . Then, when the value of the counter 108 becomes (-1) (time t ₃ in this example), a CRI signal 611 is output. Also, latch 513
The flip-flop 109 is set according to the color of the image specified by the B/signal 621 from the . As a result, the first MH code is displayed as an image.
This means that the image can be converted to VIDEO (white 8-bit in this example). Note that after the VEN signal 602 rises,
The iNi signal 603 remains at 0 until a new HSYNC 601 arrives. Therefore, the VEN signal 60
2, for example, at time _t3 , the flip-flop 510 is reset by the CRI signal 611 indicating the count up of the counter 108 instead of the iNi signal 603, and the busy state is released. The obtained run length can be loaded into the latch 513. Now, in the explanation so far, the code length of the MH code is equal to or shorter than the run length length, and the MH code is "cue completion".
From the point in time, if the used MH code to be flushed out from the register 103 is serially shifted by setting the signals S ₀ =1 and S ₁ =S ₂ =0 given to the multiplexer 102, the MH code can be decoded without interruption. That's why. However, on the other hand, if the run length of the MH code is shorter than the code length, if the serial shift is performed as described above, while the code is being flushed out from the register 103 (during the shift), the counter 108 will store the corresponding code.
The run length count of the MH code is completed. At this point, it is necessary to take the next run length from latch 513 to counter 108 in order to eliminate image discontinuity. However, since the register 103 is not in the "cue completion" state for the next MH code, the run length to be captured has not been output from the ROM 105 to the latch 513. Eventually, in this case, the image recorded by the printer will be interrupted, making it impossible to output the image in real time. This inconvenience is caused by the aforementioned HSC code, that is, run length 1,
MH code showing 2 and 3 white and run length 1
Occurs when decoding an MH code that indicates black. Therefore, in such cases, the above-mentioned four types of HSC
Only the MH code, which is a code, uses the MH code decode logic 104 to operate the subsequent circuit equivalent to serially shifting the code to be decoded using the code length data CL0 to CL3 from the ROM 105. That is, the logic 104 is configured so that the counter 107 can be loaded with (-1).
A load value (-1) is generated by the HSC signal and loaded into the counter 107 via the gate 504. Also, at this time, the output from ROM105 CL0~
CL3 is inhibited at gate 503 by a signal. Also, the output SF1 from logic 104
The jump amount corresponding to the code length of the MH code decoded to SF2 is output as 0 to 2, and S ₀ to
The multiplexer 102 is operated via _S2 . This makes it possible to shift multiple bits in one bit time, in other words, the register 103 of the next code to be decoded in one bit time.
You will be able to "cue complete" in . This jump amount is also input to the accumulator 106 and cumulatively added to the number of empty bits in the register 103. With the above two shift methods, "cueing is completed"
A series of operations from ``run length latch'' to ``run length count'' are repeated at high speed to perform decoding without interrupting the image supplied to the printer section. 112 is the EOL detection circuit and register 10
When it detects that the EOL code appears on the outputs C ₀ to C ₁₁ of 3, it outputs a signal 0EOL. Then, the EOL code indicating the end of one line is sent to the EOL detection circuit 11.
2, the flip-flop 509 is set by the signal 0EOL from the EOL detection circuit 112 via the timing alignment circuit 523.
The EOLF signal 613 becomes 0. This ultimately results in
The SFTEN signal 605 becomes 0, and the register 103 stops until the next HSYNC arrives, and the MH code waits for HSYNC in the state of "heading complete". In this way, good synchronization between the printer and the decoding operation can be achieved. As described above, an image is formed by repeatedly scanning each line. Next, a decoding error detection method will be described using FIG. The circuit shown in FIG. 7 is connected to the appropriate location in FIG. 1 or FIG. 5. On Figure 7, 8
01 is an inverter. Further, 802 is an adder, 803 is a latch, 804 is a comparator, and 803 is a latch.
05 is a latch, and 806 and 807 are flip-flops. FIG. 7 820 is the latch 513 in FIG.
This is the same signal as the signal 820 output from the multiplexer 514, and as described above, the run length as a result of decoding the MH code is expressed in two's complement. Now, adder 802 and latch 803 constitute an accumulator. The carry from the lower LSB of the adder 802 is set to 1 by the 829 signal (1), and as a result, the output 821 of the adder 802 becomes the two's complement of the run length 820. Therefore, the output 821 is a binary representation of the positive integer of the run length. Further, the addition to the latch 803 continues at the timing 610 in FIG. 6, that is, at the timing when the run length to be counted is loaded into the counter 108 shown in FIG. or,
The latch 803 is cleared every time the HSYNC 601 signal 601 in FIG. 6 is output for each line of main scanning. That is, the output 822 of latch 803 represents the cumulative value of the run length for each line in binary form. On the other hand, the latch 805 holds a constant run length for each line (in this example, 4096, which corresponds to the number of pixels in one line), which is informed by a signal 824 from the CPU or the like. Comparator 804 is a comparator circuit that compares the run length 822 (denoted as A) currently accumulated in latch 803 with the correct value 823 (denoted as B) from latch 805. The flip-flop 806 is the EOS shown in Figure 6.
When the signal 604 is output, that is, at the final bit of each line, the signal 831 indicating that A=B is not output from the comparator 804.
Set by output 825 of AND gate 808. That is, the setting of the flip-flop 806 indicates that the cumulative run length value A has become equal to the predetermined correct value B (4096 in this example), indicating that there was an error in the MH code or its decoding. shows. When the flip-flop 807 becomes in the state of A>B, it is immediately set by the output 826 of the AND gate 809 which receives the signal 832 output from the comparator 804 even during the run length accumulation. That is, the Q output 828 of the flip-flop is such that the cumulative value of the run length is the expected correct value in the middle of the line (4096 in this example, that is,
This indicates that a large decoding error has already occurred during the decoding of one line. In addition, flip-flops 806 and 807 have 613 in FIG. 6 "0", that is, EL (Eudof).
liue) is detected by the EOL detection circuit 112.
It is not reset until HSYNC610 is input, and gate 8 is reset by HSYNC signal 601 input.
It is reset by the output of 10. Therefore, a separate EOL detection circuit 112 detects the output 827 or 828 of each flip-flop 806, 807.
By focusing on EOL detection, it is possible to minimize synchronization errors due to decoding errors, etc. Although this example shows an example in which run lengths are cumulatively added by an accumulator, this may be replaced with a method in which run length values are sequentially subtracted from a predetermined number, for example, 4096, and borrows from the subtraction counter are detected. When a decoding error occurs as described above and the flip-flop 806 or 807 is set, its output is transmitted to the buffer switch control circuit 303 of the printer circuit shown in FIG. As described above, the buffer switch control circuit 303 performs a buffer selection operation for alternately selecting input and output of line buffers of a printer having a double buffer configuration. and,
When the set signal, that is, the decoding error detection signal, is input from the flip-flop 806 or 807, the image signal of the current line in which the decoding error has occurred is invalidated, and the image signal of the previous line is reproduced in place of the line in which the error occurred. Line buffer selection control is performed so that the line buffer in which the image signal of the previous line is stored is reread for use. That is, for example, if a decoding error occurs while storing an image signal being decoded in the first line buffer 301, the first line buffer 30
1, the image signal currently being stored is invalidated, and after the reading of the second line buffer 302 from which the image signal is currently being read is completed, the same image signal is read out from the second line buffer 302 again. As a result, the influence on the recorded image can be removed without performing a printing operation based on the image signal in which the decoding error has occurred. Incidentally, the same operation can be performed even if the number of line buffers in the printer is two or more. Further, a line buffer for error correction may be provided on the decoding circuit side. Now, as mentioned above, in this example, when decoding an MH coded image, the first EL of the MH code is detected, and decoding is started from the code that follows as the first line of the image, Play the actual image. This is because the MH-encoded image is stored in, for example, an image memory, which is not shown in the present case, but is present in the previous stage of the storage circuit 101 shown in the first diagram. From there
Specify the read start address of the image memory using the CPU, etc., read the MH coded image,
It is applied to the decoder circuit via the memory circuit 101. At this time, when the MH code read from the image memory is read from the middle of the image page, the EL code does not necessarily come at the beginning. In order to start decoding correctly even in this case, the first storage circuit 101 shown in the figure is cleared before the start of decoding, and then the storage circuit 101 is full of the MH code read from the memory (state shown in FIG. 2). The data is read until it becomes , and then the data (MH code) starts to be sent inside the decoder. Then, until the first EL code is detected, it is not treated as an image code, and the data is continued to be sent one after another and concentrated on detecting the EL code. After the EL code is detected, subsequent codes are treated as image information and decoded while controlling the amount of shift using the code length and the like. In this way, by finding the first EL code by the EOL detection circuit 112 described above, it is possible to determine the delimitation of the MH code and to reproduce the image synchronously. Now, when the operation to find the first EOL code to be input for the first time starts after the start of the decoding operation described above, data is sequentially sent from the memory circuit 101 to the register 103.
If all "0"s exist in 3, it will be connected to the MH code actually coming from the storage circuit 101 or a part (in the middle) of the MH code, and will be erroneously detected as an EOL code (000000000001). To avoid this, the initial state of register 103 is all set to "1". That is, C ₀ of register 103 ~
Set all C ₂₇ to “1”. As a result, the above E
Erroneous detection of L can be avoided. A method for presetting all registers 103 to "1" will be explained. FIG. 12 shows an example of the configuration of the register 103, that is, the register 103
consists of 28 flip-flop F/Fs.
Therefore, a preset pulse 9 is applied from the CPU, etc. to the preset terminals of all flip-flop F/Fs.
01 is input, and the Q outputs of all flip-flops are set to 1. Here, the flip-flop F/F may be, for example, SN74S74N manufactured by TI in the United States. Although this embodiment has been described above using the decoding of MH codes as an example, it can also be applied to decoding apparatuses for codes using other compression methods. In addition, the decoded image signal can be used for a variety of purposes, such as being recorded on a printer such as a laser beam printer, displaying it on a display such as a CRT, or saving it as a file as a bit image. . Furthermore, it goes without saying that the numerical values used in this example are not limited to these, and can be appropriately selected depending on the application, environment, etc. As explained above, the decoding operation of the compressed code can be reliably executed, and the decoding operation can also be performed in real time for image processing that requires high-speed processing. Furthermore, it becomes possible to effectively decode and supply compressed codes to output units such as printers that require high-speed, high-quality image recording. Further, it is possible to reliably detect abnormalities related to the decoding operation or transmission of compressed codes, and to minimize the effects thereof. Further, when performing a printing operation based on an image signal obtained by decoding a compressed code, good synchronization between the printer and the decoding processing section can be obtained. Furthermore, it is possible to reliably detect the line synchronization code that serves as a reference for decoding operations, thereby eliminating inconveniences such as out-of-synchronization of decoding operations. Further, even if the compressed code is supplied to the decoding circuit from the middle of one page or one line, line synchronization in the decoding operation can be ensured and decoding errors can be prevented. As explained above, according to the present invention, the compressed code to be decoded next is set at a predetermined position in the storage means by shifting a plurality of compressed codes stored in the storage means, and the compressed code that is set at the predetermined position is By decoding the compressed code, the run length data and the code length data of the compressed code are output, and prior to storing the compressed code in the storage means, the data that is not detected as an EOL code itself and other Since it has a storage means for storing specific data that will not be detected as an EOL code even if combined with a compressed code, the compressed code other than the EOL code input to the storage means can be stored as an EOL code.
This prevents the inconvenience of erroneously detecting a code as a code, and therefore, even if a compressed code starts to be stored in the storage device in the middle of a line or in the middle of a certain compressed code, the detection of the EOL code can be used as the standard. It becomes possible to reliably execute the decoding operation of the compressed code.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing a schematic configuration of an embodiment of the present invention, FIG. 2a is a diagram showing a storage type of MH codes in the memory circuit 101, and FIG. 2b is a diagram showing a continuous state of a plurality of MH codes. Figure 3 is a circuit block diagram showing the configuration of the bit shifter.
Fig. 4 is a circuit block diagram showing the configuration of the MH code decoding circuit, Fig. 5 is a detailed circuit diagram of the circuit block diagram shown in Fig. 1, and Fig. 6 is a timing chart showing the operation timing of each part of the circuit shown in Fig. 5. figure,
FIG. 7 is a circuit block diagram showing the configuration of a decoding error detection circuit, FIG. 8 is a diagram showing an example of the configuration of the printer, and FIG. 9 is a block diagram showing the circuit configuration for recording operation of the printer shown in FIG. Figure 10 is
11 is a circuit diagram showing the configuration of the detection gate shown in FIG. 10, FIG. 12 is a circuit diagram showing an example of the configuration of a register, 101 is a storage circuit, 102 is a multiplexer, 103 is a register, 104 is MH code decode logic, 104 is MH code decode logic,
It is a table ROM.

Claims (1)

[Scope of Claims] 1. In a compressed code decoding device that sequentially decodes compressed codes of undefined length including an EOL code indicating the end of each line of an image, the memory continuously stores a plurality of compressed codes that are input continuously. means for shifting a plurality of compressed codes stored in the storage means to set the next compressed code to be decoded at a predetermined position in the storage means; a decoding means for outputting run length data and code length data of the compressed code by decoding the compressed code; and a plurality of compressed codes executed by the shifting means in accordance with the code length data output from the decoding means. shift control means for controlling the shift amount of the EOL code; detection means for detecting whether or not the EOL code is present in the storage means; and based on the detection of the EOL code by the detection means, the decoding means decoding control means for decoding the compressed code following the code; and prior to storing the compressed code in the storage means, a decoding control means for decoding the compressed code following the code; 1. A compressed code decoding apparatus, comprising: storage means for storing specific data that is not detected as the EOL code even if the EOL code is detected as the EOL code.