JPH065890B2 - Decompression device for compression code - Google Patents

Description

The present invention relates to a decoding device for a compressed code by band compression encoding used for facsimiles, image electronic files and the like.

In an image transmission device such as a conventional facsimile or an image file device using an optical disk or a magnetic disk in recent years, by compressing and handling image data, the amount of data is reduced and transmission or storage operation is speeded up and efficiency is improved. I am trying to make it.

The image compression is a kind of so-called code conversion operation, and in the case of the modified Hoffman (MH) encoding which is a typical compression method, a continuous bit block of white or black pixels in an image is separately compressed. It is expressed in correspondence with the code. At this time, a compressed code having a short code length is made to correspond to a pixel bit block having a high occurrence frequency, while a compressed code having a long code length is made to correspond to a pixel bit block having a low occurrence frequency. The entire image is represented by another code string with a smaller number of bits by utilizing the bias in the occurrence frequency of the combination of.

Incidentally, the correspondence of the compressed code to this pixel bit block is determined empirically, and the code lengths of the compressed code are not uniform.

Further, as a rule of MH coding, an EOL (End of Line) code is used together with the compression code in order to indicate the synchronization or break of the image for each line. A device on the receiving side generally uses a configuration for line synchronization based on the EOL code. Therefore, when an error occurs in the decoding operation for some reason, the decoding circuit detects the EOL code to be input thereafter, and starts the encoding operation according to the detection operation. Like this, EOL
The code plays an important function in the decoding operation.
If the EOL code is erroneously detected, the subsequent decoding operation will be disturbed and accurate image reproduction will not be performed.

Further, since the code lengths of the code codes are not uniform as described above, the code lengths of one or a plurality of code codes forming one line are not constant. Therefore, the interval at which the EOL code is input is not constant, and it is difficult to detect this EOL code.

In addition, there are some compressed codes having a shorter run length than the code length among the above-mentioned MH-encoded compressed codes. When such compressed codes are decoded, the line length of a high-speed printer is The compressed code to be decoded next is not ready before the end of the image reproduction corresponding to, and in such a case, there is a possibility that the decoding operation of the compressed code is not in time for the image reproduction of the high speed printer.

The present invention has been made in view of the above points, and decodes a compressed code of an indefinite length including a specific compressed code whose run length is shorter than the code length at high speed, and compresses the compressed code including this specific compressed code. In order to reliably detect the EOL code that serves as the reference of the decoding operation even in the configuration in which the code is decoded at high speed, in detail, the indefinite-length compressed code including the EOL code indicating the end of each line of the image is sequentially decoded. In a compressed code decoding device, a storage unit that stores a plurality of consecutively input compressed codes and a compressed code that should be decoded next by shifting the plurality of compressed codes stored in the storage unit Run length data and compression are performed by shifting means set at a predetermined position of the storage means and decoding the compression code set at a predetermined position of the storage means. Decoding means for outputting the code length data of the code, and when the compressed code decoded by the decoding means is not a specific compressed code having a shorter run length than the code length, the shift means converts the code length data into the code length data. Shift control means for sequentially executing the following shifts, and in the case of the specific compression code, for executing the shifts according to the code length data at once by the shift means,
When the compressed code decoded by the decoding means is the specific compressed code, a plurality of different bits shifted by 1 bit from the predetermined position of the storage means corresponding to the maximum shift amount executed at one time by the shift means EO in position
A plurality of detecting means for respectively detecting whether or not the L code exists, and a decoding control means for decoding the compressed code following the EOL code by the decoding means based on the detection of the EOL code by the plurality of detecting means. There is provided a compressed code decoding device having:

A detailed description of the invention is provided below.

First, an outline of an embodiment of the present invention will be described using the circuit block shown in FIG.

In FIG. 1, reference numeral 101 denotes a storage circuit, which has been input from, for example, a reader that photoelectrically reads an image, an electronic file that files an image, or a receiver that receives image information via a transmission line such as a telephone line. A circuit that stores a so-called MH code (Modified Hoffman) code obtained by compressing and encoding an image signal using a separate means so that it can be sequentially read in 16-bit (1 word) units, for example, It is a circuit that can be realized by a RAM (random access memory) or a latch circuit. Also, the memory circuit
The storage format of the MH code in 101 is as shown in FIG. In other words, the nature of the MH code is that the code lengths are not uniform (minimum 2 bits to maximum 13 bits).
However, regardless of the code length, there is no 1-bit vacancy, and a serially concatenated bit string is parallel-converted every 16 bits and arranged as shown in FIG. 2 (b). In FIG. 2 (b), WB and BB are MH codes indicating white and black pixels, respectively.
The number after BB and BB indicates the run length indicated by the code. For example, WB8 is MH indicating the run length 8 is white.
Is the code. In this format, the MH code delimiter and the word (16 bit) delimiter do not necessarily match. Further, the memory circuit 101 has a function of sequentially outputting the subsequent words in parallel in accordance with external control.

In FIG. 1, 102 is a so-called multiplexer (data selector). Further, 103 is a register having 28-bit parallel input and output, which is given to the input side of the register 103 from the memory circuit 101 through the multiplexer 102.
The function of temporarily storing the MH code and the role of giving the MH code already stored in the register 103 as an output to the MH code decoding logic 104 and the MH code decoding table ROM (read only memory) 105 described later. Have a

The multiplexer 102 and the register 103 form a so-called loose bit shifter capable of serial shift of data and jump shift of n bits. This bit shifter is controlled by the output of the MH code decode logic 104 and MH code decode ROM 105, which will be described later,
By the method described above, the memory circuit 10 regardless of the boundary of the MH code
This functions to shift the MH code stored in the register 103 from 1 by the required number of bits and store it. FIG. 3 (details will be described later) is a diagram showing a detailed configuration of the bit shifter, and the MH code string illustrated in the register 103 is an appropriate control for the MH code illustrated in the memory circuit 101 illustrated in FIG. MH showing a white run length 8 through
It shows a state in which the code WB1 (10011) has come to a position where it can be decoded. That is, the output CO of the register 103 shown in FIG. 3, that is, the state in which the first bit of the MH code is output to the LSB output is set as a decodable position, and is hereinafter referred to as "cue completion". Therefore, the arrangement of the codes in the register 103 in FIG. 3 indicates that the MH code WB8 indicating the white run length 8 is in the "cue completed" state.

In FIG. 1, reference numeral 104 denotes an MH code decoding logic (hereinafter referred to as logic 104), which is the following four types of codes, in which the run length indicated by the MH code is shorter than the code length of the MH code, that is, the white run length. 1 (00 with MH code
0111, code length = 6> run length = 1), white run length 2 (MH code 0111, code length = 4> run length = 2), white run length 3 (MH code 100)
0, code length = 4> run length = 3) and black run length 1 (MH code 010, code length = 3> run length = 1).

In the following description, the above four types of MH codes indicating the white run length 1, the white run length 2, the white run length 3 and the black run length 1 will be collectively referred to as an HSC code. .

In FIG. 1, reference numeral 105 denotes an MH code decode RM (hereinafter referred to as RM105), which is a circuit that mainly decodes all MH codes including four kinds of MH codes that the logic 104 takes charge of decoding.

The logic 104 and the ROM 105 divide the MH code that is in charge of decoding according to the difference in the processing speed and method of the MH code. These two decoders each time the MH code in the register 103 is “cue completed”,
The output of the run length of the MH code, the code length and the color of the image of black or white, the make-up code or the termination code, and whether or not they are present.

Reference numeral 112 denotes an EOL detection circuit, which detects whether or not a line synchronization code, that is, an end of line (EOL) code exists in the MH code stored in the register 103 in bit serial, and the storage position thereof. To do.

In FIG. 1, reference numeral 108 denotes a run length counter, which is a run length of the maximum make-up code from the count number "0", that is, a binary number capable of counting "2560" or more.
It is a counter. The run length counter 108 outputs a count end signal (ripple carry CR of the counter in this example) every time the run length of the MH code output from the logic 104 or the ROM 105 is counted.

Reference numeral 109 is a flip-flop, which receives a count end signal (ripple carry CR) from the run-length counter 108 and inverts the output each time. However, as will be described later, the output is controlled not to be inverted by the make-up code count end signal. The output of this flip-flop 109 was read from the memory circuit 101.
It is an image signal obtained by decoding the MH code.

Reference numeral 107 is a code length counter capable of counting the maximum code length "13" or more of the MH code. binary·
By serially shifting or jump-shifting the MH code that had been "cue completed" in the register 103 by the counter, it was swept out of the 103 register as a decoded code, and the subsequent MH code was at the "cue completed" position. When shifting to, the shift amount is counted and controlled.

106 is a 4-bit accumulator. As described above, the MH code fetched from the memory circuit 101 into the register 103 is sequentially swept out from the register 103 when it has been decoded, which causes an empty bit in the register 103. Therefore, the accumulator 106 counts the number of empty bits in the register 103, and each time 16 empty bits are generated, a new MH code is read from the memory circuit 101 by one word (16 bits).
Fill empty bits in register 103 in parallel. Thus, the sequence of the MH code given from the register 103 to the logic 104 or the RM 105 is controlled so as not to be interrupted, and a high-speed decoding operation is enabled.

Reference numeral 110 shows a control circuit for controlling input / output signals between the blocks 101 to 109 shown in the first figure.

As described above, the MH code is converted into the image signal, that is, the MH code is decoded. The decoded image signal is a printer
The image is recorded on the recording material by being supplied to 111.
The printer 111 outputs a horizontal synchronizing signal HSYNC which is a synchronizing signal for each scanning, and this HSYNC is used for the timing of the decoding operation.

Next, examples of the present invention will be described more specifically. This embodiment is a so-called "high-speed, high-speed," which is used to directly output an image signal, which is the result of decoding the MH code, which is an image compression code, to a high-speed printer such as a laser beam printer without providing any image memory. It provides "real-time MH decoder". Therefore, the high processing speed of the MH decoder and the image output of the MH decoder (in this example, the image frequency = +
The problem of synchronization between high-speed printers such as laser beam printers should be solved. Therefore, in order to solve these problems, a desired "high-speed real-time MH decoder" is realized based on the processing method described below.

(1) The MH decoder and the printer are synchronized with the EL of the MH code and the horizontal synchronizing signal which is a synchronizing signal for each line of the printer.

(2) Jumping by the code to be swept out as a method of sweeping out the MH code that has been “delayed” and decoded in the first register 103 and shifting the subsequent MH code to the “cueing completed” position・ Shift and serial ・
Use one of two methods of shifting.

A specific configuration for achieving these two points will be described with reference to the drawings.

FIG. 8 is a perspective view showing the configuration of an embodiment of the laser beam printer shown as an example of the output section in FIG.

This print is based on an electrophotographic method using laser light, and 201 is a photosensitive drum rotatably supported in the housing Ha. Reference numeral 202 denotes a semiconductor laser that emits laser light La, and the emitted laser light La is made incident on the beam expander 203 and becomes a laser light having a predetermined beam diameter. Further, the laser light is incident on the polyhedral mirror 204 having a plurality of mirror surfaces. The polyhedral mirror 204 is rotated at a predetermined speed by a constant speed rotation motor 205. The laser light emitted from the beam expander 203 is scanned substantially horizontally by the polygon mirror 204. Then, an image is formed as spot light on the photosensitive drum 201 charged to a predetermined polarity by the charger 213 by the image forming lens 206 having the f-θ characteristic.

A beam detector 207 detects the laser light reflected by the reflection mirror 208, and the photosensitive drum 20 is detected by this detection signal.
The timing of the modulation operation of the semiconductor laser 202 is determined in order to give desired optical information on 1.

A high-resolution electrostatic latent image is formed on the photosensitive drum 201 by the laser light image-formed and scanned on the photosensitive drum 201. This latent image is visualized by the developing device 209, and then the cassette 210, 2
The image is transferred onto a recording material housed in any one of 11, and the recording material is further passed through a fixing device 212, whereby the image is fixed on the recording material and is ejected as a hard copy to an ejection portion (not shown).

FIG. 9 shows an embodiment of a printer circuit for modulating the semiconductor laser of FIG. 8 with a predetermined image signal.

Image signal VI decoded and input from input terminal IN
DEO is a first line buffer 301 and a second line buffer 3 each including a shift register having a number of bits equal to the number of pixels for at least one scan for each image signal group for one scan.
The signals are alternately input to 02 under the control of the buffer switch control circuit 303.

Furthermore, the first line buffer 301 and the second line buffer 3
The image signal input to 02 is alternately read for each scanning by using the beam detection signal from the beam detector 304 as a trigger signal and applied to the laser driver 305.

The laser driver 305 modulates and controls the semiconductor laser 306 based on the input image signal to control the emission of laser light.

By having two line buffers, the image signals already stored in the other line buffer are input to the laser driver 305 while the image signals input one after the other are input to the laser driver 305. It is possible to handle the input of image signals.

The beam detection signal from the beam detector 304 is also transmitted to the decoding processing circuit as the horizontal synchronization signal HSYNC, and is used for synchronization between the decoding processing and the printer operation as described later.

The image signal decoded by the printer is input via two line buffers, that is, a double-buffered buffer including a first line buffer 301 and a second line buffer 302. This double buffer configuration is used to perform the correction operation when there is an error in the decoding operation. That is, if an error occurs in the decoding operation while the image signal decoded by the decoding circuit is being stored in one of the line buffers, the printing operation by the image signal of the current line in which the error occurred is prohibited and the other line buffer The printing operation is performed by the image signal of the previous line already stored in.

As a result, printing is not performed due to the image signal that has been erroneously decoded, so that it is possible to remove the influence on the reproduced image.
It should be noted that at least two lines of images by the same image signal are overlapped by this correction operation, but in the high-resolution (for example, 16 pel / mm) recording operation used in this example, the reproduced image is greatly affected. is not.

In FIG. 4, 105 is the MH code table ROM shown in FIG.
In reality, it is composed of a plurality of RMs (read only memory). Below is RM105
When the contents of the above are schematically explained, AD0 to AD13 are address terminals of the RM 105. Further, 0 to O11 are output terminals of the RM105. The format of the contents stored in ROM 105 is the LSB of the MH code to be decoded supplied from register 103.
Align bits to the address terminal AD0 of RM105
Each bit of the code is sequentially applied to the ADB to AD11 of the address terminal of the RM105 in the MSB direction. A signal B / -ROM indicating the color of the MH code is input to the address terminal AD13 (black = 1, white =
0) shall be given. If the MH code is shorter than 12 bits, the insufficient bits are ignored (DON'T CAR
E) to do. The EL code is treated as a make-up code. In addition, the color code bit (AD13) of the make-up code of run length 1972 or higher is ignored) (DON'T CAR
E).

The contents of the MH code to which each address is given are written in the ROM 105 as the storage data of the address determined by the above, and the output corresponding to each MH code is output terminals O _{0 to} O ₁₁
Output to. That is, the output terminal 0 outputs the signal M / which becomes "1" when the decoded MH code is the make-up code and "0" when the decoded MH code is the termination code. The output terminal 1 outputs a signal "0" when the decoded MH code is a white code (00110101) with run length 0 or a black code (0000110111) with run length 0, and a signal ▲ ▼ that becomes "1" at other times. Output.

The output terminals 2 to 5 output 4-bit outputs CL0 to CL3 in a format in which each MH code length (the number of bits) is expressed in 2's complement.
However, the output terminal 5 is the LSB of the code length. The output terminals 6 to 11 output 6-bit outputs RL0 to RL5 in a format in which the run length of each MH code is expressed in 2's complement. However, the output terminal 11 is the LSB of the run length.
For the make-up code, only the upper 6 bits of the run length binary number expression are assigned to the output terminals to 11. This is because the make-up code in the MH code can express its run length with only the upper 6 bits. The output 0 to O11 of the ROM 105 when the MH code WB8 (10011) indicating the white of the run length 8 is decoded at 402 in FIG. 4 is illustrated (the MH code table used in this embodiment is CCITT YELLOW BK Fascicle VII.2 Rec. T.4
According to TABLE1 / T.4 and TABLE2 / T.4).

In FIG. 4, reference numeral 104 denotes the MH code decoding logic shown in FIG. 1, and in this embodiment is a detection logic constituted by an AND gate and an OR gate. The signal {circle around (1)} which is the output of the logic 104 becomes "0" when the HSC code, that is, the MH code indicating that the run lengths 1, 2 and 3 are white and the MH code indicating that the run length 1 is black are detected. The outputs ▲ ▼ to ▲ ▼ represent the code lengths of the above-mentioned four types of MH codes (HSC codes) in binary numbers, which are inverted and output.
Fig. 4 MH code white 1W showing run length 1 white in Fig. 404
An output when B1 (000111) is decoded is illustrated.

The reason why the logic circuit is used for decoding the HSC code is that the current ROM address system for high-speed processing cannot sufficiently cope with time.

The operation of the bit shifter shown in FIG. 3 will be described with reference to Tables 1 and 2.

FIG. 3 shows the multiplexer shown in FIG. 1 and comprises two tri-state multiplexers 1021 and 1022. When the control line from the accumulator 106 to the multiplexer 102 is "0", the outputs A7 to A27 from the multiplexer 1022 side to the register 103 are all invalidated because they become tristate floating.
The outputs A0 to A27 from the multiplexer 1021 side are valid for 103 and become the outputs C0 to C27 of the register 103. At that time, the multiplexer 1021 selects the input signals C0 to C27 from the register 103 by the input lines S0 to S2. Table 1 shows the selection method. For example, in the case of S ₀ = S ₁ = 1 and S ₂ = 0, the outputs C _{3 to} C ₂₇ of the register 103 are taken in, and the outputs A _{0 respectively.}
~ Output as A ₂₄ .

Next, when the control line to the multiplexer 102 is "1",
The outputs A0 to A6 of the multiplexer 102 are selectively given from the multiplexer 1021 by the input lines S0 to S2 in the same manner as when the control line is "0". Output A7 from multiplexer 102
~ A27 multiplexers other than those indicated by Y in Table 2
Side becomes valid, and outputs A7 to A27 from the multiplexer 1021 side
Of those, those other than those indicated by Y in Table 2 become floating and invalid. Further, as shown in Table 2, outputs A7 to A27 given from the multiplexer 1022 to the register 103 are the multiplexer 1
It is selected by the input lines Σ0 to Σ2 to 022, but the bit indicated by Y in Table 2 is selected from the multiplexer 1021 side. The number of Y is set by controlling the tri-state state of the multiplexer 1021 by the input lines ST7 to ST11 output corresponding to the input lines Σ0 to Σ2 to the multiplexer 1022. The circuits of the multiplexers 1021 and 1022 in FIG. 3 can be easily realized by a commercially available multiplexer (for example, IC, F215 manufactured by Fairchild, USA) and a gate circuit. Also, the multiplexer 10
The outputs selected by A0 to A27 as outputs to the register 103 in 2 are latched in the register 103 by the clock CK.

By configuring the bit shifter as described above, it is possible to shift the MH code signal input from the memory circuit 101 in 16-bit parallel by an arbitrary number of bits. This allows
For MH codes with irregular code lengths, the above-mentioned "cue completed"
Can be in a state.

As described above, what is the MH code is determined by observing the code string moving in the register 103. The moving method is 1 by the bit shifter 102 or the like.
A maximum 6-bit jump shift occurs when a serial shift that moves bit by bit and an MH code that is treated as an HSC code are detected. That is, the code string in the 103 register is controlled so that the maximum movement is 6 bits or less in one clock time.

Therefore, when the EOL code (000000000001) moves in the register 103, even if the movement amount is incorrect from the previous time, the LS
The B bit always appears in C0 to C5 of the register 103.

Now, generally, when decoding an MH code, detection of the EL code is extremely important due to its code system. Hereinafter, the EOL detection circuit 112 shown in FIG. 1 will be described in detail.

That is, the EOL code is a code that separates each line of the image, and at the same time, it has the role of indicating the I of the MH code that follows it. Therefore, if the EOL code is detected as a detection error during decoding, it immediately follows it. The delimiter of each MH code becomes unknown, and the image for one line cannot be decoded. Also, the EOL of each subsequent image line cannot be detected depending on the detection method, and eventually the printed image is disturbed and almost It will spread to the extent that it cannot be used.

Therefore, in the MH code sequence, even if there is an error in sending or receiving,
Even if the MH code is a little wrong, it is important to have an EOL detection method that does not cause an error in detecting the EOL code as much as possible.

If the EOL code is reliably detected, the code error can be recovered within one image line.

FIG. 10 is a diagram showing a detailed configuration of the EOL detection circuit 112. As shown in FIG. 10, a 12-bit EL code (0
In order that the LSB of (00000000001) may come anywhere in C0 to C5 of the register 103, at least six kinds of detection gates 1001 corresponding to the shift amount which can be shifted at one time of the register, that is, 6 are provided in parallel. As a result, the EL code detection failure is prevented by monitoring the data stored in the register 103. Then, the detection gate 1001 that has detected the EOL code outputs a detection signal indicating the position of the EOL code in the register 103, as shown in ▲ ▼ to ▲ ▼, respectively.

This method prevents the EL detection from being mistaken unless the EOL code itself includes an error bit.

Therefore, the image code error can always be recovered within one line. In addition, the probability that the EOL code contains an error bit is extremely low compared to the probability that the error code is included in the image code, and is extremely low in practical use and can be ignored.

FIG. 11 shows the details of the detection gate for detecting the EOL code. As shown in the figure, the configuration is such that 12-bit data is fetched in parallel, and 11-bit data excluding the MSB is applied to the 12-input NAND gate 1002 together with the above-mentioned MSB via the inversion gate INV. As a result, the EOL code is decoded, and when the EOL code is decoded, the output of the NAND gate 1002 becomes low level.

Outputs 0EOL to 5EOL of the EOL detection circuit 112 of FIG. 10 are transmitted to the code length counter 107 and the accumulator 106. Based on this signal, the accumulator 106 causes the register 103 to shift by the code length of the EOL code.

That is, the EL detection circuit 112 shown in the tenth figure shows the MH code or F1LL before the EOL code in the register 103 from the detection position.
EOL may already be detected with bits still remaining. Therefore, among the EOL codes detected by the EOL detection circuit 112, EOL code detection signals other than the signal ▲ ▼, that is, ▲
When ▼ to ▲ ▼ are detected, the accumulator 106 shifts the code length of the EL code, that is, 12 bits after the remaining code before the EL code in the register 103 is swept from the register 103 by the shift operation described above. The register 103 is made to perform further.

As a result, the EOL code has been swept out, and the state of the "image heading completed" of the image MH code at the beginning of the next line to be decoded is set. Further, by doing so, it is possible to eliminate the waste of time due to the decoding operation of the EOL code which is not the image information similarly to other compressed codes.

Next, a detailed description of the entire block shown in FIG. 1 will be given with reference to FIG. Since the operation of the circuit shown in FIG. 5 is complicated, some conditions are set to facilitate the explanation, and the decoding operation of the MH code which is considered to be more general is taken as an example. The basic operation will be described, and then the establishment of the setting condition will be described.

FIG. 2 (b) is used as an example of the MH code string to be decoded. As a principle of operation of this circuit, before the horizontal synchronizing signal HSYNC of the printer arrives, the EL code appearing at the end of FIG. 2 (b) is swept from the register 103 shown in FIG. 3 by the bit shift operation described above. , MH code WB8 indicating the white run length 8 which is the MH code next to EL (that is, the MH code of the first image signal of the line to be decoded from now on) is stored in the register 103 as "cue completed" as described above. Suppose that the printer is waiting for HSYNC from the printer.

FIG. 6 is a time chart of the main part of the circuit shown in FIG. In FIG. 6, HSYNC601 is a synchronizing signal in the main scanning direction of the printer described above, which is generated for each main scanning line. Using this as the reference for the time chart, this time t ₀
And CK600 is the basic clock, and its frequency is the same as the image frequency. VEN602 is a section signal that defines the effective image section within the main scanning line. INi603 is a section signal
A pulse one clock (1 bit) before VEN starts, EOS60
4 is a pulse of the last clock (bit) of the section signal VEN.

As described above, when the recording operation based on the image signal obtained by decoding the compressed code (MH code) is performed by the laser beam printer, the horizontal synchronization signal HSYNC is set at a predetermined position of the scan line of the raster scan by the laser light. , Is based on the beam detection signal that detects the arrival of the laser beam, and the section signal VEN is scanned by the laser beam and the laser beam scans the photoconductor (drum) on which a latent image is formed. Based on the section.

As is clear from these, the signals 600 to 6 in FIG.
The time relationship of 04 should generally be fixed to a fixed value. In this example, a fixed length of 64 clocks is set between HSYNC601 and iNi603. In addition, the section of VEN602 has the number of pixels of one line, but in this example, it is 4096 bits (pixels).

In FIG. 6, at time t ₀ , the circuit of FIG. 6 is set to the initial state for each main scanning of image output. That is, as described above, the MH code (WB8 (10011) indicating the white run length 8 in this example) of the head image of each line is registered.
103 is "cue completed", and the output of the register 103-C0
~ C12 ((10011.0010.0001) in this example)
Are provided to the logic 104, ROM 105, etc.

Similarly, the value of the code length counter 107 is (-1) = (11
11B). At this time, (-1) is defined to mean "cue completion". Also, each flip-flop 510,10
9,515 is in a reset state and flip-flop 509 is in a set state.

Flip-flop 509 is set (Q = 1)
After detecting the EOL of the MH code, it indicates that the sweeping of the EOL code from the register 103 is completed. In addition, when the flip-flop 510 is set (Q = 1), the run length latch 513 is busy (B = 1) as described later.
usy). F / Flip 515 is B /
Output ROM signal as output Q. This flip
When the output of flop 515 is 1, MH to be decoded from now
-B / -ROM signal indicating that the color of the code is black. Similarly, when the output Q is 0, it indicates white.

Also, assume that the run length counter 108 is stopped,
The value is assumed to be 0. SFTEN605 is a control line, and when this is 1, it means that the register 103 may shift data (MH code). Further, for simplicity, it is assumed that the output signals Σ0 to Σ2 and the signal of the accumulator 106 are zero. That is, according to this assumption, 28 of register 103
All bits are a valid MH code string, indicating a non-empty state.

The above is the state at time t ₀ .

Now, at time t ₁ , the flip-flop 509 shown in FIG. 5 is reset by the fall of the HSYNC signal 601 shown in FIG. 6, and the signal ▲ ▼ shown in FIG.
-SFTEN signal 605 goes to 1 through gate 508. When the SFTEN signal 605 is 1, the counter 107 shown in FIG. 6 is count enable. At the same time, the outputs C0 to C12 held by the register 103 are given to the address of the ROM 105 at time t ₁ .
(10011 ×××××××× in this example), and among the outputs of the RM 105, the code lengths CL0 to CL3 are given to the code length counter 107 via the gate 503 and the gate 504. At the same time, since the signal 607 is 0, the counter 107 enters the load mode and the values of CL0 to CL3 are loaded into the counter 107 by the clock of t ₁ . In this example, (-5) which is the two's complement of the code length 5 of the MH code WB8 indicating the white of the run length 8 is loaded.

The outputs RL0 to RL5 and M / of RM105 are provided as inputs to run length latch 513. At the same time, the Q output of the flip-flop 515 is also input to the run length latch 513 as the B / -ROM signal 620. At this time, RL
The CH signal 608 controls the latch 513 to be latch enable by ₁ and latches the values of D0 to D7 in the latch 513 at the clock of t ₁ .

At the same time, flip-flop 510 is set to ₁ at time t ₁ . Also, flip-flop 515 is inverted. The BUSY signal 609, which is the Q output of flip-flop 510, is one, indicating that latch 513 is latching a valid run length. When the B / -RM signal 620, which is the Q output of the flip-flop 515, is 1, it indicates that the color indicated by the MH code that should be "cue completed" in the register 103 is black. (Also, the B / -RM signal 620 is 0
, The color is white. The SFTEN signal 605 is applied to the multiplexer 102 as an S signal via the gates 505 and 506 and controls so that the data in the register 103 is shifted by 1 bit. As a result, the transfer of the necessary data from the MH code in the register 103 to the subsequent stage is completed, so that the MH code is used and can be counted by the SFTEN signal 605. Bit shift is performed from the counter 107 until the carry-out signal CRO606 is generated, and the used MH code is registered in the register.
Swept from 103. That is, in this example, the 1-bit shift of the register 103 is repeatedly continued until the value of the counter 107 set to -5 becomes the value of (-1).

When the value of the counter 107 becomes (-1), the MH that has been used now
Code (MH code WB that indicates white with run length 8 in this example)
After the sweep of 8) is completed, the next MH code (run length 6
The MH code BB6) that indicates the black color is “Completed at the beginning” in the register 103), but the previous MH code W still appears in the latch 513.
Flip flop due to remaining run length of B8
The 510 remains the set. Therefore, the CRO of counter 107
When the signal becomes 1, the output of the gate 511 becomes 0, and eventually the SFTEN signal 605 becomes 0, so that the counter
107 stops. Similarly, when the SFTEN signal is set to 0, the S0 to S2 signals are all set to 0, the register 103 stops shifting, and the data is held. Therefore, the state of “cue completion” BB6 continues until time t ₂ .

At time t ₂ , the iNi signal 603 causes the ▲ ▼ signal 610 to become 0, and the run length (8 bits of white in this example) held in the latch 513 is transferred to the counter 108 by the ▼ signal 610 via the multiplexer 514. Be done. At the same time, the flip-flop 510 is reset by the signal 610. As a result, the latch 513 is emptied and the busy state is canceled. Therefore, the output of the gate 511 becomes 1 and the SFTEN signal 605 becomes 1 in the same manner as described above, and the run length obtained by the MH code which is "cue completed" in the register 103 is latched in the latch 513.

Similarly, the MH code is sequentially decoded thereafter.

Based on the run length (-5 in this example) loaded into the counter 108 at time t ₂ , the VEN signal 602 generated from the next bit at time t ₂ causes the counter 108 to start counting. And issue a CR1 signal 611 (time t ₃ in this example) when the value of the counter 108 has decreased to (-1). Also, B from the latch 513
/ Flip by color of image specified by signal 621
Set flop 109. As a result, the first
The second MH code is the image VIDE0 (white 8 bits in this example)
I was able to convert to.

After the rising edge of the VEN signal 602, the ii signal 603 remains 0 until a new HSYNC 601 arrives. Therefore VE
After the rising of the N signal 602, for example, at time t ₃ , the iNi signal
CR1 instead of 603, indicating a count-up of counter 108
The signal 611 resets the flip-flop 510 to release its busy state, and the run length obtained by the subsequent decoding of the MH code can be taken into the latch 513.

By the way, in the above description, the code length of the MH code is equal to or shorter than the run length length,
If the used MH code to be swept out from the register 103 is serially shifted by setting the signals S0 = 1, S1 = S2 = 0 from the time point of “completion of cueing” the MH code, the MH code can be obtained. However, if the run length length of the MH code is shorter than the code length, serial shift as described above can be performed while sweeping the code from the register 103 (shift In the middle 0, the count of the run length of the MH code is completed in the counter 108. At this point, the next run length needs to be taken from the latch 513 to the counter 108 in order to eliminate the discontinuity of the image. Since the register 103 is not in the “cue completion” state for the next MH code, the latch 51
The run length that should be captured in 3 is not output from ROM 105.

After all, in this case, the image recorded by the printer is interrupted, and the image cannot be output in real time. Such inconvenience occurs when decoding the above-mentioned HSC code, that is, the MH code indicating that the run lengths 1, 2 and 3 are white and the MH code indicating that the run length 1 is black.

Therefore, in such a case, only the MH code, which is the above-mentioned four types of HSC code, is serially shifted by the code length data CL0 to CL3 from the ROM 105 using the MH code decoding logic 104, and the latter stage is equivalent. Activate the circuit of. That is, the logic 104 generates a load value (-1) by the signal and loads it into the counter 107 through the gate 504 so that the counter 107 can be loaded with (-1). or,
At this time, the outputs CL0 to CL3 from the ROM 105 are inverted by the gate 503 by the signal. Also, logic 104
Outputs the jump amount corresponding to the code length of the decoded MH code to SF1 and SF2 as ▲ ▼ to ▲ ▼, and operates the multiplexer 102 via S0 to S2. As a result, it is possible to shift a plurality of bits in 1 bit time, in other words, it is possible to "cue out" in the register 103 of the next code to be decoded in 1 bit time. This jump amount is also input to the accumulator 106 and is cumulatively added to the number of empty bits in the register 103.

By the above two shift methods, a series of operations from "cue completion" to "run length latch" and "run length count" are repeated at high speed to execute decoding without interrupting the image supplied to the printer unit. An EOL detection circuit 112 outputs a signal 0 EOL signal when detecting that an EOL code appears at the outputs C0 to C11 of the register 103. When the EOL code indicating the end of one line is detected by the EOL detection circuit 112, the EOL detection circuit 11 is passed through the timing adjustment circuit 523.
The signal 0EOL from 2 sets the flip-flop 509, and the signal 613 becomes 0. As a result, the SFTEN signal 605 eventually becomes 0, the register 103 is stopped until the next HSYNC comes, and the MH code waits for HSYNC in the state of “cue completion”. In this way, good synchronization between the printer and the decoding operation can be obtained.

An image is formed by repeating the scanning for each line as described above.

Next, the decoding error detection method will be described with reference to FIG. The circuit shown in FIG. 7 is connected to the appropriate position shown in FIG. 1 or 5. In FIG. 7, reference numeral 801 is an inverter.
802 is an adder, 803 is a latch, 804 is a comparator, 805 is a latch, and 806 and 807 are flip-flops.

FIG. 7 820 is the same signal as the signal 820 output from the latch 513 through the multiplexer 514 in FIG.
As described above, the run length as a result of decoding the MH code is expressed in 2's complement.

Now, the adder 802 and the latch 803 constitute an accumulator. The carry from the lower LSB of the adder 802 is 829 signals
It is set to 1 by (1) and eventually the output 82 of the adder 802
1 is the two's complement of run length 820. Therefore output 821
Is a binary representation of the run length positive integer. The addition to the latch 803 is continued at the timing of 610 in FIG. 6, that is, the timing of loading the run length to be counted into the counter 108 shown in FIG. The latch 803 is cleared for each line of the main scan and for each HSYNC signal 601 shown in FIG. That is, the output 822 of the latch 803 represents the cumulative value of the run length for each line by a binary number. On the other hand, the latch 805 has a constant run length for each line (in this example, 40 pixels corresponding to the number of pixels on one line).
96) is held by being notified from the CPU or the like by the signal 824. The comparator 804 is the run length 822 (A) accumulated in the latch 803 and the correct answer value 82 from the latch 805.
It is a comparator circuit that compares 3 (denoted as B).

The flip-flop 806 converts the EOS signal 604 shown in FIG. 6, that is, at the last bit of each line, into the converter.
It is set by the output 825 of the AND gate 808 when the signal 831 indicating that A = B is not output from 804. That is, the setting of the flip-flop 806 means that the cumulative value A of the run length is the correct correct value B (40 in this example).
96) and that the MH code or its decoding was incorrect.

When the signal 832 output from the comparator 804 is input when the state of A> B is entered, the flip-flop 807 is immediately set by the output 826 of the AND gate 809 even during the accumulation of run lengths. That is, the Q output 828 of the flip-flop indicates that the cumulative run length value has exceeded the planned correct value (4096 in this example, that is, the number of pixels in the VEN602 section) in the middle of the line. This indicates that a large erroneous decoding error has already occurred during the decoding of one line.

The flip-flops 806 and 807 are shown in FIG.
▼ 613 is "0", that is, EL (End of line) is not reset until the EOL detection circuit 112 detects and the HSYNC 601 is input, and is reset by the output of the gate 810 by the input of the HSYN signal 601. Therefore, by detecting the output 827 or the output 828 of each of the flip-flops 806 and 807 and devoting it to the EOL detection by the separate EOL detection circuit 112, it is possible to minimize the synchronization deviation due to a decoding error or the like.

In this example, the run length is cumulatively added by the accumulator, but this can be replaced with a method of sequentially subtracting the run length value from a predetermined number, for example, 4096, and detecting a borrow from the subtraction counter.

As described above, the decoding error occurs and the flip-flop
When 806 or 807 is set, its output is transmitted to the buffer switch control circuit 303 of the printer circuit shown in FIG.

The buffer switch control circuit 303 performs a buffer selection operation for alternately selecting the input / output of the line buffer of the printer having the double buffer structure as described above. When the set signal, that is, the decoding error detection signal is input from the flip-flop 806 or 807, the image signal of the current line in which the decoding error occurs is invalidated, and the previous line is replaced with the line in error. In order to reuse the image signal of, the line buffer selection control is performed so that the line buffer in which the image signal of the previous line is stored is reread. That is, for example, when a decoding error occurs while the image signal being decoded is being stored in the first line buffer 301, the image signal currently stored in the first line buffer 301 is invalidated, and the current image signal After the reading of the read second line buffer 302 is completed, the same image signal is read again from the second line buffer 302.

As a result, the print operation is not performed by the image signal of the line in which the decoding error occurs, and the influence on the recorded image can be removed. It should be noted that even if the number of line buffers of the printer is two or more, the same process can be performed. A line buffer for correcting this error may be provided on the decoding circuit side.

Now, as described above, in the present example, when decoding the MH coded image, the head EL of the MH code is detected,
Decoding is started from the code following that as the first line of the image, and the actual image is reproduced.

This is because the MH-coded image exists in the preceding stage of the storage circuit 101 shown in the first illustration, although not shown in the present drawing. For example, it is stored in an image memory or the like. From there, the CPU or the like specifies the read start address of the image memory, reads the MH coded image, and supplies it to the decoding circuit via the memory circuit 101.

At that time, the MH code read from the image memory is, for example,
When the color is read out in the middle of the image page, the EL code does not always come at the beginning. In order to start decoding correctly in this case as well, the first illustrated memory circuit 101 is set to the clear state before the decoding is started, and then the MH code read from the memory is full in the memory circuit 101 (state of FIG. 2). Until, the data (MH code) is sent to the inside of the decode. Then, until the first EL code can be detected, it is not treated as an image code, and data is sent continuously one after another, and the focus is on detecting the EL code.

After the EL code is detected, the subsequent codes are treated as image information and are decoded while controlling the shift amount by the code length or the like. In this way, the first EL code is changed to the above-mentioned EO.
By finding it by the L detection circuit 112, it becomes possible to judge the delimiter of the MH code and to synchronously reproduce the image.

Now, the first input after the above decoding operation is started
When the operation of finding the EOL code of is started, data is sequentially sent from the memory circuit 101 to the register 103. However, if all "0" s exist in the register 103 before the start, the memory circuit 101 actually receives the data. In addition to the MH code or a part of the MH code (on the way), it will be erroneously detected as the EOL code (000000000001). Register 103 to avoid it
The initial state of is set to "1". Ie register 10
C0 to C27 of 3 are all set to "1". As a result, the above E
False detection of L can be avoided.

A method of presetting all the registers 103 to "1" will be described. FIG. 12 shows an example of the structure of the register 103, that is, the register 103 is composed of 28 flip-flops F / F. Therefore, the preset pulse 901 is input from the CPU or the like to the preset terminals of all the flip-flops F / F, and the Q outputs of all the flip-flops are set to 1. Here, as the flip-flop F / F, for example, SN74S74N manufactured by American TI Co. can be used.

Although the present embodiment has been described by taking the decoding of the MH code as an example, the present embodiment can be applied to a decoding device for a code by another compression method. Also, the image signal after decoding can be used for various purposes such as displaying on a display such as a CRT or file as a bit image in addition to recording the image with a printer such as a laser beam printer. is there. Further, it goes without saying that the numerical values used in the present embodiment are not limited to those values, and may be appropriately selected depending on the application, environment and the like.

As described above, the decoding operation of the compressed code can be surely executed, and the decoding operation can be performed in real time even for the image processing that requires high speed processing. Further, it is possible to effectively decode and supply the compressed code to an output unit such as a printer that requires high-speed and high-quality image recording.

Further, it is possible to surely detect an abnormality related to the decoding operation or transmission of the compressed code, and to minimize the influence thereof.

Also, based on the image signal obtained by decoding the compressed code,
When the printing operation is performed, good synchronization can be obtained between the printer and the decoding processing unit.

Further, it is possible to surely detect the line synchronization code which is the reference of the decoding operation, and to eliminate the inconvenience such as the synchronization deviation of the decoding operation.

Further, even if the compressed code is supplied to the decoding circuit from the middle of one page or one line, the line synchronization in the decoding operation can be reliably performed, and erroneous decoding can be prevented.

As described above, according to the present invention, a plurality of compressed codes stored in the storage means are shifted to set a compressed code to be decoded next at a predetermined position of the storage means, and the compressed code is set at a predetermined position of the storage means. The run length data and the code length data of the compressed code is output by decoding the set compressed code, and if the decoded compressed code is not a specific compressed code whose run length is shorter than the code length, the code Decodes a specific compressed code that has a shorter run length than the code length, because it sequentially performs shifts according to long data and, in the case of a specific compression code, shifts according to code length data at once. Even if the compression code is executed, the compression code to be decoded next can be immediately set in a predetermined position of the storage means, and therefore, the compression code following the specific compression code can be set. The code can be quickly decoded, and further, when the decoded compressed code is a specific compressed code, a plurality of bits shifted from the predetermined position of the storage means corresponding to the maximum shift amount at one bit A plurality of detecting means for respectively detecting whether or not the EOL code exists at different positions, and the compressed code following the EOL code can be decoded based on the detection of the EOL code by the plurality of detecting means. In the structure for high-speed decoding of the compressed code including the compressed code, the EOL code which is the reference of the decoding operation can be surely detected.
The decoding operation of the compressed code based on the L code can be satisfactorily executed.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a schematic configuration of an embodiment of the present invention, FIG. 2 (a) is a diagram showing a memory type of an MH code in a memory circuit 101, and FIG. 2 (b) is a plurality of MH codes. Showing a continuous state of the circuit, FIG. 3 is a circuit block diagram showing the configuration of the bit shifter, FIG. 4 is a circuit block diagram showing the configuration of the MH code decoding circuit, and FIG. 5 is the circuit block shown in FIG. FIG. 6 is a detailed circuit diagram of the figure, FIG. 6 is a timing chart diagram showing operation timing of each part of the illustrated circuit, FIG. 7 is a circuit block diagram showing a configuration of a decoding error detection circuit, and FIG.
FIG. 9 is a diagram showing a configuration example of a printer, FIG. 9 is a block diagram showing a circuit configuration for recording operation of the printer shown in FIG.
FIG. 10 is a circuit block diagram showing the configuration of the EOL detection circuit,
FIG. 11 is a circuit diagram showing the configuration of the detection gate shown in FIG. 10, and FIG. 12 is a circuit diagram showing an example of the configuration of the register. 101 is a recording circuit, 102 is a multiplexer, 103 is a register, 104 is an MH code. Decoding logic 104 is an MH code table ROM.

Claims (1)

[Claims] 1. A compression code decoding device for sequentially decoding an indefinite length compression code including an EOL code indicating the end of each line of an image, and a storage means for storing a plurality of compression codes to be continuously input. Shift means for setting a compressed code to be decoded next at a predetermined position of the storage means by shifting a plurality of compressed codes stored in the storage means, and compression set at a predetermined position of the storage means Decoding means for outputting the run length data and the code length data of the compressed code by decoding the code, and when the compressed code decoded by the decoding means is not a specific compressed code whose run length is shorter than the code length. Causes the shift means to sequentially perform shifts according to the code length data, and in the case of the specific compressed code, the shift means A shift control means for executing a shift according to the code length data at a time, and a maximum shift amount executed by the shift means at a time when the compression code decoded by the decoding means is the specific compression code. Corresponding to the EO at a plurality of different positions shifted by 1 bit from the predetermined position of the storage means.
A plurality of detecting means for respectively detecting whether or not the L code exists, and a decoding control means for decoding the compressed code following the EOL code by the decoding means based on the detection of the EOL code by the plurality of detecting means. An apparatus for decoding a compressed code, comprising: