JPH0584698B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a decoding apparatus for compressed codes using band compression encoding used for facsimiles, image electronic films, and the like. In conventional image transmission devices such as facsimiles and recent image file devices using optical disks and magnetic disks, image data is compressed and handled to reduce the amount of data and speed up transmission or storage operations. We are trying to improve efficiency. Such image compression is a type of so-called code conversion operation, and in the case of Modified Hoffman (MH) encoding, which is a typical compression method, bit blocks of continuous white or black pixels in an image are converted to a different compression code. It is expressed in correspondence with . At this time, pixel bit blocks with a high occurrence frequency are associated with compressed codes with a short code length, while pixel bit blocks with a low occurrence frequency are associated with compressed codes with a long code length. This method utilizes the bias in the frequency of occurrence of combinations to express the entire image using a different code string with a smaller number of bits. Incidentally, the correspondence of compressed codes to pixel bit blocks is determined based on empirical rules, and the code lengths of the compressed codes are irregular. Therefore, when a plurality of compressed codes are input in succession, in order to decode the compressed codes, it is necessary to accurately separate and decode the individual compressed codes having uneven code lengths. In conventional facsimile devices, the transmission speed of the transmission line is not high, and
Since such a high-quality image was not required, there was no need to perform decoding processing at high speed. Therefore, in such facsimile apparatuses, the decoding process for the compressed codes that are input continuously is executed one after another by software processing using an inexpensive microcomputer or the like. In recent years, high-speed printers capable of forming high-quality images have been developed, such as laser beam printers using an electrophotographic process, and it is desirable to reproduce compressed images in real time using such printers. I'm getting used to it. However, the processing speed of such printers reaches over 10 megabits, which is beyond the reach of software processing by microcomputers, and without countermeasures such as providing page memory such as semiconductor memory. It is not possible to apply decoding processing using conventional software processing. Also, among the compressed codes by MH encoding mentioned above, there are some compressed codes whose run length is shorter than the code length, and when such compressed codes are decoded, the run length by the speed printer is The next compressed code to be decoded is not ready before the image reproduction corresponding to the image is completed, and in such a case, there is a possibility that the decoding operation of the compressed code is not in time for the image reproduction of the high-speed printer. The present invention has been made in view of the above points, and is capable of rapidly decoding an undefined length compressed code including a specific compressed code whose run length is shorter than the code length, and at the same time decoding it to a subsequent device. The purpose is to provide a compressed code decoding device that can supply image data without interruption, and more specifically, in a compressed code decoding device that sequentially decodes compressed codes of undefined length, a plurality of compressed codes input in succession are provided. a storage means for sequentially storing; a shifting means for shifting a plurality of compressed codes stored in the storage means to set a compressed code to be decoded next at a predetermined position in the storage means; and the storage means a decoding means for outputting run length data and code length data of the compressed code by decoding a compressed code set at a predetermined position of the compressed code; and a compressed code decoded by the decoding means has a run length longer than the code length. a determining means for determining whether or not the code is a short specific compressed code; and when the determining unit determines that the code is not the specific compressed code, the shifting unit sequentially executes a shift according to the code length data. Furthermore, the present invention provides a compressed code decoding device having a shift control means for causing the shift means to execute a shift according to the code length data at once when the compressed code is determined to be the specific compressed code. . A detailed description of the invention follows. First, an outline of an embodiment of the present invention will be explained using the circuit block diagram shown in FIG. In FIG. 1, numeral 101 is a storage circuit that stores information input from, for example, a reader that photoelectrically reads images, an electronic file that files images, or a receiver that receives image information via a transmission path such as a telephone line. A circuit that stores a so-called MH (Modified Hoffman) code obtained by compressing and encoding an image signal using a separate means in a form that can be read out sequentially in units of 16 bits (1 word), for example. This is a circuit that can be implemented using RAM (random access memory) or a latch circuit. Furthermore, the storage format of the MH code in the storage circuit 101 is as follows:
An example is shown in FIG. 2a. In other words, the inherent nature of MH codes is that their code lengths are uneven (minimum 2 bits to maximum 13 bits), but regardless of the code length, there is no blank bit, and the MH codes are serially connected as shown in Figure 2b. This is a format in which a bit string is converted and arranged in parallel every 16 bits. In Figure 2b, WB and BB indicate white and black pixels, respectively.
In the code, the numbers after WB and BB represent the run length of the code, for example:
WB8 is an MH code indicating white with a run length of 8. In this format, the MH code delimiter and the word (16 bit) delimiter do not necessarily match. Furthermore, the memory circuit 101 has a function of outputting subsequent words in parallel in sequence under external control. In FIG. 1, 102 is a so-called multiplexer (data selector). Further, 103 is a register having 28-bit parallel input and output,
A function to temporarily store the MH code applied from the storage circuit 101 to the input side of the register 103 via the multiplexer 102 and
The MH code stored in is described later as the output.
MH code decode logic 104 and MH
It has the role of providing a code decode table ROM (read only memory) 105 and the like. Multiplexer 102 and register 103 form a so-called bit shifter capable of serial shifting of data and n-bit jump shifting. This bit shifter is connected to the MH code decode logic 104 and the MH code decode logic 104, which will be described later.
It is controlled by the output of the decoding RM 105, etc., and functions to shift and store the MH code stored in the register 103 from the storage circuit 101 by the necessary number of bits, regardless of the boundary between the MH codes, using the method described above. . FIG. 3 (details will be described later) is a diagram showing the detailed configuration of this bit shifter, and is illustrated in the register 103.
The MH code string is an MH code WB1 indicating a white run length of 8 after the MH code exemplified in the storage circuit 101 shown in the first diagram passes through appropriate control.
(10011) is shown in a position where it can be decoded. That is, the output of the register 103 shown in FIG.
The state in which the first bit of the MH code is output to the CO, that is, the LSB output, is defined as a decodable position, and is hereinafter referred to as ``completion of cueing''. Therefore, the code arrangement in the register 103 in FIG. 3 is such that the MH code WB8, which indicates a white run length of 8, is "cue completion".
It shows that it is in the state of In FIG. 1, 104 is an MH code decoding logic (hereinafter referred to as logic 104), and the following four types of codes have run lengths shorter than the code length of the MH code, namely, the white run length. 1 (MH code 000111,
code length = 6 > run length = 1), white run length 2 (0111 in MH code, code length = 4 > run length = 2), white run length 3 (1000 in MH code, code length = 4 > run length = 3)
This is a circuit that decodes black run length 1 (010 in MH code, code length = 3> run length = 1). In the following explanation, the above four types of MH codes that indicate white run length 1, white run length 2, white run length 3, and black run length 1 will be collectively referred to as the HSC code. . In FIG. 1, 105 is an MH code decode RM (hereinafter referred to as RM 105), and the logic 104 described above is responsible for decoding.
This is a circuit that mainly decodes all MH codes, including the MH codes of various types. The logic 104 and the ROM 105 are responsible for decoding the MH codes, which are divided according to the processing speed and method of the MH codes.
Every time the MH code completes cueing,
It outputs the run length of the MH code, the code length, whether the image is black or white, whether it is a make-up code or a termination code, and whether it is present or not. 112 is an EOL detection circuit that detects whether or not a code for line synchronization, that is, an end-of-line (EOL) code exists in the MH code stored bit-serial in the register 103, and its storage position. do. In FIG. 1, reference numeral 108 is a run length counter, which is a binary counter capable of counting from a count number "0" to the maximum make-up code run length, that is, "2560" or more. Each time the run length counter 108 finishes counting the run length of the MH code output from the logic 104 or ROM 105, a count end signal (in this example, the counter ripple/carry CR) is sent.
Output. A flip-flop 109 inverts its output each time it receives a count end signal (ripple/carry CR) from the run-length counter 108 mentioned above. However, as will be described later, the output is controlled so as not to be inverted by the count end signal of the make-up code. The output of flip-flop 109 is an image signal obtained by decoding the MH code read from memory circuit 101. 107 is a code length counter, and the MH code is a binary counter that can count the maximum code length of "13" or more.Register 103
By performing a serial shift or jump shift on the MH code that was "cueing completed" in the code, it is swept out of the 103 register as a decoded code, and the subsequent MH code is shifted to the "cueing complete" position. When shifting, the amount of shift is counted and controlled. 106 is a 4-bit accumulator. As mentioned above, the memory circuit 10 is stored in the register 103.
When the MH code taken in from 1 is decoded, it is sequentially flushed out from the register 103, thereby creating an empty bit in the register 103. Therefore, the accumulator 106 counts the number of empty bits in the register 103, and every time there are 16 empty bits, a new MH code is transferred from the storage circuit 101 to 1.
Empty bits in register 103 are filled in words (16 bits) in parallel. This causes register 10
3 to logic 104 or RM105
Controls the MH code string so that it is not interrupted, enabling high-speed decoding. In addition, 110 is the blocks 101 to 10 shown in the first diagram.
9 is a diagram illustrating a control circuit that controls input/output signals between 9 and 9. Convert the MH code to an image signal as described above,
That is, the MH code is decoded. The decoded image signal is supplied to the printer 111, and the image is stored on the storage material. Note that the printer 111 outputs a horizontal synchronization signal, which is a synchronization signal for each scan.
HSYNC is output, and this HSYNC is used for timing of decoding operations. Next, embodiments of the present invention will be described in more detail.
This embodiment uses a so-called "high-speed printer" that is used to directly output an image signal that is the result of decoding an MH code, which is an image compression code, to a high-speed printer such as a laser beam printer without providing any image memory.・Real-time MH decoder”. Therefore, the problems of high processing speed of the MH decoder and synchronization of the image output of the MH decoder (in this example, image frequency = 10-odd _MHz ) with a high-speed printer such as a laser beam printer must be solved. It won't happen. Therefore, in order to solve these problems, based on the processing method described below,
Realize the desired “high-speed real-time MH decoder”. (1) Synchronization between the MH decoder and the printer is performed using the EL of the MH code and the horizontal synchronization signal, which is a synchronization signal for each line of the printer. (2) In the register 103 in FIG. 1, the MH code that has been decoded with "cueing complete" is swept out, and the subsequent MH code is shifted to the "cueing complete" position. Therefore, one of two methods is used: jump shift and serial shift. A specific configuration for achieving these two points will be explained using the drawings. FIG. 8 is a perspective view showing the structure of an embodiment of the laser beam printer shown as an example of the output section in FIG. 1. This printer uses an electrophotographic method using laser light, and 201 is a photosensitive drum rotatably supported within a housing Ha. 202 is a semiconductor laser that emits laser light La, and the emitted laser light La is transmitted to the beam expander 20.
3 and becomes a laser beam with a predetermined beam diameter. Further, the laser beam is incident on a polyhedral mirror 204 having a plurality of mirror surfaces. The polyhedral mirror 204 is rotated at a predetermined speed by a constant speed rotation motor 205. The laser light emitted from the beam expander 203 is scanned substantially horizontally by the polyhedral mirror 204. The photosensitive drum 201 is charged to a predetermined polarity by a charger 213 using an imaging lens 206 having f-θ characteristics.
An image is formed above as a spot light. A beam detector 207 detects the laser beam reflected by the reflecting mirror 208, and uses this detection signal to determine the timing of the modulation operation of the semiconductor laser 202 in order to provide desired optical information onto the photosensitive drum 201. A high-resolution electrostatic latent image is formed on the photosensitive drum 201 by the laser light that is imaged and scanned on the photosensitive drum 201 . After this latent image is developed by a developing device 209, it is transferred to a recording material stored in either cassette 210 or 211, and then the image is fixed on the recording material by passing through a fixing device 212. The hard copy is ejected to an ejecting unit (not shown). FIG. 9 shows an embodiment of a printer circuit for modulating the semiconductor laser shown in FIG. 8 with a predetermined image signal. The image signal VIDEO that has been decoded and input from the input terminal IN is transferred to a first line buffer 301 and a second line buffer 301, each consisting of a shift register or the like, having a number of bits equal to the number of pixels for at least one scan for each group of image signals for one scan. The signals are alternately input to the two-line buffer 302 under the control of the buffer switch control circuit 303. Further, the image signals inputted to the first line buffer 301 and the second line buffer 302 are read out alternately for each scan using the beam detection signal from the beam detector 304 as a trigger signal, and are applied to the laser driver 305. The laser driver 305 controls the semiconductor laser 3 based on the input image signal to control the emission of laser light.
06 is modulated and controlled. By having two line buffers, while inputting image signals that are input one after another to one of the line buffers, the laser driver 305 transfers the image signals already stored in the other line buffer.
It can respond to high-speed image signal input. The beam detection signal from the beam detector 304 is also transmitted to the decoding processing circuit as a horizontal synchronizing signal HSYNC, and is used for synchronizing the decoding processing and the printer operation, as will be described later. Incidentally, the image signal decoded in this printer is inputted through two line buffers, that is, a buffer having a double buffer configuration including a first line buffer 301 and a second line buffer 302. This double buffer configuration is used to perform a correction operation when an error occurs in the decoding operation. In other words, if an error occurs in the decoding operation while the image signal decoded by the decoding circuit is being stored in one line buffer, printing operation using the image signal of the current line containing the error is prohibited, and the image signal already stored in the other line buffer is Printing is performed based on the stored image signal of the previous line. As a result, printing is not performed using an image signal with a decoding error, so that the influence on the reproduced image can be eliminated. Note that this correction operation causes at least two lines of images with the same image signal to overlap, but in the high-resolution (for example, 16 pel/mm) recording operation used in this example, it does not affect the reproduced image much. isn't it. In FIG. 4, 105 is the MH code table ROM shown in FIG.
It consists of an O-only memory. The contents of R are schematically explained below.
AD0 to AD13 are R address terminals,
Further, O0 to O11 are output terminals of R. ROM
The format of the memory contents of 105 is register 1.
MH code to be decoded supplied from 03
Align the LSB bit with the address terminal ADO of R, and then set each bit of each MH code sequentially in the MSB direction from AD1 to AD1 of the address terminal of RM105.
Give by 1. Address terminal AD13 has MH
Signal B/-ROM (black = 1,
white = 0). Furthermore, the MH code is
If it is shorter than 12 bits, the missing bits are ignored (DON'T CARE). Also, the EL code is treated as a make-up code. Also, color bits (AD13) of make-up codes with a run length of 1972 or more are ignored (DON'T CARE). The contents of the MH codes given each address are written in the ROM 105 as storage data for the addresses determined above, and outputs corresponding to each MH code are output to the output terminals O0 to O11.
That is, output terminal 0 outputs a signal M/ which becomes "1" when the decoded MH code is a make-up code and "0" when it is a terminate code. The output terminal is a signal that outputs "0" when the decoded MH code is a white code (00110101) with a run length of 0 (or a black code (0000110111) with a run length of 0), and becomes "1" in other cases.
Output TO. Output terminals 2 to 5 are 4-bit outputs CL0 in which each MH code length (number of bits) is expressed as two's complement.
~Output CL3. However, the output terminal 5 is the LSB of the code length. Output terminals 6 to 11 are
Outputs 6-bit outputs RL0 to RL5 in a two's complement format representing the run length of the MH code. however,
Output terminal 11 is the LSB of the run length.
For the make-up code, only the upper 6 bits of the binary representation of the run length are assigned to the output terminal O11. This is because the make-up code in the MH code can express its run length using only the upper 6 bits. MH code indicating white with run length 8 at 402 in Figure 4
ROM10 when decoding WB8 (10011)
(The MH code table used in this example is CCITT YELLOW BK.
Fascicle． 2Rec.T.4TABLE1/T.4 and
According to TABLE2/T.4). In FIG. 4, numeral 104 is the MH code decoding logic shown in FIG. 1, which in this embodiment is a detection logic composed of an AND gate and an OR gate. The signal output from the logic 104 becomes "0" when detecting the HSC code, that is, the MH code indicating white with run lengths 1, 2, and 3, and the MH code indicating black with run length 1.
Outputs 1 and 2 are the code lengths of the four types of MH codes (HSC codes) described above expressed in binary numbers, inverted and output. FIG. 4 404 shows an example of the output when decoding the MH code white 1WB1 (000111) indicating white with a run length of 1. Note that a logic circuit was used to decode the HSC code because the current ROM addressing system cannot adequately handle the time required for high-speed processing. The operation of the bit shifter shown in FIG. 3 will be explained with reference to Tables 1 and 2. FIG. 3 102 is the multiplexer shown in FIG. 1, with two tri-state multiplexers 10
It consists of 21 and 1022. multiplexer 10
a control line from the accumulator 106 to 2;
When is "0", all outputs A7 to A27 from the multiplexer 1022 side to the register 103 become tri-state floating and become invalid, and outputs A0 to A27 from the multiplexer 1021 side become valid to the register 103. The outputs of the register 103 are C0 to C27.
At that time, the multiplexer 1021 inputs the input lines S0 to S.
2, the input signals C0 to C from the register 103
Performs 27 selection operations. Table 1 shows how the selection is made.
Shown below. For example, if S ₀ = S ₁ = 1 and S ₂ = 0, the outputs C ₃ to _{C 27} of the register 103 are taken in, and the outputs A ₀
Select and output as ~A ₂₄ . Next, when the control line to the multiplexer 102 is "1", the output A0 of the multiplexer 102
.about.A6 are selectively given from the multiplexer 1021 by the input lines S0 to S2 in the same way as when the control line is "0". Among the outputs A7 to A27 from the multiplexer 102, except those indicated by Y in Table 2, the multiplexer 1022 side is valid, and the outputs A7 to A27 from the multiplexer 1021 side, as shown in Table 2, are valid.
The values other than those indicated by Y are floating and invalid. Also from multiplexer 1022 to register 10
As shown in Table 2, the outputs A7 to A27 given to the multiplexer 1022 are input to the input lines Σ0 to Σ
However, the bit indicated by Y in Table 2 is selected from the multiplexer 1021 side. The number of Y is the input line output corresponding to the input lines Σ0 to Σ2 to the multiplexer 1022.
It is set by controlling the tri-state state of multiplexer 1021 using ST7 to ST11. Note that the multiplexer 10 in FIG.
The circuits 21 and 1022 are commercially available multiplexers (for example, IC manufactured by Fairchild, Inc., F215, etc.)
This can be easily realized using a gate circuit or the like. or,
The output selected by multiplexer 102 as output to register 103 from A0 to A27 is latched into register 103 by clock CK. By configuring the bit shifter as described above, it is possible to shift the 16-bit parallel MH code signal inputted from the memory circuit 101 by an arbitrary number of bits. As a result, MH codes with uneven code lengths can be brought into the above-mentioned "cue completion" state.

【table】

【table】

【table】

【table】

[Table] As mentioned above, the MH code is determined by monitoring the code string moving within the register 103, and the movement method is to move one bit at a time using bit shift 102 or the like. Treated as serial shift and HSC code
A jump shift of up to 6 bits occurs when an MH code is detected. That is, the code string in register 103 is controlled so that it can only move by 6 bits or less in one clock time. Therefore, when the EOL code (000000000001) moves within the register 103, its LSB bit will always appear in C0 to C5 of the register 103 even if the amount of movement is incorrect due to the previous code. Generally, when decoding an MH code, detection of an EL code is extremely important due to its code system. Below, EOL detection circuit 1 shown in Figure 1
12 will be explained in detail. In other words, the EOL code is a delimiter code for each line of the image, and at the same time has the role of indicating the position of the MH code that follows it. The boundaries of the MH code become unclear, making it impossible to decode one line of the image.
Furthermore, depending on the detection method used, the EOL of each subsequent image line cannot be detected, and as a result, the printed image is distorted to the extent that it is almost unusable. Therefore, even if the MH code in the MH code string is slightly incorrect due to transmission/reception errors, the EOL
It is important to develop an EOL detection method that minimizes code detection errors. If the EOL code is reliably detected, code errors can be recovered within one line of the image. FIG. 10 is a diagram showing a detailed configuration of the EOL detection circuit 112. As shown in FIG. 10, so that the LSB of the 12-bit EL code (000000000001) can be placed anywhere from C0 to C5 of the register 103, at least six types of registers corresponding to the shift amount that can be shifted at one time, that is, 6, are set. Detection gate 1001
are installed in parallel. This prevents failure to detect an EL code by monitoring the data stored in the register 103. Then, each 0 is output from the detection gate 1001 that detected the EOL code.
EOL code register 1, like EOL~5
A detection signal indicating the position within 03 is output. This method prevents errors in EL detection unless the EOL code itself contains error bits. Therefore, image code errors can always be recovered within one line. Furthermore, the probability that an error bit is included in an EOL code is extremely low compared to the probability that an error bit is included in an image code, considering the ratio of the number of bits, and can be ignored in practical terms. FIG. 11 shows details of the detection gate for detecting the EOL code. As shown in the figure, the configuration is such that 12-bit data is imported in parallel, and the MSB
The 11-bit data excluding the above is applied to the 12-input NAND gate 1002 along with the aforementioned MSB via the inverting gate INV. As a result, the EOL code is decoded, and when the EOL code is decoded, the output of the NAND gate 1002 becomes low level. Output 0EOL~ of the EOL detection circuit 112 in Fig. 10
5EOL is transmitted to the code length counter 107 and the accumulator 106. The accumulator 106 uses this signal to cause the register 103 to shift by the code length of the EOL code. That is, the EL detection circuit 112 shown in FIG. 10 may already detect EOL even though the MH code or FiLL bit still remains in the register 103 before the EOL code, considering its detection position. Therefore, when the EOL detection circuit 112 detects an EOL code detection signal other than signal 0, that is, an EOL code detection signal 1 to 5 among the EOL codes detected, the accumulator 106 detects the remaining code before the EL code in the register 103 from the above-mentioned EOL code. After being cleared by the shift operation, the register 103 is caused to further shift by the code length of the EL code, that is, 12 bits. As a result, the EOL code has been swept out, and the state of "cue completion" of the image MH code at the beginning of the next line to be decoded is reached. This also eliminates wasted time caused by decoding an EOL code that is not image information in the same way as other compressed codes. Next, a detailed explanation of the entire block diagram shown in FIG. 1 will be given using FIG. 5 and the like. The operation of the circuit shown in Figure 5 is complex, so in order to make the explanation easier, we will set some conditions and take the decoding operation of the MH code, which is considered to be more common, as an example. The basic operation will be explained, and then the establishment of the setting conditions will be explained. Let us use FIG. 2b as an example of the MH code string to be decoded. The operating principle of this circuit is that, before the printer's horizontal synchronization signal HSYNC arrives, the EL code that appears earlier in FIG. 2b is swept out of the register 103 shown in FIG. next to
The MH code WB8 indicating white run length 8, which is the MH code (that is, the MH code of the first image signal of the line to be decoded), is stored in the register 103 in the state of "starting complete" as described above, and is sent from the printer. Suppose you have HSYNC. FIG. 6 is a time chart of the main parts of the circuit shown in FIG. In FIG. 6, HSYNC 601 is a synchronization signal in the main scanning direction of the printer described above, and is generated for each main scanning line. This is used as the reference for the time chart, and this time is set as t ₀ . CK600
is the fundamental clock, whose frequency is the same as the image frequency. VEN 602 is a section signal that defines an effective image section within the main scanning line. Also iNi6
03 is a pulse 1 clock (1 bit) before the start of the section signal VEN, and EOS604 is the section signal VEN.
This is the final clock (bit) pulse of In addition, as mentioned above, the compression code (MH code)
When using a laser beam printer to perform a recording operation based on the image signal decoded, the horizontal synchronization signal
HSYNC is based on a beam detection signal that detects that the laser beam has reached a predetermined position on the scan line of the raster scan using the laser beam.
The section signal VEN is based on the section in which the laser beam scans the photoreceptor (drum) on which a latent image is formed. As is clear from these, the temporal relationships among the signals 600 to 604 in FIG. 6 should generally be fixed at constant values. And in this example
The length between HSYNC601 and iNi603 is a fixed length of 64 clocks. Also, the section of VEN 602 has the number of pixels of one line, and in this example, it is 4096 bits (pixels). In FIG. 6, at time _t0 , the circuit of FIG. 5 is set to the initial state for each main scan of image output. That is, as mentioned above, the MH code of the first image of each line (in this example, WB8 (10011) indicating white run length 8) is stored in the register 103 as "starting complete", and the output of the register 103, C ₀ ~
C ₁₂ (c10011.0010.0001 in this example) is Logic 10
4. It is given to ROM105 etc. Similarly, the value of the code length counter 107 is (-1)=(1111B). At this time (-
1) is defined to mean "completion of cueing." Also, each flip-flop 510, 109, 5
15 is in a reset state, and flip-flop 509 is in a set state. The flip-flop 509 being set (Q=1) indicates that the EOL code has been completely flushed out from the register 103 after the EOL of the MH code has been detected. Also, flip
When the flop 510 is set (Q=1), the run length latch 5 is set as described below.
13 indicates busy. Flip-flop 515 outputs the B/-ROM signal as output Q. This flip flop 5
The output of 15 should be decoded from now on when it is 1
B- indicates that the MH code color is black
It is a ROM signal. Similarly, when the output Q is 0, it indicates white. It is also assumed that the run-length counter 108 is stopped and its value is zero. SFTEN6
05 is a control line, and the fact that it is 1 indicates that the register 103 can shift data (MH code). For simplicity, it is assumed that the output signals Σ0 to Σ2 and the signal of the accumulator 106 are 0. That is, with this assumption, register 1
All 28 bits of 03 are valid MH code strings, indicating a state with no emptiness. The above is the state at time to. Now, at time t ₁ , the HSYNC signal shown in Figure 6
The fall of 601 causes flip-flop 5 shown in the figure.
09 is reset, as shown at 613 in FIG.
The EOLF signal becomes 1, and the SFTEN signal 605 becomes 1 via the AND gate 508. SFTEN signal
When 605 is 1, the counter 107 shown in FIG. 6 is enabled for counting. At the same time at time t ₁
Outputs C0 to C12 held by the register 103 are given to addresses in the ROM 105. (10011×××××××× in this example) and RM105
Of the outputs, code lengths CL0 to SL3 are provided to a code length counter 107 via gates 503 and 504. At the same time, since the signal 607 is 0, the counter 1
07 is in load mode and by the clock of _t1
The values CL ₀ to _{CL 3} are loaded into the counter 107 .
In this example, the MH code indicating white with run length 8
(-5), which is the two's complement of the code length 5 of WB8, is loaded. Also, the outputs RL0 to RL5 of RM105 and M/
T is provided as an input to runlength latch 513. At the same time, the Q output of the flip-flop 515 is also applied to the run length latch 513.
A ROM signal 620 608 controls the latch 513 to latch enable by setting it to 1, and latches the values D0 to D7 in the latch 513 at the clock of _t1 . At the same time, flip-flop 510 is set to 1 at time _t1 . Also flip flop 515
is reversed. A 1 on the BUSY signal 609, the Q output of flip-flop 510, indicates that latch 513 is latching a valid run length. Also, the fact that the B/-RM signal 620, which is the Q output of the flip-flop 515, is 1 indicates that the register 103 should indicate that "cueing is complete".
Indicates that the color indicated by the MH code is black. (or,
If the B/-RM signal 620 is 0, the color is white. ) SFTEN signal 605 is gate 505, gate 5
06, multiplexer 1 as the S signal.
02 to control the data in register 103 to be shifted by 1 bit. As a result, the transfer of the necessary data from the MH code in the register 103 to the subsequent stage has been completed, and the MH code is now used.The time chart in FIG. Bit shifting is performed until the carry-out signal CRO 606 is generated from the counter 107 as shown in FIG. That is, in this example, the value of the counter 107 set to -5 is (-1)
The 1-bit shift of register 103 continues repeatedly until the value of . When the value of the counter 107 becomes (-1), the cleaning of the currently used MH code (in this example, the MH code WB8 indicating white with run length 8) is completed, and the next MH code (run length 6) is cleared. show black
The MH code BB6) is "cueing complete" in the register 103, but the latch 513 is still
Since the run length of the previous MH code WB8 remains, the flip-flop 510 remains set. Therefore, when the CRO signal of the counter 107 becomes 1, the output of the gate 511 becomes 0, and when the SFTEN signal 605 becomes 0, the counter 107 stops. Similarly SFTEN
When the signal 605 becomes 0, all the S0 to S2 signals also become 0, the register 103 stops shifting, and the data is held. Therefore, "cueing complete"
The state of BB6 continues until time _t2 . At time _t2 , the iNi signal 603 causes the signal 610 to become 0, and the run length held in the latch 513 (white 8 bits in this example) is transferred to the counter 108 by the signal 610 via the multiplexer 514. Similarly, flip-flop 510 is reset by signal 610. This empties the latch 513 and eliminates the BUSY state. Therefore, the output of the gate 511 becomes 1, the SFTEN signal 605 becomes 1 in the same manner as described above, and the run length obtained by the MH code whose "cue finding is completed" in the register 103 is latched into the latch 513. . Thereafter, the MH codes are sequentially decoded in the same manner. Based on the run length (-5 in this example) loaded into the counter 108 at time _t2 , the counter 108 starts counting by the VEN signal 602 generated from the next bit at time _t2 . Then, when the value of the counter 108 becomes (-1) (in this example, the time
t ₃ ) Output CR1 signal 611. Further, the flip-flop 109 is set according to the color of the image specified by the B/signal 621 from the latch 513.
As a result, the first MH code can be converted into an image VIDEO (white 8-bit in this example). Furthermore, after the rise of the VEN signal 602,
iNi signal 603 until new HSYNC arrives.
It remains 0. Therefore, after the rise of the VEN signal 602, for example at time _t3 , the iNi signal 603 indicates the count up of the counter 108.
CR1 signal 611 causes flip-flop 510
is reset, the busy state is released, and the run length obtained by the subsequent decoding of the MH code can be taken into the latch 513. Now, in the explanation so far, the code length of the MH code is equal to or shorter than the run length length, and from the time when the MH code is "cueing completed", the used MH code to be flushed from the register 103 is If the code is serially shifted by setting the signals S0=1 and S1=S2=0 applied to the multiplexer 102, decoding of the MH code can be continued without interruption. However, on the other hand, if the run length of the MH code is shorter than the code length, if the serial shift is performed as described above, while the code is being flushed out from the register 103 (at 0 during the shift, in the counter 108,
Counting of the run length of the MH code is completed. At this point, it is necessary to take the next run length from latch 513 to counter 108 in order to eliminate image discontinuity. However, since the register 103 is not in the "cue completion" state for the next MH code, the run length that should be taken into the latch 513 has not been output from the ROM 105. Eventually, in this case, the image recorded by the printer will be interrupted, making it impossible to output the image in real time. This inconvenience is caused by the aforementioned HSC code, that is, run length 1,
MH code showing 2 and 3 white and run length 1
occurs when decoding the MH code. In such cases, the four types of HSC mentioned above
Only the MH code, which is a code, is used to operate the subsequent circuit equivalent to serially shifted code length data CL0 to CL3 from the ROM 105 using the MH code decode logic 104. That is, in order to load (-1) into the counter 107, the logic 104 uses a signal to load the counter 107 with (-1).
A load value (-1) is created and loaded into the counter 107 via the gate 504. Also, at this time
Outputs CL0 to CL3 from the ROM 105 are input to the gate 503 by signals. Further, the jump amount corresponding to the code length of the decoded MH code is outputted as outputs SF1 and SF2 from the logic 104 as 0 to 2, and the multiplexer 102 is operated via S0 to S2. This makes it possible to shift a plurality of bits in the time of one bit. In other words, it becomes possible to "complete the cue finding" in the register 103 of the next code to be decoded in the time of one bit. This jump amount is also input to the accumulator 106,
It is cumulatively added to the number of empty bits in register 103. With the above two shift methods, "cueing is completed"
A series of operations from ``run length latch'' to ``run length count'' are repeated at high speed to execute decoding without interrupting the image supplied to the printer section. 112 is the EOL detection circuit and register 1
When it detects that the EOL code appears on the outputs C0 to C11 of 03, it outputs the signal 0EOL. When the EOL code indicating the end of one line is detected by the EOL detection circuit 112, a signal from the EOL detection circuit 112 is sent via the timing alignment circuit 523.
By 0EOL, flip-flop 509 is set and signal 613 becomes 0. As a result, the SFTEN signal 605 becomes 0, and the next
Register 103 is stopped until HSYNC comes,
The MH code will wait for HSYNC in the state of "cueing completed". In this way, good synchronization between the printer and the decoding operation can be achieved. An image is formed by repeatedly scanning each line as described above. Next, a decoding error detection method will be described using FIG. The circuit shown in FIG. 7 is connected to the appropriate location in FIG. 1 or FIG. 5. In Figure 7, 80
1 is an inverter. Further, 802 is an adder, 803 is a latch, 804 is a comparator, and 803 is a latch.
05 is a latch, and 806 and 807 are flip-flops. FIG. 7 820 is the latch 513 in FIG.
This is the same signal as the signal 820 output from the multiplexer 514, and as described above, the run length as a result of decoding the MH code is expressed in two's complement. Now, adder 802 and latch 803 constitute an accumulator. The carry from the lower LSB of the adder 802 is set to 1 by the 829 signal (1), and as a result, the output 821 of the adder 802
is the two's complement of the run length 820. Therefore, the output 821 is a binary representation of the positive integer of the run length. Further, the addition to the latch 803 continues at the timing 610 in FIG. 6, that is, at the timing when the run length to be counted is loaded into the counter 108 shown in FIG.
Furthermore, the latch 803 is cleared for each main scanning line and for each HSYNC signal 601 in FIG. 6 that is output. That is, the output 822 of latch 803 represents the cumulative value of the run length for each line in binary form. On the other hand, the latch 805 has a constant run length for each line (4096, which corresponds to the number of pixels in one line in this example).
is notified from the CPU or the like by a signal 824 and held. Comparator 804 is now latch 803
This is a comparator circuit that compares the run length 822 (denoted as A) accumulated in the latch 805 with the correct value 823 (denoted as B) from the latch 805. The flip-flop 806 is the EOS shown in Figure 6.
When the signal 604 is output, that is, when the signal 831 indicating that A=B is not output from the comparator 804 at the final bit of each line.
Set by output 825 of AND gate 808. That is, the setting of flip-flop 806 indicates that the run length cumulative value A was not equal to the expected correct value B (4096 in this example), and that there was an error in the MH code or its decoding. shows. The flip-flop 807 is immediately set even during the run length accumulation by the output 826 of the AND gate 809 which receives the signal 832 output from the comparator 804 when the condition A>B is reached. That is, the Q output 828 of the flip-flop is such that the cumulative value of the run length is the expected correct value (4096 in this example, i.e., 4096 in this example).
This indicates that a large decoding error has already occurred during the decoding of one line. In addition, the flip-flops 806 and 807 have a value of 613 in FIG.
line) is detected by the EOL detection circuit 112.
It is not reset until HSYNC601 is input, and gate 8 is reset by HSYN signal 601 input.
It is reset by the output of 10. Therefore, the output 827 or 828 of each flip-flop 806, 807 is detected and a separate EOL detection circuit 11 is provided.
By focusing on EOL detection using 2, it is possible to minimize synchronization deviations due to decoding errors, etc. Although this example shows an example in which run lengths are cumulatively added by an accumulator, this may be replaced by a method in which run length values are sequentially subtracted from a predetermined number, for example, 4096, and borrows from the subtraction counter are detected. As described above, decoding errors occur, causing flips and
When flop 806 or 807 is set, its output is transmitted to buffer switch control circuit 303 of the printer circuit shown in FIG. The buffer switch control circuit 303 performs a buffer selection operation for alternately selecting the input and output of the line buffer of the printer having the double buffer configuration as described above. When the set signal, that is, the decoding error detection signal, is input from flip-flop 806 or 807, the image signal of the current line in which the decoding error has occurred is invalidated, and the previous line is used in place of the line in which the error has occurred. In order to reuse the image signal, line buffer selection control is performed so that the line buffer in which the image signal of the previous line is stored is read out again. That is, for example, if a decoding error occurs while storing an image signal being decoded in the first line buffer 301, the first line buffer 30
1, and after reading out the second line buffer 302 from which the image signal is currently being read out, the same image signal is read out again from the second line buffer 302. As a result, a printing operation is not performed based on the image signal of the line in which the decoding error has occurred, and the influence on the recorded image can be removed. Incidentally, the same operation can be performed even if the number of line buffers in the printer is two or more. Further, a line buffer for error correction may be provided on the decoding circuit side. Now, as mentioned above, in this example, when decoding an MH coded image, the first EL of the MH code is detected, and decoding is started from the code that follows as the first line of the image, Play the actual image. This is because the MH-encoded image is stored in, for example, an image memory, which is not shown in the present case, but is present in the previous stage of the storage circuit 101 shown in the first diagram. From there, the CPU or the like specifies the readout start address of the image memory, reads out the MH encoded image, and supplies it to the decoder circuit via the storage circuit 101. At this time, when the MH code read from the image memory is read from the middle of the image page, the EL code does not necessarily come at the beginning. In order to start decoding correctly even in this case, the first illustrated memory circuit 101 is cleared before starting decoding, and then the MH read from the memory is
Code storage circuit 101 is full (state shown in Figure 2)
The data is read until it becomes , and then the data (MH code) starts to be sent inside the decoder. Then, until the first EL code is detected, it is not treated as an image code, and data continues to be sent one after another until the EL code is detected.
Concentrate on detecting code. After the EL code is detected, the subsequent code is treated as image information and decoded while controlling the amount of shift using the code length or the like. In this way, by finding the first EL code by the EOL detection circuit 112 described above, it is possible to determine the delimitation of the MH code and to reproduce the image synchronously. Now, when the operation to find the first EOL code to be input after the start of the decoding operation described above is started, data is sequentially sent from the memory circuit 101 to the register 103.
If all "0"s exist in 03, the MH code or a part (in the middle) of the MH code actually coming from the storage circuit 101 will be continuation, and the EOL code (000000000001) will be erroneously detected. To avoid this, the initial state of the register 103 is all set to "1". That is, C0 of register 103
-C27 are all set to "1". This makes it possible to avoid the aforementioned false detection of EL. A method for presetting all registers 103 to "1" will be explained. FIG. 12 shows an example of the configuration of the register 103.
consists of 28 flip-flop F/Fs. Therefore, all the flip-flops F/
A preset pulse 901 is input from the CPU or the like to the preset terminal of F, and the Q outputs of all flip-flops are set to 1. Here, the flip-flop F/F is, for example, SN74S74N manufactured by TI in the United States.
etc. can be used. Although this embodiment has been described above using the decoding of MH codes as an example, it can also be applied to decoding apparatuses for codes using other compression methods. In addition, the decoded image signal can be used for a variety of purposes, such as being recorded on a printer such as a laser beam printer, or being displayed on a display such as a CRT, or as a file as a bit image. be. Furthermore,
It goes without saying that the multi-values used in this embodiment are not limited to these, and may be appropriately selected depending on the application, environment, etc. As explained above, the decoding operation of the compressed code can be reliably executed, and the decoding operation can also be performed in real time for image processing that requires high-speed processing. Furthermore, it becomes possible to effectively decode and supply compressed codes to output units such as printers that require high-speed, high-quality image recording. Further, it is possible to reliably detect abnormalities related to the decoding operation or transmission of compressed codes, and to minimize the effects thereof. Further, when performing a printing operation based on the image signal obtained by decoding the compressed code, the printer and the decoding processing section can be synchronized well. Furthermore, it is possible to reliably detect the line synchronization code that serves as a reference for decoding operations, thereby eliminating inconveniences such as out-of-synchronization of decoding operations. Further, even if the compressed code is supplied to the decoding circuit from the middle of one page or one line, line synchronization in the decoding operation can be ensured and decoding errors can be prevented. As explained above, according to the present invention, by shifting a plurality of compressed codes stored in the storage means, the compressed code to be decoded next is set at a predetermined position in the storage means, and the compressed code is set at a predetermined position in the storage means. By decoding the set compressed code, run length data and code length data of the compressed code are output, and whether or not the decoded compressed code is a specific compressed code whose run length is shorter than the code length. If the determining means determines that the compressed code is not a specific compressed code, a shift according to the code length data is executed sequentially, and if it is determined that the compressed code is a specific compressed code, the Since the shift according to the code length data is executed at once, even if a specific compressed code whose run length is shorter than the code length is decoded,
The next compressed code to be decoded can be immediately set in a predetermined position in the storage means, and the compressed codes following a specific compressed code can be quickly decoded. It is possible to decode compressed codes that can be supplied without interruption.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing a schematic configuration of an embodiment of the present invention, FIG. 2a is a diagram showing a storage type of MH codes in the memory circuit 101, and FIG. 2b is a diagram showing a continuous state of a plurality of MH codes. Figure 3 is a circuit block diagram showing the configuration of the bit shifter.
Fig. 4 is a circuit block diagram showing the configuration of the MH code decoding circuit, Fig. 5 is a detailed circuit diagram of the circuit block diagram shown in Fig. 1, and Fig. 6 is a timing chart showing the operation timing of each part of the circuit shown in Fig. 5. figure,
FIG. 7 is a circuit block diagram showing the configuration of a decoding error detection circuit, FIG. 8 is a diagram showing an example of the configuration of the printer, and FIG. 9 is a block diagram showing the circuit configuration for recording operation of the printer shown in FIG. Figure 10 is
11 is a circuit diagram showing the configuration of the detection gate shown in FIG. 10, FIG. 12 is a circuit diagram showing an example of the configuration of a register, 101 is a storage circuit, 102 is a multiplexer, 103 is a register, 104 is MH code decode logic, 104 is MH code decode logic,
It is a table ROM.

Claims (1)

[Scope of Claims] 1. A compressed code decoding device that sequentially decodes compressed codes of undefined length, comprising: storage means for successively storing a plurality of compressed codes input in succession; and a plurality of compressed codes stored in the storage means. a shift means for setting a compressed code to be decoded next in a predetermined position in the storage means by shifting the compressed code in the storage means; a decoding means for outputting code length data of a compressed code; a determining means for determining whether the compressed code decoded by the decoding means is a specific compressed code having a run length shorter than the code length; If the determining means determines that the code is not the specific compressed code, the shifting unit sequentially executes a shift according to the code length data, and if it is determined that the code is the specific compressed code, the shifting A compressed code decoding apparatus comprising: shift control means for causing a shift according to the code length data to be executed at once by the means.