JP3345531B2 - Encoding device and facsimile device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding apparatus for a facsimile apparatus suitable for transmitting a document in which a black-and-white binary image and a halftone image are mixed, and more particularly, to a conventional MH or MR system. The present invention relates to an encoding apparatus and a facsimile apparatus that enable efficient transfer using an existing circuit even for a document in which an improvement in the compression ratio of image data cannot be expected in encoding processing by the MMR method or the like.

[0002]

2. Description of the Related Art Conventionally, in a facsimile apparatus, encoding processing based on an MH method, an MR method, an MMR method, or the like has been performed. In these conventional encoding processes, it is not necessary to set a line break (line boundary) to a byte, word, or W word (hereinafter, referred to as a byte boundary). On the transmitting side, the read data is serially encoded, and on the receiving side, EOL (end of line)
Decoding is performed by synchronizing with a code (EOFB code for page unit in the case of MMR).

In this case, in order to simplify the subsequent processing, there has been proposed a binary image data compression apparatus capable of always setting the start of a line to a byte boundary (Japanese Patent Laid-Open No. Hei 6-30284). ). In this binary image data compression device, in the case of the conventional device, since the break of each line cannot be easily determined, a fill bit insertion process or the like cannot be easily executed, and the start of the line does not always start at a byte boundary. In order to solve the problem that a bit shift operation is necessary because there is no coding line (binary image data) when the compression mode is specified for each line of image data, "0" if the last bit of the last encoding line does not match a byte boundary
EOL indicating that this is the last data corresponding to the encoding line when a bit is inserted and the last byte is output
A signal (code) is output.

Accordingly, it is possible to efficiently execute processing such as fill bit insertion processing and editing at the code data level with respect to the code data output from the binary image data compression apparatus. By the way, the above-mentioned conventional technology is a black and white 2
This is a case where a document with a value is transmitted and received. For example, in the case of a halftone image that is complex and has many change points, the compression ratio is deteriorated, and in some cases, the code amount of the encoded data is reduced by Will be exceeded. In such a case, it is more efficient to accumulate raw data as it is than to compress and accumulate by the MH method or MR method.

[0005] For example, when such a halftone image and a black and white binary image are mixed in one document, code data (binary image) and raw data (halftone image) are used.
Will be mixed and accumulated. As for the parts having different data formats, such as the coded data and the raw data, it is more convenient to use byte boundaries in the later processing.
There is a need to align line boundaries with byte boundaries.

In the prior art, in order to realize a device in which a data format is different, specifically, a line boundary is a byte boundary, register and counter data are read out by software and a bit shift operation is performed. Therefore, the device becomes extremely slow.
The encoding apparatus disclosed in Japanese Patent Application Laid-Open No. 6-30284 is provided with a fraction bit generation instructing unit, which is a so-called black box. Is also not described.

[0007]

When a binary image and a halftone image are mixed, a boundary between a line to be coded and a line to leave raw data (a line not to be coded) is a byte boundary. It is desirable that the raw data be transferred on a byte-by-byte basis. In this case, if it is to be realized by the prior art, as described above,
This results in a very low speed device.

According to the present invention, when image data having different data formats, such as coded data and raw data, coexist, there is no need to provide a means such as a fractional bit generation unit or an EOL signal output unit. Provided are an encoding device and a facsimile device in which a boundary can be aligned with a byte boundary and high-speed processing is enabled by a simple circuit using an existing circuit (block) necessary for encoding processing as it is.

[0009]

According to the first aspect of the present invention, an encoding apparatus comprising a host interface unit, an overall system control unit, an image analysis unit, an encoding unit, and code data or a function code generation unit generates the data. A first multiplexer that selects data (code), a second multiplexer that selects data length (code length) to be generated,
And P / S shift register the data selected by the first multiplexer converts the parallel / serial, second
A first counter that counts the data length selected by the multiplexer , a P / S shift register, and a first counter .
And code the serial data generation unit by the counter to generate a serial data encoded, byte output of the code the serial data generation unit, word, and S / P shift register for serial / parallel conversion W word units, before
Second counting the shift amount of the serial S / P Shift Register
Comprising a counter, said second counter counter data decoder which decodes the output of administers control of their internal block, and block control unit for interfacing with an external block, the city, the counter data inputs the output of the decoder to the second multiplexer, enter the pad bits to the first multiplexer, and by the sequence to place a starting automatically adds an invalid pad bits effective fraction bits , Byte, word, W word boundaries,
It is configured to transfer to the host interface unit.

[0010] In the second aspect of the present invention, the encoding apparatus according to claim 1, inputs the EOL code data forming the EOFB code or RTC code to the first multiplexer, the EOL code length data to the second multiplexer type and by the sequence to place a autostart, EOL, EOFB, it is configured to generate a RTC code.

According to a third aspect of the present invention, in the encoding apparatus of the first or second aspect, the raw line code data for identification added to the head of the raw line that is not coded is stored in the first line.
As well as input to the multiplexer, the raw line code length data input to the second multiplexer, and, by applying a sequence and automatically start, and configured to generate raw line code data for identification.

According to a fourth aspect of the present invention, in the encoding apparatus according to any one of the first to third aspects, the EOL, EOF
B, RTC code and raw line code data for identification, pad bit generation processing means, fraction bit sweeping processing means, raw line flag and page end flag, depending on the state of normal encoding flow and raw line code generation flow And a means for branching to a page end processing flow. In the normal encoding flow, sequence control is performed so as to return to a standby state upon completion of encoding of one line,
In the raw line code generation flow, after generating a raw line code, a pad bit generation process is performed, a raw data transfer instruction is output, and sequence control is performed so as to return to a standby state.
In the page end processing flow, after performing the EOFB and RTC code generation processing, the fraction bit sweeping processing is performed,
The sequence is controlled so as to return to the page unit standby state.

According to a fifth aspect of the present invention, there is provided a facsimile apparatus including the encoding apparatus according to any one of the first to fourth aspects .

[0014]

According to the present invention, means for simply and quickly aligning a line boundary with a byte boundary by hardware is provided by using the existing circuit currently used for encoding as it is (claim 1). invention). Specifically, an existing code data generation unit necessary for encoding (5 in FIG. 1 described later)
First and second multiplexers (51, 52 in FIG. 2 also shown later) and a counter data decoder (FIG. 2 shown later)
(58), the function code generation unit is realized with a simple configuration.

In the prior art, EOL, EOFB, and RTC codes are generated through software. However, since the software is slow, the present invention is currently used for encoding. EOL, EOL,
Since the EOFB and RTC codes can be generated, the conventional means for generating the EOL, EOFB and RTC codes becomes unnecessary, and the circuit configuration is simplified accordingly (the invention of claim 2). In the prior art, the raw line code data for identification was added by software.
In the present invention, the existing raw line code data currently used for encoding is used as it is, and the raw line code data for identification can be generated easily and at high speed by hardware. Data generation means is not required, and the circuit configuration is simplified by that amount (the invention of claim 3).

In the prior art, software is interposed on a line-by-line basis to perform processing such as MMR encoding, next generation of a raw line code, next transmission of raw data, and generation of an EOFB code. However, according to the present invention, the sequence control is performed entirely by hardware in units of pages (state transition diagrams of FIGS. 5 and 6 described later) (the invention of claim 4). Further, in the present invention, as described above, the facsimile apparatus is provided with an encoding device that performs the encoding process entirely by hardware, so that the encoding process can be simplified and speeded up. Invention).

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of an encoding apparatus and a facsimile apparatus according to the present invention will be described in detail with reference to the drawings. This embodiment corresponds to claims 1 to 5.
The invention of claim 1 is a basic invention.

FIG. 1 shows an encoding apparatus according to the present invention.
FIG. 2 is a functional block diagram showing an embodiment of the main part configuration.
In the figure, 1 is a host interface unit, 2 is an overall system control unit, 3 is an image analysis unit, 4 is an encoding unit, 5 is a code data / function code generation unit, and 6 is a system bus.

The outline of the function of each section is as follows.
The host interface unit 1 has a function of exchanging data and exchanging DMA data with a host system (not shown). Overall system control unit 2
Is responsible for DMA requests and acknowledge control,
1 is a control unit of FIG. 1 having a function of controlling a system according to an encoding mode. The image analysis unit 3 has a function of detecting a two-dimensional mode and detecting black, white, color, and run length.

The encoding unit 4 has a function of performing an encoding search from the output of the image analysis unit 3 and generating low-order 8-bit code data and code length data. The encoding apparatus of FIG. 1 has a feature in a code data / function code generation unit 5, which generates continuous serial data from an output from the coding unit 4. It has a function to re-divide it into byte units and a function to generate various function codes (the invention of claim 1).

FIG. 2 is a functional block diagram showing one embodiment of the detailed configuration of the code data / function code generator 5 shown in FIG. In the figure, 51 is the first M
UX (multiplexer), 52 is a second MUX (multiplexer), 53 is an 8-bit P / S (parallel / serial) shift register, 54 is an 8-bit counter, 55 is a sign serial data generator, and 56 is an 8-bit S / S P (serial / parallel) shift register, 57 is a 4-bit counter, 58 is a counter data decoder, 59 is a control unit in a block, EN1 is an enable signal 1, EN2
Indicates an enable signal 2, and CLK indicates a clock signal.

The first MUX 51 is a multiplexer for selecting one of the code data, the EOL code data, the raw line code data, and the pad bit data from the encoding unit 4 of FIG. The second MUX 52 is a multiplexer that selects one of the code length data from the encoding unit 4, the EOL code length data, the raw line code length data, and the output of the counter data decoder.

The 8-bit P / S shift register 53 has L
SB1 first, EN1 (enable signal 1) is 0
When (inactive), the shift operation is stopped. 8
The bit counter 54 is a subtraction counter with data loading, and counts until the loaded data becomes zero.
Then, since EN2 (enable signal 2) becomes inactive, the operation is stopped. The code serial data generation unit 55 has a function of serially generating normal code data (details are shown in FIG. 4 described later).

The 8-bit S / P shift register 56 is a shift register that performs serial / parallel conversion of normally encoded code data, code data, pad bits and the like. The 4-bit counter 57 is an up counter that counts how many bits have been shifted to the 8-bit S / P shift register 56. In this embodiment, since the data is arranged in word units, the data has a 4-bit configuration. The counter data decoder 58 is a decoder that decodes the value of the 4-bit counter 57 and obtains a shift length until the data becomes word (byte) unit data.

The in-block control section 59 has functions for controlling data transfer with other blocks (request, acknowledge control) and line start control, and codes,
It has a function of controlling a sequence for generating various codes such as codes and pad bits. The above is the components and functions of the code data / function code generation unit 5 shown in FIG.

The lower 3 bits of the 4-bit counter 57
By decoding bits, the number of remaining shifts up to the byte boundary can be obtained. By decoding 4 bits, the number of remaining shifts up to the word boundary can be obtained. Next, a truth table in the counter data decoder 58 of FIG. 2 is shown.

FIG. 3 is an example of a truth table used in the counter data decoder 58 shown in FIG. A
-F shows 10-15.

When the counter value of the 4-bit counter 57 shown in the left column of FIG. 3 is 0H in the first row, as shown in the first row in the middle, the shift length data until it becomes the word unit data is obtained. Is also 0H, and the shift length data until the byte unit data shown in the right column is also 0H. When the counter value of the 4-bit counter 57 is 1H in the second row, as shown in the second row at the center, the shift length data until the word unit data becomes FH (15 bits), and is shown in the right column. The shift length data until the data becomes byte unit data is 7H
(7 bits). Thus, the 4-bit counter 5
If the lower 3 bits of 7 are decoded, shift length data up to byte unit data can be obtained. If the lower 4 bits are decoded, shift length data up to the word unit data can be obtained. Counter data decoder 58
Outputs shift length data using a truth table as shown in FIG.

FIG. 4 is a diagram for explaining a code generation process in the code serial data generation unit 55 shown in FIG.
(1) is for black run length 0, and (2) is for EOL code. In the figure, 55a indicates a decoder, and 55b indicates an AND gate circuit.

FIG. 4A shows a case where the black run length is zero. The code data of black run length 0 is 10
The first MUX 51 and the 8-bit P / S shift register 53 shown in FIG. 2 from the encoding unit 4 in FIG.
, The lower 8 bits in LSB first are shown in FIG.
(1) is supplied to the AND gate circuit 55b of the code serial data generation unit 55. Therefore, "0011011"
1 (because it is LSB first, it is shown in the opposite direction in the figure).

The code length data of this black run length 0 is AH (binary 1010), and is transmitted from the encoding unit 4 of FIG. 1 through the second MUX 52 and the 8-bit counter 54 shown in FIG. 4 (1) is supplied to the decoder 55a of the code serial data generator 55. From the decoder 55a, the counter value of the 8-bit counter 54 is 9
If it is higher than H, it is output as 0 and the AND gate circuit 5
The gate of 5b is closed, and EN1 (enable signal 1) to the 8-bit P / S shift register 53 also becomes 0 (inactive), and 0 is automatically inserted in the data.

More specifically, in this state, EN in FIG.
1 (enable signal 1) is 0 (inactive) and EN
Since 2 (enable signal 2) is 1 (active), 0 is inserted into the 8-bit S / P shift register 56. On the other hand, when the counter value of the 8-bit counter 54 becomes 8H or less, EN1 (enable signal 1) becomes 1, and the lower 8-bit code data is sequentially output from the 8-bit P / S shift register 53 from the LSB. You.

FIG. 4B shows the case of the EOL code. The EOL code data is 12-bit “0000000000001”, and is transmitted from the encoding unit 4 in FIG. 1 through the first MUX 51 and the 8-bit P / S shift register 53 shown in FIG.
The bit is supplied to the AND gate circuit 55b of the code serial data generation unit 55 in FIG. Therefore,
"00000001" (shown in the opposite direction in the figure)
Is entered.

The code length data of this EOL code is C
H (1100 of binary), and the encoding unit 4 in FIG.
4 through the second MUX 52 and the 8-bit counter 54 shown in FIG.
5 decoder 55a. This decoder 55a
Is output as 0 when the count value of the 8-bit counter 54 is 9H or more, the gate of the AND gate circuit 55b is closed, and the 8-bit P / S shift register 5
EN1 (enable signal 1) to 3 also becomes 0 (inactive), and 0 is automatically inserted in the data.

As described above, in the encoding apparatus of the present invention, various function codes (EOL code, raw line code), pad bit data, and the like are generated using the existing data generation circuit (claim). Inventions of claim 2 and claim 3). That is, the output from the counter data decoder 58 is given to the second MUX 52, and the pad bit data (usually a bit string of 0) is given to the first MUX 51,
If the circuit shown in FIG. 2 is started, the value of the 4-bit counter 57 automatically becomes 0 at the end of generation, and 8
Valid data that is less than a bit can also be output because it is converted into bytes. To be precise, it is a word boundary. The above operation is shown in a state transition diagram (the invention of claim 4).

FIG. 5 is a state transition diagram showing a main processing flow at the time of MMR encoding in the encoded data / function code generator 5 of the encoding apparatus of the present invention. In the figure, # 1 to # 11 indicate steps, and the signal symbols are PSTART, page start trigger, and LINS.
T is a line (processing) start trigger, PENDF is a page end processing flag, NMAF is a raw line code processing flag, EOLIN is a flag indicating the last data of the line, CGCMP is a code (code) generation end signal, B
SCD is the value of the 4-bit counter 57,! Is negative! = Indicates unequal.

The outline of the state transition diagram shown in FIG. 5, more specifically, the sequence control is as follows. Depending on the states of the raw line flag and the page end flag (step # 2), the flow branches to a normal encoding flow, a raw line code generation flow, and a page end processing flow (step # 2).
3, # 5, # 8). Normal encoding flow (Step # 3:
State 0) returns to the standby state when the encoding of one line is completed.

Raw line code generation flow (step #)
5, # 6: states 1 and 2), after generating a raw line code, perform pad bit generation processing, issue a raw data transfer instruction, and return to a standby state. Further, the page end processing flow (steps # 8 to # 10: states 3 to 5)
After performing the EOFB and RTC code generation processing, a fraction bit sweeping processing is performed, and finally, the processing returns to the page unit standby state. The above is the outline of the sequence control in the encoding apparatus of the present invention. The basic encoding flow will be described in detail with reference to FIG.

Step # 1 is a page start standby state until the page start trigger PSTART is present.
I'm waiting. When there is a command set from the host, a page start is triggered.

Step # 2 is an encoding standby state (initial state). First, a page start trigger PS
In response to the TART signal, a line (processing) start trigger LINST signal is generated. In this case, if the page end processing flag PENDF is not set (if it is not the page end: PENDF = 0) (steps # 3 and # 5), the operation flag is cleared after the processing is completed (step #) 4, # 7), and always return to this initial state (step # 2).

In step # 2, the judgment is made based on the clear signal of the operating flag, and the next line or the next process is restarted (generation of a line start trigger LINST signal). When the page end processing is completed (steps # 8 to # 11), the page is ended, so the step #
It returns to the page start standby state of No. 1.

When the first line is triggered by the page start and the trigger LINST signal is issued, if the encoding of the first line is MMR encoding, the raw line code processing flag NMAF is not set (NMAF = 0). Move to step # 3 (state 0). In step # 3, an MMR code generation process for one code is performed.

For example, the horizontal mode code "001" is encoded. When the code generation is completed, a code (code) generation processing end signal CGCMP rises (CGCMP =
1) Until the flag EOLIN indicating the last data of the line is set (EOLIN = 1: last data), step #
3 (state 0) is repeated. When the flag EOLIN indicating the last data of the line is set (EOLIN = 1: final data), the process proceeds to the next step # 4, the operating flag is cleared, and the process returns to the previous step # 2.

In step # 2, a restart is performed upon seeing the clear of the operating flag. In this case, if the next line is also an MMR coded line, the flow described so far (steps # 2 to # 4) is repeated. If step #
As a result of the judgment in step 2, the raw line code processing flag NAM
If F is standing (NAMAF = 1: raw line processing)
The process proceeds to a raw line code generation process in step # 5 (state 1).

In step # 5, identification code data to be added to the head of a raw line that is not coded is generated. The raw line code data is generated in the code data / function code generation unit 5 of FIG.
, The raw line code length data is the second MUX5
2, each is input and selected.

When the code generation is completed and the value of the 4-bit counter 57 is 0 (BSCD = 0), since the end of the raw line code data is at a word boundary, the process proceeds to step # 7, and the operation flag is set. After clearing, the process returns to the previous step # 2. If the value of the 4-bit counter 57 is not 0 (BSCD ≠ 0), the valid bits are not swept out, so the process proceeds to step # 6 (state 2) and proceeds to the pad bit generation process.

In the encoding device shown in FIG. 1, unless the data is in byte units, the data is not taken by the host interface unit 1 in FIG. 1 (the host does not take the data). In the case where the system configuration is word access, the host does not receive data unless it is in word units. Therefore, in step # 6, a pad bit is generated. Generated pad bit data (usually,
0) to the first MUX 51 in FIG. 2 and the output from the counter data decoder 58 to the second MUX 52
Enter and select each.

The activation of state 2 (transition to step # 6) is triggered by the end of state 1 (step # 5). When pad bit generation is completed, CGCMP
Since the (code generation processing end signal) rises, the process proceeds to step # 7, where the in-operation flag is cleared, and the previous step # 2
Return to

In this state, since the generation of the raw data code for identification has been completed, in step # 2, the raw data is transferred to the overall system control unit 2 in FIG.
Or word units). When the raw data transfer for one line is completed, a line start trigger LINST signal is output again to start the processing of the next line.

In this case, if the next line is the MMR encoding, step # 3 (state 0) is repeated, and if it is a raw line, step # 5 (state 1) is repeated.
Then, if the page end processing flag is set last (PENDF = 1), the process proceeds to the EOFB generation process (proceeding to step # 8). First, step # 8 (state 3)
Then, the process proceeds to the EOL code generation process 1, where the EOL code is similarly generated. When the generation of the EOL code is completed, the process proceeds to step # 9 (state 4).

In step # 9 (state 4), the EO
The processing shifts to L code generation processing 2 to generate an EOL code again. Since the EOFB code is a two-continuous pattern of the EOL code, the EOFB code is generated by the processing of step # 8 (state 3) and step # 9 (state 4).

The reason that the EOFB code is generated in this way is that the encoding device of the present invention uses the circuit used in the ordinary encoding as it is, so that step # 8 (state 3) and step # 9 (state 3) are performed. This is because the two states 4) are required. After the generation of the EOFB code ends, the branch destination differs depending on whether or not it is a word boundary.

First, at a word boundary, a request for data collection is output, so that all generated data is collected by the system. As a result, since the final data has been output, the process proceeds to step # 11, the in-operation flag is cleared, and the process returns to step # 1 to enter a page start standby state. That is, the processing for one page has been completed.

On the other hand, when it is not a word boundary (4
The value of the bit counter 57: BSCD ≠ 0) is determined in step # 10 because the valid data remains as fraction bits.
Proceed to (State 5). In step # 10 (state 5), fractional bit sweeping processing is performed to sweep out valid data. The process in step # 10 (state 5) is the same as the process of generating the pad bits in step # 6 (state 2) described above.

In the encoding apparatus of the present invention, the series of processes in steps # 1 to # 11 described above can be performed without software intervention.
Every page is realized by hardware only.

Although only the MMR encoding process is shown in the state transition diagram of FIG. 5, it is also possible to simultaneously execute the MH or MR encoding. This case is also basically the same as FIG. 5, and some steps may be added to FIG.

FIG. 6 is a block diagram showing the structure of the encoded data / function code generating section 5 of the encoding apparatus according to the present invention.
It is a state transition diagram which shows the flow of main processing at the time of encoding processing. In the figure, # 1 to # 11 are the same steps as in FIG. 5, # 21 and # 22 are the newly added steps, and the signal symbols are the same as in FIG.
F indicates an MMR mode flag, and RTCF indicates an RTC processing flag.

The state transition diagram shown in FIG. 6 is the same as the state transition diagram shown in FIG.
The only difference is that step # 21 is newly added between step # 4 and step # 22 is provided instead of step # 8. First, in the newly added step # 21 (state 6), EOL code generation processing 3 is performed. This EOL code generation processing 3 is executed when the system is not the MMR system (MMRF: MMR mode flag = 0), that is, when the system is the MH system or the MR system.

In the case of the MH system or the MR system, since it is necessary to insert an EOL code for each line, this step # 21 (state 6) is provided. Also in this case, the generation processing is the same as step # 8 (state 3) and step # 9 (state 4) in FIG. In this case, a tag bit (1 bit) in the MR mode can be added at the same time.

Next, in step # 22 (state 3) provided in place of step # 8, the EOL code generation processing 1 is performed as in step # 8 (state 3). However, the EO executed in step # 22 (state 3)
In the L code generation processing 1, when the RTC processing flag is set (repetition processing of EOL generation: RTCF = 1),
The point that this process is repeated is different from the previous step # 8 (state 3). Normally, the RTC code is EOL
Since the code is a six-consecutive pattern, during the RTC process, the EOL code generation process 1 in step # 22 (state 3) is repeated five times, and the process proceeds to the next step # 9 (state 4). The EOL code generation processing is performed six times to generate the RTC code.

In this case, a tag bit can be added. As described above, according to the state transition diagram shown in FIG. 6, whether the encoding method is the MMR method, or the MH method or the MR method can be executed simultaneously. The processing for the raw data is the same as that in FIG. As described in detail above, the encoding apparatus of the present invention realizes a series of processes shown in the state transition diagrams in FIGS. 5 and 6 on a page-by-page basis without software and all using only hardware. ing.

Therefore, the line boundary can be aligned with the byte boundary easily and at high speed by hardware by using the existing circuit currently used for encoding as it is. Further, by providing such an encoding device in a facsimile device, a facsimile device with a simple encoding process can be obtained (the invention of claim 5).

[0063]

According to the first aspect of the present invention, the means for inputting the output of the counter data decoder to the data length multiplexer and the pad bit (invalid bit only for padding: usually padding "0") with the data are used. A means for inputting to the multiplexer and a means for automatically starting the sequence in a manner similar to ordinary encoding are provided for this circuit, and invalid pad bits are automatically added to valid fraction bits so that byte, word , W word boundaries are transferred to the host interface unit. Therefore, the line boundary can be aligned with the byte boundary by hardware simply and at high speed using the circuit currently used for encoding as it is.

According to a second aspect of the present invention, there is provided an encoding apparatus for inputting EOL code data forming an EOFB code or an RTC code to a data multiplexer, inputting EOL code length data to a data length multiplexer,
As in the normal encoding, a means for automatically starting the circuit in a sequence is provided. Therefore, in the prior art, the EO
Existing circuits that generate L, EOFB, and RTC codes can be used as they are, and can be implemented simply and quickly with hardware.
EOL, EOFB, and RTC codes can be generated.

In the prior art, the raw line code data for identification is added by software.
Means for inputting raw line code data for identification to be added to the head of a raw line not subjected to encoding to a data multiplexer, means for inputting raw line code length data to a data length multiplexer, As in the normal encoding, a means for automatically starting the circuit in a sequence is provided. Therefore, the raw line code data for identification can be easily and quickly generated by hardware using the existing circuit that currently uses the raw line code data for identification.

In the prior art, software intervenes on a line-by-line basis, and the following processing is performed: MMR encoding, next, raw line code generation, next, raw data transfer, and next, EOFB code generation. 4 uses the existing circuit currently used for encoding as it is, and
L, EOFB, RTC code and raw line code data for identification, pad bit generation processing means, fraction bit sweeping processing means, raw line flag, and page end flag, depending on the state of normal encoding flow and raw line code The sequence control is performed by hardware including means for branching into a generation flow and a page end processing flow. Therefore, an apparatus can be obtained in which the existing circuits currently used for encoding are used as they are, and the sequence is controlled by hardware in units of pages.

In the facsimile apparatus according to the fifth aspect, the facsimile apparatus is constituted by the encoding apparatus according to the first to fourth aspects. Therefore, a facsimile apparatus with a simple encoding process can be obtained.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of a main part configuration of an encoding apparatus according to the present invention.

2 is a code data / function code generation unit 5 shown in FIG.
FIG. 2 is a functional block diagram showing an example of a detailed configuration of the embodiment.

FIG. 3 is an example of a truth table used in the counter data decoder 58 shown in FIG. 2;

FIG. 4 is a diagram for explaining a process of generating a code in a code serial data generation unit 55 shown in FIG. 2;

FIG. 5 is a state transition diagram showing a flow of main processing at the time of MMR encoding processing in the encoded data / function code generation unit 5 of the encoding device of the present invention.

FIG. 6 is a state transition diagram showing a flow of main processing at the time of MMR, MH, and MR encoding processing in the encoded data / function code generation unit 5 of the encoding device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Host interface unit 2 Overall system control unit 3 Image analysis unit 4 Encoding unit 5 Code data / function code generation unit 6 System bus 51 First MUX (multiplexer) 52 Second MUX (multiplexer) 53 8-bit P / S (Parallel / Serial) shift register 54 8-bit counter 55 Code serial data generation unit 55a Decoder 55b AND gate circuit 56 8-bit S / P (serial / parallel) shift register 57 4-bit counter 58 Counter data decoder 59 In-block control unit

Claims (5)

(57) [Claims] 1. A first multiplexer for selecting data (code) to be generated in an encoding device including a host interface unit, an overall system control unit, an image analysis unit, an encoding unit, and encoded data or a function code generation unit. A second multiplexer for selecting a data length (code length) to be generated, a P / S shift register for parallel / serial conversion of the data selected by the first multiplexer, and a data selected by the second multiplexer. A first counter for counting the length, a code serial data generation unit for generating serial data encoded by the P / S shift register and the first counter, and an output of the code serial data generation unit for outputting bytes, words, S / P for serial / parallel conversion in W word units
A shift register; a second counter for counting the amount of shift of the S / P shift register; a counter data decoder for decoding the output of the second counter; block control unit for interfacing with the block, with a capital inputs the output of the counter data decoder to the second multiplexer, enter the pad bits to the first multiplexer, or
One, by the sequence to place a starting automatically adds an invalid pad bits effective fraction bits, bytes, words, separated the W word boundaries, the encoding apparatus characterized by transferring to the host interface unit . In the coding apparatus of the claim 1, when the EOL code data forming the EOFB code or RTC code is input to the first multiplexer bets
Moni, the EOL code length data input to the second multiplexer, and by the sequence to place a autostart, EOL, EOFB, encoding device and generates a RTC code. 3. A coding apparatus according to claim 1 or claim 2, the raw line code data for identification to be added to the beginning of the raw lines not subjected to coding as well as input to the first multiplexer, the raw line An encoding apparatus, wherein code length data is input to the second multiplexer and raw line code data for identification is generated by automatically starting in sequence. 4. The encoding apparatus according to claim 1, wherein said EOL, EOFB, RTC code, raw line code data for identification, and pad bit generation processing means, and fraction bit sweeping processing means. Means for branching into a normal coding flow, a raw line code generation flow, and a page end processing flow according to the state of the raw line flag and the page end flag. In the raw line code generation flow, after generating a raw line code, a pad bit generation process is performed, a raw data transfer instruction is output, and the sequence control is performed to return to the standby state. However, in the page end processing flow, after performing EOFB and RTC code generation processing, a fractional bit sweep is performed. Perform the processing
An encoding apparatus that performs sequence control so as to return to a page unit standby state. 5. A facsimile apparatus comprising the coding apparatus according to claim 1.