JPS60251648A - Ｉｃパツケ−ジ - Google Patents

Ｉｃパツケ−ジ

Info

Publication number
JPS60251648A
JPS60251648A JP59107762A JP10776284A JPS60251648A JP S60251648 A JPS60251648 A JP S60251648A JP 59107762 A JP59107762 A JP 59107762A JP 10776284 A JP10776284 A JP 10776284A JP S60251648 A JPS60251648 A JP S60251648A
Authority
JP
Japan
Prior art keywords
package
chip
lead
earthing
applied film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59107762A
Other languages
English (en)
Inventor
Masahiko Takagi
高木　正彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59107762A priority Critical patent/JPS60251648A/ja
Publication of JPS60251648A publication Critical patent/JPS60251648A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＩＣチップを封入するＩＣパッケージに関する
ものである。
〔従来技術とその問題点〕
第３図（α）〜（的に各種ＩＣチップパッケージの例を
示す。図中１はＩＣチップ、２はパッケージである。Ｉ
Ｃチップ１は図示のようにパッケージ２中に封入されて
いる。また、パッケージ２にはプラスチックス、アルミ
ナ、セラミック、ガ）スなよりパッケージ２内にＩＣチ
ップ１を封じ込めるものと、（α）　、　（ｃ）　、　
（ｄ）のようにケース内に収容してシールするものとが
ある。
ところで、ＩＣチップはパッケージ２を通して外部から
入射する放射線あるいはパッケージ２より放射される放
射線の影響により、ダイブミックＲＡＭを構成するコン
デンサにたくわえられた電荷が放電し、調に記憶された
データが消失することがあり、ＩＣの回路に誤動作が生
ずるという問題点があった。
〔発明の目的〕
本発明の目的は放射線の影響によるＩＣの誤動作を防止
したＩＣパッケージを提供することにある。
〔発明の構成〕
本発明はＩＣチップに面するＩＣパッケージ本体の一部
に鉛の塗膜を設け、該鉛の塗膜をパンケージ本体に備え
た接地端子に接続したことを特徴とするＩＣパッケージ
である。
［実施例） 以下に、本発明の一実施例を図により説明する。
第１図、第２図において、ＩＣパッケージ本体２はＩＣ
チップ１を載置するパッケージ台Ｕと、ＩＣチップ１を
被覆するパンケージ蓋２ｂとからなり、ＩＣチップ１と
面するパッケージ蓋２ｂ、２ｂの内側に鉛３の塗膜３を
設け、一方パッケージ台あの一部に接地エリア４を形成
するとともに、該エリア４をパッケージ本体に備えた接
地端子５にワイヤ６で接続する。パッケージ台２αをパ
ッケージ蓋２ｂｆ施蓋するときに、鉛の塗膜３を接地エ
リア４に接触させて、接地端子５を接地することにより
該鉛の塗膜３を接地する。図中、７はＩＣチップ１の回
路端子１ｃＬに接続されたリードである。
〔発明の効果〕
本発明は以上説明したように、ＩＣパック−ジのＩＣチ
ップに面した部分に鉛の塗膜を設け、接地端子に該塗膜
を接続したので、該端子を通して塗膜を接地することに
より、鉛の塗膜でＩＣパッケージからＩＣチップに向け
て放射する放射線を有効に除去でき、またＩＣチップの
外部から電界が侵入するのを防止でき、放射線、外部電
界によるＩＣの誤動作を防止して安定な動作を確保でき
る効果を有するものである。
【図面の簡単な説明】
第１図は本発明の一実施例を示す図であり、パッケージ
の蓋を開いた状態の斜視図、第２図はパッケージの中央
断面図、第３図（α）〜（カは従来のパッケージを示す
断面図である。 １・・・ＩＣチップ　２・・ＩＣパッケージ本体３・・
・鉛の塗膜　５・接地端子 特許出願人　日本電気株式会社 代理人　弁理士　菅　野　中 筒１図 第２図 見３図 （α）（Ｃ） （ｂ）　（ｄ）

Claims (1)

    【特許請求の範囲】
  1. （１）　Ｉ　Ｃチップを封入するＩＣパッケージにおい
    て、ＩＣチップに面するＩＣパッケージ本体の一部に鉛
    の塗膜を設け、該鉛の塗膜をパッケージ本体に備えた接
    地端子に接続したことを特徴とするＩＣパッケージ。
JP59107762A 1984-05-28 1984-05-28 Ｉｃパツケ−ジ Pending JPS60251648A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59107762A JPS60251648A (ja) 1984-05-28 1984-05-28 Ｉｃパツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59107762A JPS60251648A (ja) 1984-05-28 1984-05-28 Ｉｃパツケ−ジ

Publications (1)

Publication Number Publication Date
JPS60251648A true JPS60251648A (ja) 1985-12-12

Family

ID=14467347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59107762A Pending JPS60251648A (ja) 1984-05-28 1984-05-28 Ｉｃパツケ−ジ

Country Status (1)

Country Link
JP (1) JPS60251648A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150180A (en) * 1990-06-15 1992-09-22 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device with high energy radiation absorbent glass

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150180A (en) * 1990-06-15 1992-09-22 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device with high energy radiation absorbent glass

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