JPS60229359A - High-frequency semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the lowering of the withstanding voltage of a high-frequency semiconductor device by forming a diode for protecting a gate oxide film in the chip of an MOS capacitor for matching input impedance. CONSTITUTION:Diodes D4, D5 for protecting a gate oxide film in an MOS field- effect transistor are shaped in the chip of an MOS capacitor for matching input impedance. The MOS capacito for matching input impedance is constituted by an N type substrate 13 for the capacitor, an insulating film 14 and an Al electrode 15. The diodes D4, D5 for protecting the gate oxide film are formed by the N type substrate 13 for the capacitor, a P type diffusion layer 16 and an N type diffusion layer 17.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a high frequency semiconductor device in which a MOS field effect transistor, an incoming impedance matching MOS capacitor, and a gate oxide film protection diode are sealed in the same package. Regarding.

Conventional configuration and its problems When operating a MOS field effect transistor at high frequencies, a MOS capacitor chip is placed inside the package to prevent a drop in impedance at the ends of the package and to ensure matching with external circuits. A matching circuit is generally formed by this MOS capacitor and the inductance of a wire to the input part of the MOS field effect transistor.

In addition, the gate oxide film of a MOS field effect transistor is usually very thin at 260 to 100A, and its dielectric strength is 2
The voltage is about 0 to 70V, and the gate oxide film is easily destroyed by surge voltage. Therefore, it is common practice to completely insert a gate oxide film protection diode which breaks down below the dielectric strength voltage of the oxide film between the gate and the source. Such gate oxide film protection diodes are usually M
It is integrated and formed in the same chip as the OS field effect transistor.

FIG. 1 VL is an equivalent circuit of a conventional high frequency semiconductor device. In FIG. 1, G and D are the gate and drain terminals at the ends of the C-cage, respectively. Inside the Hanokage is the step T1 of the MOS Cano ζ jitter. The chip T2 of the MOS field effect transistor, the gate G' of the MOS field effect transistor, and the MOS capacitor, (i
The gate G' of the H1 MO3 field effect transistor is connected within the chip T2 of the MOS field effect transistor.
and the gate oxide film protection diode D1. D2 is integrated. This gate oxide film protection diode D1. A bidirectional diode is formed by D2, and the gate oxide film is protected from both positive and negative surge voltages. A breakdown voltage of approximately ±10V is sufficient for this bidirectional diode.

However, in the conventional example shown in FIG. 1, the gate oxide film protection diode D1. With the formation of D2,
A diode D3 is formed in the chip substrate of the MOS field effect transistor, and as a result, a bidirectional diode consisting of a gate oxide film protection diode D1 and a diode D3 is inserted between the gate G' and the gate D' of the MOS field effect transistor. . Similarly, a bidirectional diode consisting of a gate oxide film protection diode D2 and a diode D3 is inserted between the source S' and 124701 of the MOS field effect transistor. Source S' and 12
As a result, the two bidirectional diodes inserted between 4701 and 4701 lower the withstand voltage between the gate G' and 4701 of the MOS field effect transistor and between the source S' and 124701, and the breakdown voltage between the MOS field effect transistor The original characteristics of metalwork are broken. That is, in high-frequency MOS field effect transistors that normally require high output, a voltage of 40V to 60V is often required as a drain bias, and when AC amplitude is taken into account, a withstand voltage of about soV to 10oV is required. Sign. Ken) -(, Dl and D3 and D2 and D3
A bidirectional diode consisting of soV~1oo■
A breakdown voltage of L is required, but if a protection diode is formed on the same chip as the tip of the MOS field effect transistor, it is very difficult to ensure the full breakdown voltage. This point will be explained in more detail below.

FIG. 2 is a cross-sectional structural diagram of the chip T2 of the conventional MOS field effect transistor shown in FIG. In FIG. 2, components equivalent to those in FIG. 1 are designated with the same reference numbers and symbols.

In FIG. 2, the MOS field effect transistor is a vertical double-diffusion device, with an N-type substrate 1. P-type channel diffusion region2. N-type source region 3. Gate oxide film4. Gate electrode6. Insulating film 6. It is composed of a source electrode 7. Although not shown in FIG. 2, the P-type channel diffusion region 2 and the N-type source region 3 are normally closed to ensure breakdown voltage.

On the other hand, the gate oxide film protection diode D1. D2 is formed on the same N-type substrate 1, and includes a P-type well 8, an N-type region 9,
Consisting of 10, Gui A-1 city pole 1j, 12.

In the conventional example shown in FIG. 2, since the P-type tube 8 is electrically floating, the N-type region 9.
The emitter-collector breakdown voltage (BVc) of an equivalent transistor with the type well 8 as the base and the N-type substrate as the collector
EO) is affected by hFE of the transistor, and the base
Tolerance between collectors BvcBo; 10ov, hFE=
BvcE at 10.

The breakdown voltage between the source S' and drain DM and gate G' and 124701 as a chip of the MOS field effect transistor, which is ≠32V, is limited to this value. N-type region 9.10 ((emitter, P-type well 8
In order to increase the hFE of an equivalent transistor with 1 as a base and an N-type substrate 1 as a collector, it is possible to reduce the concentration of the P-type well 8 serving as the base or to increase the diffusion depth. Not only does the process of forming a MOS field effect transistor chip become complicated, but it is also extremely difficult to set hFE to 1. Also, soV~
Applying a high voltage of 1oov to all diodes at all times increases the probability of failure occurring on the diode side, which poses a problem in terms of reliability. Furthermore, since the gate electrode 6 of the MOS field effect transistor and the diode electrode 12 must be connected on the chip of the MO3i field effect transistor, the wiring used for the connection and the diode itself have a large gate-to-train capacitance (Cqd). increase. An increase in gate-drain capacitance (Cqd) means an increase in feedback capacitance, which also causes a decrease in the gain of the MOS field effect transistor.

OBJECTS OF THE INVENTION An object of the present invention is to integrate a MOS field effect transistor and a MOS capacitor/capacitor for input impedance matching in the same panocage.
In a configuration in which two types of chips are sealed, 1v1
An object of the present invention is to provide an excellent high-frequency semiconductor device having a diode for protecting the gate oxide film of an OS field effect transistor, and having no drop in breakdown voltage.

Structure of the Invention The present invention has a structure in which two types of chips, a MOS field effect transistor and an input impedance matching MOS capacitor, are sealed in the same panocage, and a gate oxide film protection diode is sealed within the chip of the input impedance matching MOS capacitor. It is characterized by the formation of

DESCRIPTION OF THE EMBODIMENTS FIG. 3 is an equivalent circuit showing an embodiment of the high frequency semiconductor device of the present invention. In FIG. 3, components equivalent to those in FIGS. 1 and 2 are given the same reference numerals and symbols.

As shown in FIG. 3, in the present invention, the gate oxide film protection diode D4. D6 is MO for input impedance matching
It is formed in the chip T3 of the S capanocouple, but not in the chip T4 of the MOS field effect transistor. Gate oxide film protection diode D4. In D5, the wire l that acts as an inductance is connected to the connection point σ'
When it is turned on/off, it is connected to the gate and source of the MOS field effect transistor and serves to protect the gate oxide film of the MOS field effect transistor. Since the voltage applied between the gate terminal G and source S' of the package is around ±10V at the maximum in normal operation, the gate oxide film protection diode D4. The bidirectional diode made of D5 does not require a withstand voltage of 80v to 100v. That is, according to the present invention, the gate oxide film protection diode D4.
D5'i is formed within the chip T3 of the input impedance matching MOS capacitor/tar, so a parasitic transistor is not formed between it and the drain to which a high voltage is applied.

Further, according to the present invention, only the chip T4 of the MOS field effect transistor is subjected to high voltage, so the probability of failure due to the diode is lower than in the conventional example, and reliability problems are also reduced.

Furthermore, according to the present invention, no protection diode is formed in the chip T4 of the MOS field effect transistor, and the MOS field effect transistor is
Since there is no need for wiring on the chip T4 of the S field effect transistor, there is no increase in the gate-drain capacitance (Cqd).

Moreover, inside the chip T4 of the MOS field effect transistor,
Since there is only a MOS field effect transistor, there is a lot of freedom in terms of role, such as placement, without considering the relationship with the gate oxide film protection diode.

FIG. 4 is a cross-sectional structural diagram of the chip T3 of the input impedance matching MOS capacitor/capacitor according to the embodiment of the present invention shown in FIG. In FIG. 4, components equivalent to those in FIG. 3 are designated with the same reference numbers and symbols.

As shown in FIG. 4, in the present invention, a diode for protecting the gate oxide film of a MOS field effect transistor is formed within the chip of a MOS capacitor for input impedance matching. The input impedance matching MOS capacitor/capacitor includes an N-type substrate 13 for capacitor, an insulating film 14, and an AI
The gate oxide film protection diodes D4 to D6 are composed of an N-type capacitor substrate 13 and a P-type diffusion layer 16. It is formed by the N type diffusion layer 17.

As an embodiment of the high frequency semiconductor device of the present invention,
As explained in (-), we took as an example a configuration in which a bidirectional diode consisting of a MOS capacitor/capacitor for beadance matching and two gate oxide films and a gate oxide film are formed on the same chip.
A configuration may also be adopted in which the number of gate oxide film protection diodes is one and the gate oxide film is protected against unidirectional polarity of the surge voltage. Father, N as MO3 field effect transistor
The explanation has been given using a transistor with a vertical double-diffusion channel as an example, but it goes without saying that the same effect can be achieved with a P-channel or with other structures, such as an MO3 field effect transistor with a V-groove gate structure. .

Effect of the invention The present invention brings about the following effects.

(1) Gate protection using a gate oxide film protection diode
There is no drop in breakdown voltage between drains and between source and drain.

(2) High voltage is not applied to the gate oxide film protection diode, improving reliability.

(3) There is no increase in gate-drain capacitance (Cqd) associated with a diode for protecting the gate oxide film, and there is no decrease in the gain of the MO3 field effect transistor.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of a conventional high-frequency semiconductor device, FIG. 2 is a chip cross-sectional structure diagram of an MO8 field effect transistor used in the conventional high-frequency semiconductor device, and FIG. 3 is an example of the high-frequency semiconductor device of the present invention. An equivalent circuit diagram of the embodiment, FIG. 4 is a chip cross-sectional structure diagram of an input innovation matching MOS capacitor used in an embodiment of the high frequency semiconductor device of the present invention. G: Gate terminal, D: Drain terminal, T
3... Input impedance matching piece MOS capacitor/tar chip, C... MOS capacitor/tar, T4...M
O3 field effect transistor chip, D4. D6...
・Diode for gate oxide film protection. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Figure 4 Figure h

Claims (1)

[Claims] (1) Two types of chips in the same package: a MOS field effect transistor and an input impedance matching MOS capacitor connected to the gate and north of the field effect transistor through a wire and a metal electrode of the package. is sealed, and a diode for protecting the gate oxide film of the MOS field effect transistor, which is connected to the gate and source of the MOS field effect transistor via a wire and a metal electrode of the package, is connected to the gate and source of the MOS field effect transistor for matching the input impedance/s. A high frequency semiconductor device characterized in that it is formed within a chip of a MOS capacitor. ? 2. The high frequency semiconductor device according to claim 1, wherein the gate oxide film protection diode is a bidirectional diode.