JPH0241909B2 - - Google Patents

Description

[Detailed description of the invention]

Industrial Application Field The present invention provides a method for combining a MOS field effect transistor and an input impedance matching transistor in the same package.
This invention relates to a high frequency semiconductor device in which a MOS capacitor and a gate oxide film protection diode are sealed. Conventional configurations and their problems When operating a MOS field effect transistor at high frequencies, a MOS capacitor chip must be placed inside the package to prevent a drop in impedance at the ends of the package and to ensure matching with external circuits. ,
Generally, a matching circuit is formed by this MOS capacitor and the inductance of a wire to the input part of the MOS field effect transistor. Furthermore, the gate oxide film of a MOS field effect transistor is usually very thin, 250 Å to 1000 Å, and its dielectric strength is only about 20 to 70 V, so the gate oxide film is easily destroyed by surge voltage. Therefore, it is common practice to insert a gate oxide film protection diode that breaks down below the dielectric strength voltage of the oxide film between the gate and the source. Such a gate oxide film protection diode is usually formed integrated in the same chip as a MOS field effect transistor. FIG. 1 shows an equivalent circuit of a conventional high frequency semiconductor device. In FIG. 1, G and D are the gate and drain terminals at the ends of the package, respectively. Inside the package, there is a MOS capacitor chip T ₁ , a MOS field effect transistor chip T ₂ , and a MOS field effect transistor gate G′.
It is composed of a wire l that connects the MOS capacitor C _I and acts as an inductance. M.O.S.
Inside the field effect transistor chip _T2 is a MOS
A diode D ₁ for protecting the gate oxide film is connected between the gate G′ and the source S′ of the field effect transistor.
D ₂ is integrated. These gate oxide film protection diodes D ₁ and D ₂ form a bidirectional diode, and the gate oxide film is protected from both positive and negative surge voltages. A breakdown voltage of about ±10V is sufficient for this bidirectional diode. However, in the conventional example shown in FIG. 1, by forming the gate oxide film protection diodes D ₁ and D ₂ , a diode D ₃ is formed in the chip substrate of the MOS field effect transistor, and as a result, the MOS field A diode D ₁ for protecting the gate oxide film is placed between the gate G′ and drain D′ of the effect transistor.
A bidirectional diode consisting of and diode _D3 is inserted. Similarly, a bidirectional diode consisting of a gate oxide film protection diode _D2 and a diode _D3 is inserted between the source S' and drain D' of the MOS field effect transistor. The two bidirectional diodes inserted between the gate G' and drain D' and between the source S' and drain D' of this MOS field effect transistor result in the gate G' and drain D' of the MOS field effect transistor. This lowers the withstand voltage between source S' and drain D', and deteriorates the original characteristics of the MOS field effect transistor. That is, in high-frequency MOS field effect transistors that normally require high output, a voltage of 40V to 50V is often used as a drain bias, and a withstand voltage of approximately 80V to 100V is required when AC amplitude is taken into account. Therefore, bidirectional diodes consisting of D ₁ and D ₃ and D ₂ and D ₃ are required to have a withstand voltage of 80V to 100V or more, but if a protection diode is formed on the same chip as the MOS field effect transistor chip, , it is extremely difficult to ensure voltage resistance. This point will be explained in more detail below. FIG. 2 is a cross-sectional structural diagram of the chip _T2 of the conventional MOS field effect transistor shown in FIG. In FIG. 2, components equivalent to those in FIG. 1 are designated with the same reference numbers and symbols. In FIG. 2, the MOS field effect transistor is a vertical double diffusion element, with an N-type substrate 1, a P
It is composed of a type channel diffusion region 2, an N type source region 3, a gate oxide film 4, a gate electrode 5, an insulating film 6, and a source electrode. Although not shown in FIG. 2, the P-type channel diffusion region 2 and the N-type source region 3 are usually shorted to ensure breakdown voltage. On the other hand, the gate oxide film protection diodes D ₁ , D ₂
are formed on the same N-type substrate 1 and consist of a P-type well 8, N-type regions 9 and 10, and diode electrodes 11 and 12. In the conventional example shown in FIG. 2, since the P-type well 8 is electrically floating, the N-type regions 9 and 10
The emitter-collector breakdown voltage (BV _CEO ) of an equivalent transistor with the emitter, P-type well 8 as the base, and N-type substrate as the collector is affected by the transistor's _hFE , and the base-collector breakdown voltage (BV _CBO ) of

It decreases significantly to [formula]. For example, when BV _CEO = 100V and h _FE = 10, BV _CEO becomes ≒32V, and the voltage between the source S' and drain D' and the gate of the MOS field effect transistor chip becomes
The breakdown voltage between G' and drain D' is limited to this value. In order to lower the h _FE of an equivalent transistor in which the N-type regions 9 and 10 are emitters, the P-type well 8 is a base, and the N-type substrate is a collector, the concentration of the P-type well 8 that serves as the base is increased, and the diffusion depth is increased. A method of increasing the depth of h FE is considered, but this not only complicates the process of forming the MOS field effect transistor chip, but also makes it extremely difficult to make h _FE 1. Also, constantly applying a high voltage of 80V to 100V to the diode increases the probability of failure on the diode side.
This is a reliability problem. Furthermore, the gate electrode 5 of the MOS field effect transistor and the diode electrode 12 must be connected on the chip of the MOS field effect transistor, and the wiring used for this connection and the diode itself have a gate-drain capacitance (Cgd). increase. An increase in gate-drain capacitance (Cgd) means an increase in feedback capacitance, which also causes a decrease in the gain of the MOS field effect transistor. Purpose of the Invention The purpose of the present invention is to provide a MOS field effect transistor and an input impedance matching device in the same package.
An object of the present invention is to provide an excellent high-frequency semiconductor device having a structure in which two types of MOS capacitor chips are sealed, which has a diode for protecting the gate oxide film of a MOS field effect transistor, and which does not have a drop in breakdown voltage. Structure of the Invention The present invention provides a first chip in which a MOS field effect transistor is formed and a MOS capacitor for input impedance matching are formed in the same package, and a second chip separate from the first chip is sealed. , the gate electrode of the transistor and the MOS capacitor are connected to each other via a bonding wire, and a diode for protecting the gate oxide film of the transistor is formed in the second chip. DESCRIPTION OF EMBODIMENTS FIG. 3 is an equivalent circuit showing an embodiment of the high frequency semiconductor device of the present invention. In FIG. 3, components that are equivalent to those in FIGS. 1 and 2 are given the same reference numerals and signals. As shown in FIG. 3, in the present invention, gate oxide film protection diodes D ₄ and D ₅ are formed in the chip T ₃ of the MOS capacitor for input impedance matching, and are formed in the chip T ₄ of the MOS field effect transistor. Not done. The gate oxide film protection diodes D ₄ and D ₅ are connected to the gate and source of the MOS field effect transistor at the time when the wire l acting as an inductance is wire bonded to the connection point G'', and the gate oxide film protection diodes D 4 and D 5 are connected to the gate and source of the MOS field effect transistor. The voltage applied between the gate terminal G and the source S' of the package is around ±10V at maximum in normal operation, so both gate oxide film protection diodes D ₄ and D ₅ are used to protect the gate oxide film. The forward diode does not require a withstand voltage of 80 V to 100 V. That is, according to the present invention, since the gate oxide film protection diodes D ₄ and D ₅ are formed within the chip T ₃ of the MOS capacitor for input impedance matching. This is because a parasitic transistor is not formed between the drain and the drain to which a high voltage is applied.Furthermore, according to the present invention, the MOS
Since only the _T4 field effect transistor chip is used, the probability of failure due to the diode is lower than in the conventional example, and there are fewer reliability problems. Furthermore, according to the present invention, no protection diode is formed in the chip _T4 of the MOS field effect transistor, and the chip T4 of the MOS field effect transistor is
Since there is no need for wiring on _T4 , there is no increase in gate-drain capacitance (Cgd). Also, since there is only a MOS field effect transistor inside the chip _T4 of the MOS field effect transistor,
There is a lot of freedom in design, such as placement, without considering the relationship with the gate oxide film protection diode. FIG. 4 is a cross-sectional structural diagram of the chip _T3 of the input impedance matching MOS capacitor according to the embodiment of the present invention shown in FIG. In Figure 4,
Components equivalent to those in FIG. 3 are designated with the same reference numbers and symbols. As shown in FIG. 4, in the present invention, a diode for protecting the gate oxide film of the MOS field effect transistor is formed within the chip of the MOS capacitor for input impedance matching. The input impedance matching MOS capacitor is composed of an N-type capacitor substrate 13, an insulating film 14, and an Al electrode 15, and includes a gate oxide film protection diode _D4 ,
_D5 is formed by the capacitor N-type substrate 13, the P-type diffusion layer 16, and the N-type diffusion layer 17. As an embodiment of the high frequency semiconductor device of the present invention,
The explanation was given using as an example a configuration in which a bidirectional diode consisting of an input impedance matching MOS capacitor and two gate oxide film protection diodes is formed on the same chip. , a configuration may be used in which the gate oxide film is protected against the unidirectional polarity of the surge voltage. In addition, the explanation was given using an N-channel vertical double-diffusion transistor as an example of a MOS field effect transistor, but the same effect can be obtained with a P channel or other structure, such as a V-groove gate structure. It goes without saying that there is. Effects of the Invention The present invention brings about the following effects. (1) There is no reduction in breakdown voltage between the gate and drain and between the source and drain due to the diode for protecting the gate oxide film. (2) High voltage is not applied to the gate oxide film protection diode, improving reliability. (3) There is no increase in gate-drain capacitance (Cgd) associated with gate oxide film protection diodes;
There is no decrease in the gain of MOS field effect transistors.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram of a conventional high-frequency semiconductor device, FIG. 2 is a cross-sectional diagram of a chip cross-section of a MOS field effect transistor used in a conventional high-frequency semiconductor device, and FIG. 3 is an example of a high-frequency semiconductor device of the present invention. FIG. 4 is a cross-sectional view of a chip of an input impedance matching MOS capacitor used in an embodiment of the high frequency semiconductor device of the present invention. G...Gate terminal, D...Drain terminal, T ₃
...MOS capacitor chip for input impedance matching, C _i ...MOS capacitor, T ₄ ...
MOS field effect transistor chip, D ₄ , D ₅ …
...Diode for gate oxide film protection.

Claims (1)

[Scope of Claims] 1. A first chip in which a high voltage MOS field effect transistor is formed and a MOS capacitor for input impedance matching are formed in the same package, and a second chip separate from the first chip. The transistor is sealed, the gate electrode of the transistor and the MOS capacitor are connected to each other via a bonding wire, and a diode for protecting the gate oxide film of the transistor is formed in a second chip in which the capacitor is formed. A high frequency semiconductor device characterized by: 2. The high frequency semiconductor device according to claim 1, wherein the diode is a bidirectional diode.