JPS60222925A - Magnetic disk device - Google Patents

Abstract

PURPOSE:To prevent the order of writing to and reading from RAM from being reversed and to utilize effectively the whole capacity of the RAM by providing a reset circuit which resets the address counter of the RAM at the start of access to the RAM. CONSTITUTION:The address counter 12 of the RAM5 is reset by a read/write signal output circuit 8 when data begins to be transferred from an IC 3 to the RAM5 with an instruction from a host system 4. Therefore, the circuit 8 serves as the reset circuit of the counter 12. Then, the counter 12 updates the address every time one byte of data read from a driver 1 is transferred to the RAM5. Consequently, when the data exceeds the capacity of the RAM5, the generation of a read/write signal to the RAM5 is interrupted forcibly. Further, the transfer of data from the RAM5 to the system 4 is performed similarly at a request from the system 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a magnetic disk device including a random access memory in a controller.

[Prior art]

Conventionally, for example, a magnetic disk drive connected to a host system computer directly transfers data via a path line between the controller large-scale integrated circuit (+-3L) of the magnetic disk drive and the computer. It was like that. Because of this direct transfer, the data transfer speed was determined by the drive speed of the magnetic disk. Therefore, computers cannot transfer data at arbitrary times, and this has a large effect, especially on host computers that require extremely high performance, making it difficult to write efficient programs. .

[Purpose of the invention]

As a magnetic disk device that solves the above conventional problems, the applicant has developed a random access memory (random access memory) that temporarily stores data transferred to and from a computer on the controller side.
We have developed a magnetic disk drive that improves the performance of a combi coater by using this memory as an intermediate and relay to provide more precise data transfer timing in a computer.

This invention was made in connection with the above-mentioned statement, and is capable of resetting the memory by providing a reset circuit that resets the address counter of the random access memory provided in the controller 1 at the start of accessing the memory. Prevents reversal of the order of writes and reads to
Moreover, it is an object of the present invention to provide a magnetic disk device that can effectively utilize the entire capacity of its memory.

[Structure of the invention]

The present invention is characterized in that the random access memory provided in the controller of the magnetic disk device is configured to be reset by a reset circuit when the random access memory is started to be read/written by an instruction code from the computer. .

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described based on the drawings.

In the figure, 1 is a drive of a magnetic disk device, and 2 is its controller. The large-scale integrated circuit (IsI) 3 is the main component of these circuits 1 to 2. A pass line is formed between the controllers 1 to 2 and the ij-st system 4, and data transfer between the magnetic j-isf device and the host system 4 is performed through the controller 2. There is. The controller 2 is equipped with a random access memory (hereinafter referred to as rRAMJ) 5 located in a path line between the host systems 4 . This RAM 5 is used for transferring data from the drive 1 to the host system 4, d5 and vice versa.
This is to temporarily store data transferred from the drive 1 to the drive 1.

Hereinafter, each circuit provided in the controller 2 will be explained along with its operation.

For data transfer, RAM 5 is used as a relay from drive 1 to post system 4, and RAM 5 is used as a relay.
, 5 as a relay from the host system 4 to the drive 1.

Therefore, first, the former transfer, that is, the transfer from the drive 1 to the host system 4 using the RAM 5 as a relay will be explained.

For data transfer in this direction, first drive 1 to RAM
A first stage transfer from RAM 5 to post system 4 takes place, followed by a second stage transfer from RAM 5 to post system 4.

(1) First-stage transfer This transfer command is given from the host system 4 to the controller 2 as a control signal. In this case, the control signal requests the commie roller 2 to read data from the drive 1. The control signal is input to the read/write discrimination circuit 6 of the controller 2. This discrimination circuit 6 is configured so that the input control signal is connected to the integrated circuit 3 and R.
It is determined whether the request requests data transfer between the RAM 5 and the host system 4. Here, it is determined that the request is the former. Next, the host system 41) 1.1
These instruction codes cause the data transfer direction determining circuit 7 to
4. Determine whether Higashinoki is a read or a write for AM5. Here, it is determined that there is a request C for the RAM 5. As a result, it is determined whether the data is to be transferred from the integrated circuit 3 to the RAM 5, and this is transmitted to the read/write signal output circuit 8.

Then, the integrated circuit 3 reads data from the drive 1 through the read/write circuits 1 to 9, and requests that the data read by step A be transferred to the outside of the integrated circuit 3. In response to this request, the read/write code generation circuit 10 outputs a data transfer signal between the integrated circuit 3 and the RAM 5 to the read/write signal output circuit 8 at a timing that meets the request. The oscillation signal of the oscillator 11 is used to set the timing. Upon receiving this data transfer signal, the read/write signal output circuit 8 issues a write command to the RAM 5 based on the previously received instruction in the data transfer direction, that is, the instruction to transfer data from the integrated circuit 3 to the RAM 5. , is issued in accordance with the data transfer signal from the read/write signal generation circuit 10. RAM that received this write command
5 sequentially stores the transfer data from the integrated circuit 3.

The address counter 12 of the RAM 5 is
It is reset by the read/write signal output circuit 8 when data transfer is started by a command from the read/write signal output circuit 8.

Therefore, in this respect, the read/write signal output circuit 7 can be said to be a reset circuit for the address counter 12. Then, each time the data read by the integrated circuit 3 from the drive 1 is transferred to the RAM 5 one byte at a time, the address counter 12 updates the address one by one.

When the address exceeds the capacity of the RAM 5 due to this update, the address counter 12 outputs a prohibition signal to the read/write signal generation circuit 10 to forcibly stop the generation of read/write signals to the RAM 5. For this reason, R.A.
Access exceeding the capacity of M4 is prevented.

In this way, the data transfer from the drive 1 to the RAM 5 is completed.

■ Second stage transfer This transfer is requested by the host system 4 at any time. This request signal is determined by the read/write discrimination circuit 6 and the data transfer direction determination circuit 7 as in the case of the transfer described above. Then, the address counter 12 is reset by the read/write signal output circuit 8, and RΔ
“Each time one byte of data is transferred from M5 to host system 4, address counter 12 updates the address one by one. When the address exceeds the capacity of RAM 5 due to this update, address counter 12 Similarly, a signal prohibiting access to the RAM 5 is issued.

The above is an explanation of the transfer from the drive 1 to the host system 4 using the RAM 5 as a relay, and then about the transfer in the opposite direction, that is, from the host system 4 to the drive 1 using the RAM 5 as a relay. explain.

This transfer is also divided into two stages: transfer from the host system 4 to the RAM 5, and transfer from the RAM 5 to the drive 1.

First, a transfer command from the host system 4 to the RAM 5 is issued from the host system 4, and its contents are determined by the read/write discrimination circuit 6 and the data transfer direction determination circuit 7. Then, the address counter 12 is reset by the read/write signal output circuit 8, and the address counter 12 updates one address each time one byte of data is written from the host system 4 to the RAM 5. When the address exceeds the capacity of the RAM 5 due to this update, the address counter 12 issues a signal prohibiting access to the RAM 5. After writing data to the RAM 5 in this manner, when the host system 4 issues a command to transfer data from the RAM 5 to the drive 1, the contents of the command are transmitted to the read/write discrimination circuit 6 and the data transfer direction determining circuit 7. It is determined by Then, the address counter 12 is reset by the read/write signal output circuit 8, and each time one byte of data is read from the RAM 5 and written to the drive 1, the address counter 12 updates the address one by one. This update changes the address to
When the capacity of AM5 is exceeded, the address counter 12
A signal prohibiting access to AM5 is issued.

As described above, by transferring data via the RAM 5, the host system 4 can request data transfer at its own most efficient time, and can transfer data without being affected by the data transfer speed of the drive 1. Transfer can be performed at high speed.

Note that by connecting to the address counter 12 an alarm device that issues an alarm in response to the access prohibition signal for the random access memory 5 output by the address counter 12,
It is possible to proactively notify the operator that there has been an abnormal access to the random access memory 12 that exceeds its capacity.

〔Effect of the invention〕

As explained above, the magnetic disk device of the present invention has
When accessing the random access memory provided in the controller starts, the address counter for that memory is reset.
, it is possible to avoid reversing the order of writing and reading from the memory. Furthermore, since access to the random access memory always starts from address "0", the full capacity of the random access memory can be used at any time. Also,
Address management of the random access memory is limited to resetting and updating the address counter, which simplifies the circuit and reduces malfunctions.

[Brief explanation of the drawing]

The drawing is a block diagram showing an embodiment of the present invention. 1...Drive, 2...Controller, 3...Integrated circuit, 4...Host system (computer), 5...Random access Memory (RAM), 8...read/write signal output circuit (reset circuit), 12...address counter.

Claims (1)

[Claims] In a magnetic disk device that transfers data to and from a computer through a magnetic disk controller,
The controller includes a random access memory that is located in a path line between the controller and the computer and temporarily stores transfer data, and an address that sequentially counts the storage address when reading/writing transfer data to/from the random access memory. 1. A magnetic disk drive comprising: a counter; and a reset circuit that resets the address counter at the start of random access memory read/write based on an instruction code from a computer.