JPS60222926A - Magnetic disk device - Google Patents

Abstract

PURPOSE:To prevent RAM from being accessed beyond its capacity by providing an address counter which outputs an access inhibiting signal when an address beyond the capacity of the RAM is counted. CONSTITUTION:The address counter 12 of the RAM5 is reset by a read/write signal output circuit 8 when the transfer of data is started with an instruction from a host system 4. Then, the counter 12 updates the address by one every time one byte of data read from a driver 1 is transferred to the RAM5. When the updated address goes beyond the capacity of the RAM5, an inhibiting signal for interrupting forcibly the generation of a read/write signal to the RAM5 is outputted to a read/write signal generating circuit 10. Further, the transfer of data from the RAM5 to the system 4 is performed similarly at a request from the system 4. Consequently, access exceeding the capacity of the RAM5 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention covers a magnetic disk device including a random access memory in a controller.

[Prior art]

Conventionally, for example, a magnetic disk device connected to a pump coater of a host system directly transfers data via a path line between the controller large-scale integrated circuit (1-3l) of the magnetic disk device and the computer. I was supposed to. Because of this direct transfer, the data transfer speed was determined by the drive speed of the magnetic disk. Therefore, computers cannot transfer data at arbitrary times, and this has a large effect, especially on host computers that require high performance, making it difficult to write efficient programs. .

[Purpose of the invention]

The present applicant has proposed a random access system (R
We have developed a magnetic disk device that is equipped with AM) and uses this memory as a relay to give flexibility in the timing of data transfer in the combicoater, thereby improving the performance of the combicoater.

This invention 1 was made in connection with the development described in section 2 above, and is intended to prevent accesses beyond the capacity of the random access message provided in the controller from being executed. 1 magnetic disk device that can prevent
1? The purpose is to provide.

(Structure of the Invention) According to the present invention, when an address counter of a random access memory provided in a controller of a magnetic disk device counts an address exceeding the capacity of the random access memory, the address counter The present invention is characterized in that it is configured to output a prohibition signal for prohibiting access.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described based on the drawings.

In the figure, 1 is a drive of a magnetic disk device, and 2 is a controller 1 to a roller thereof. This =+controller 2 is person 7J
The main integrated circuit is LSI'>3.A path line is formed between the controller 1-2 and the boss system 4, and data transfer between the magnetic disk device and the boss system 4 is performed. is performed through the controller 2.The controller 1 and the controller 2 are equipped with a random access memory (hereinafter referred to as IRAMJ) 5 that is located in the path line between the host systems 4. M5 briefly stores data transferred from the drive 1 to the host system 4, and vice versa from the host system 4 to the drive 1.

Hereinafter, each circuit provided in the controller 2 will be explained along with its operation.

Data transfer involves transfer in the direction from drive 1 to boss system 1 using RAM 5 as a relay, and
There are two types of transfer: one from the post system 4 to the drive 1 using the post system 4 as a relay.

Therefore, first, the former transfer, the transfer from the drive 1 that relays the RAM 5 to the host system 4, will be explained.

For data transfer in this direction, the data transfer from drive 1 to RA
A first stage transfer to M5 takes place, followed by ΔM at 1
A second stage transfer from 5 to boss 1 to system 4 takes place.

(1) First stage transfer This transfer command is given from the host system 4 to the C controller 2 as control number 111. In this case, the control signal requests the controller 2 to read data from the drive 1. The control signal is input to the read/write discrimination circuit 6 of the controllers I to D-2. This discrimination circuit 6 determines whether the input control signal is a request for data transfer between the integrated circuit 3 and the RA fvl 5, or a request for data transfer between the RAM 5 and the host system 4. Here, it is determined that it is the former request.

Next, based on the instruction code from the host system 4, the data φl and sending direction determining circuit 7 determines whether the request is for f3 A M 5, a read, or a write. Here, it is determined that the request is a request to [RAN 45]. As a result, it is determined that the data transfer direction is from the integrated circuit 3 to +t A M 5, and therefore the signal is output to the -1-/rai 1- signal output circuit 8.

Then, the integrated circuit 3 requests the read/write 1 to read data from the drive 1 through the circuit 9 and send the read data to the outside of the integrated circuit 3. Due to this request, read/write No. 1-16 creation circuit 1
0 reads/writes the data transfer signal between the integrated circuit 3 and the RAM 5 at a timing that meets the request [for signals]j
Output to circuit 8. When setting the timing,
An oscillation signal from the oscillator 11 is used. This data transfer 1
The read/write signal output circuit 8 that has received No.
With the instruction to transfer data to A fvl 5,
A write command to 1λ8M5 is combined with a data transfer signal from the read/write ID number generation circuit 10 and emitted.

Upon receiving this write command, the RAM 5 sequentially stores the transferred data from the integrated circuit 3.

The address counter 12 with f<AM 5 is reset by the read/write circuit 1 to the signal output circuit 8 when data transfer is started in response to a command from the host system 4 . Therefore, at this point, the lead/lie 1
~ (The No. 8 output circuit 7 can be said to be a ret circuit of the address counter 12. Then, the integrated circuit 3 reads lυ/j data from the drive 1 by 1 pie i~) , the address counter 12 updates the address one by one.

When the address exceeds the capacity of the RAM 5 due to this update, the address counter 12 outputs a prohibition signal to the read/write signal generation circuit 10 to forcibly stop the generation of read/write signals to the RAM 5. . Therefore, access exceeding the capacity of RAM 4 is prevented.

In this way, data transfer from drive 1 to RAM 5 is completed.

■ Second stage transfer This transfer is requested by the host system at any time. This request signal is transmitted to the read/write discrimination circuit 6 and the data transfer direction determining circuit 7, as in the case of the above-mentioned transfer.
It is judged by. Then, the address counter 12 is re-hit by the read/write signal output circuit 8, and the R
Every time one byte of data is transferred from the A M 5 to the small storage system 4, the address counter 12 updates the address by one.This update causes the address to be +<A.
When the capacity of RAM 5 is exceeded, the address counter 12 issues a prohibition signal for access to RA fvl 5, as in the case of transfer described above. 4, and then the opposite direction, that is, the transfer from the host system 4 to the drive 1 using the RAM 5 as a relay will be explained.

If this transfer is the case then Hoss! - Divided into two stages: transfer from system 4 to RAM 5 and transfer from RAM 5 to drive 1.

First, a transfer command from the host system 4 to the RAM 5 is issued from the host system 4, and its contents are read/transferred.
This is determined by the write discrimination circuit 6 and the data transfer direction determination circuit 7. The rear address counter 12 is then reset to the read/write signal output circuit 8, and the address counter 12 updates the address by one each time one byte of data is written from the host system 4 to the RAM 5. . As a result of this update, the address exceeds the capacity of RAM E5, and the address counter 12 becomes [<ΔM
5.1 No access prohibition signal is issued. After writing data to the RAM 5 in this way, when the host system 4 issues a command to transfer data from the RAM 5 to the drive 1, the content of the command is transferred to the read/write discrimination circuit 6 and the data transfer. J is determined by the direction determining circuit 7. Then, the address counter 12 is reset by the read/write 1~signal output)j circuit 8, and each time one byte of data is read from the RAM 5 and input to the drive 1, the address counter 12 registers one address. Updated one by one. When the address exceeds the capacity of the RAM 5 due to this update, the address counter 12 does not issue an access prohibition signal to the RAM 5.

As described above, by transferring data through RAM 5, host system 4 requests data transfer at its own most efficient time, and is subject to the transfer speed of drive 1. It is possible to transfer data at high speed without any trouble.

In addition, by connecting an alarm device to the address counter 12 that issues an alarm in response to the random access prohibition signal outputted from the address counter 12, the capacity of the random access memory 12 can be reduced. It is possible to proactively notify the operator that there has been an abnormal access that exceeds the limit.

〔Effect of the invention〕

As explained above, the magnetic disk device according to the present invention outputs the access prohibition IS Uj when the address counter of the random access memory stored in the controller or the address exceeding the capacity of the random access memory is counted. It is possible to prevent random access memory from being accessed beyond its capacity. As a result, for example, the controller may access more random access memory than it can, and the host system may load incorrect data onto the drive.
I've never had a problem where the data from the drive is stored in the random address memory, or only part of the data from the drive is stored in the random address memory.

[Brief explanation of the drawing]

The drawing is a block diagram showing one embodiment of the present invention. 1...drive, 2...=1 controller, 3...integrated circuit, 4...host 1 system ("nobita-1-ta"), 5 ...Random access memory (R△~1), 8...Read/write signal output circuit (ret circuit), 12...
address counter. Applicant Toki] Co., Ltd.

Claims (2)

[Claims] (1) In a magnetic disk device that transfers data to and from a computer through a magnetic disk controller, the controller includes a random access memory that is located in a path line between the controller and the computer and temporarily stores transferred data; When reading/writing transfer data to this random access memory, the storage addresses of the transfer data are sequentially counted, and when the counted addresses exceed the capacity of the random access memory, access to the random access memory is prohibited. A magnetic disk device comprising an address counter that outputs a prohibition signal. (2) The magnetic disk device as set forth in claim 1 or 2, wherein an alarm device is connected to the address counter to issue an alarm when a prohibition signal output from the address counter is received.