JPS60222924A - Magnetic disk device - Google Patents

Abstract

PURPOSE:To supply a degree of freedom to the transfer timing of data in a computer and to improve its performance by providing RAM which is positioned in the bus line between a controller and a computer and stored transfer data temporarily. CONSTITUTION:A control signal from a host system 4 is inputted to the read/ write discriminating circuit 6 of the controller 2 and the circuit 6 discriminates a request for data transfer between an IC3 and the RAM5. Then, a data transfer direction determining circuit 7 discriminatdd a write request to the RAM5 with an instruction code from the system 4. Consequently, the IC 3 reads data from a driver 1 and transfers and writes it to and in the RAM5. At this time, an address counter 12 updates the address, one by one, every time one byte is transferred. Then, data is transferred from the RAM5 to the system 4 with the request signal from the system 4. At this time, a counter 12 updates the address, one by one, similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a magnetic disk device including a random access memory in a controller.

[Prior art]

Conventionally, for example, a magnetic disk device connected to a combi coater of a host system directly transfers data via a path line between a large scale integrated circuit (LSI) for the controller of the magnetic disk device and a computer. J-It was turning. Because of this direct transfer, the data transfer speed was determined by the drive speed of the magnetic disk. Therefore, computers are unable to transfer data at arbitrary times, and this has a significant impact, especially on host computers that are required to have high performance, making it difficult to write efficient programs. Ta.

[Purpose of the invention]

This invention solves the above conventional problems, and includes:
By equipping the controller side of the magnetic disk drive with a random access memory (RAM) that stores the data transferred to and from the computer, it gives flexibility in the timing of data transfer to the computer and improves its performance. The objective is to provide a magnetic disk device that achieves this.

[Structure of the invention]

This invention provides a controller for a magnetic disk device that is located in a path line between it and a computer.
i'～riwo～I1. +! It is assumed that the computer is equipped with a random access memory (RAM).

(Embodiment of the Invention) Below, an embodiment of this invention will be explained based on the drawings.
Ru.

In the figure, 1 is the dry sea (with magnetic disk surface), and 2 is the number 1 to D-La. A path line is formed between the components 1" to 2 and the host system 4, and data transfer between the magnetic disk device and the host system 4 is performed via the nodes 1 to 2 and the host system 4. 41 so that you can go through 2.Conl-[]-ra2
In the lotus line between Hos 1 and Hesisnom 2 and M 4, there is a length of the device, and an Ak l! Sumeshiri (1st small r RA)
It is equipped with 5 (called MJ). This RAM
Reference numeral 5 indicates a memory read for data transferred from the drive 1 to the host system 4 (-11 for intermediate transfer data from the host system 4 to the drive 1 and vice versa).

Hereinafter, each circuit provided in the rollers 1 to 2 will be explained along with their functions.

Data transfer includes transfer from drive 1 to host system 4 via RAM 5, etc.
There are two routes, Φ, in the direction of drive 11\ from small bus I to system ram 4 ht I, which relay the data.

First, we will explain the former transfer, from drive 1 to host system 4 using RAM 5 as a relay.

For data transfer in this direction, first RA
The first stage transfer to M5 is performed, and the first step (to R
The second stage transfer from AM5 to host system 4 is on line 4.
＾It will be done.

■ First stage transfer This transfer command (J1 small system 4 to 1laJ t
The al+ signal is applied to the controller 2. In this case, the control signal is sent to controller 1 from c1 to c2.
This is a request to read data from drive 1. The control signal is input manually to the read/write discrimination circuit 6 of the controller I/roller 2. This discrimination circuit 6 determines whether the input control signal requests data transfer between the integrated circuit 3 and the RAM 5, or between the RAM 5 and the host system.
It is determined whether there are four computers requesting data transfer to or from the system 4. This is considered to be the former request. Next, according to commands ``-1'' from the small system 7 system 4, the data φm sending direction determining circuit 7 or the RAM 5 is requested to read or 1 to determine whether it is a gap or a gap. Here, it is determined that the request is a RA 1-request that appears in RA fvl 5. As a result, the transfer direction is 11 3/Jl r 1
It is determined that the direction is ΔME), and this is communicated to the read/write signal output 1mlλ″88.

Then, the integrated circuit 3 requests that all circuits from the read/write circuit 1 to the circuit 9 read data from the drive 1 and transfer the read data to the outside of the integrated circuit 3. The signal generation circuit 10 outputs the data transfer signal between the integrated circuit 3 and the RAM 5 to the write signal output circuit 8 at a timing that meets the request.In setting the timing, the oscillator 1
One oscillation signal is used. This data transfer signal (
) or -1, 2/write signal output circuit 8 first sends an instruction in the direction of data transmission, that is, from the integrated circuit 3 to R.
From the instruction 1 to transfer A M 5'\data, a write command to RAM 5 is executed as read/'write command.
- In accordance with the data transfer signal from the signal generation circuit 10! It shines (). The RAM 5 sequentially stores the transfer data from the integrated circuit 3.

The address counter 12 of the RAM 5 is set to 1! by a command from the host system 4. , when the transmission is started, it is rechecked by the L number output horn circuit 8. In this respect, it can be said that the read/write circuit 1 to the signal output circuit 7 are equivalent to the circuits 1 to Q of the read/write counter 12. Then, each time the data read from the integrated circuit 3 or the drive '1 is transferred to ΔM5 by 1, the address counter 12
updates the addresses one by one.

When the address exceeds the capacity of RΔL5 due to this update, the address counter 12 outputs a prohibition signal to the read/write 1 signal generation circuit 10 to forcibly stop the generation of the read/write signal to the RAM 5. For this reason, R
Access beyond the capacity of AM4 is prevented.

In this way, the data transfer from the first drive to ΔM5 is completed.

■ Second Stage Transfer This transfer is requested by the post system 4 at any time. This request signal is transmitted to read/write 1 to discrimination circuit 6 and data transfer direction determining circuit 7, as in the case of transfer described above.
It is judged by. Then, the read/write signal output corner circuit 8 is set to J, the rear address counter 12 is reset, and the data is transferred from RAM 5 to the host system 4 1 by 1. Updates one by one. As a result of this update, when the address exceeds the capacity of ΔM5, the address counter 12 issues a knockless prohibition signal to the RAM 5, as in the case of transfer described above.

The above is an explanation of the transfer from the drive 1 to the host system 4 using the RAM 5 as a relay.
Next, the transfer in the opposite direction, that is, from the host system 4 to the drive 1 using the RAM 5 as a relay, will be explained.

This transfer is also divided into two stages: transfer from the host system 4 to the RAM 5, and transfer from the RAM 5 to the drive 1.

First, a transfer command from the host system 4 to the RAM 5 is issued from the host system 4, and its contents are determined by the read/write discrimination circuit 6 and the data transfer direction determination circuit 7. Then, the address counter 12 is reset by the read/write signal output circuit 8, and each time data is written from the host system 4 to the RAM 5 in 1 by 1, the address counter 12 increments the address one by one.
Ru. When the address exceeds the capacity of the RAM 5 due to this update, the address counter 12 issues a signal prohibiting access to the RAM 5. After rinsing the data into the RAM 5 in this way, the host system 4
When a command for data transfer is issued from the AM 5 to the drive 1, the content of the command is determined by a read/write discrimination circuit 6 and a data transfer direction determining circuit 7. Then, the read/write signal output circuit 8 outputs the address counter 12.
The address counter 12 updates the address one by one each time data is read from the RAM 5 by one byte and written to the drive 1. When the address exceeds the capacity of RAM 5 due to this update, address counter 12 issues a signal prohibiting access to RAM 5.

It is to be noted that an alarm device is connected to the address counter 12, which issues an alarm when the address counter '12 outputs a prohibited access to the random access memory 5. It is possible to proactively inform the A operator that there has been an abnormal (exceeding) access.

〔Effect of the invention〕

As explained above, the magnetic disk device of the present invention has
Random access memory is installed in the magnetic disk controller, and this memory is used as a relay to transfer data between the computer and the computer, so the computer uses its own most efficient It is possible to request data transfer at a good time and perform the data transfer at high speed without being affected by the data transfer speed of the drive. Furthermore, by storing data for one track of the drive in a random access memory provided in the controller, this controller can be used as an external storage device for a computer. Also, Con1-
The data stored in the random access memory in the controller also serves as a backup data; for example, if the data is deleted due to a drive failure, the data remaining in the controller can be used, reducing the probability of data loss. It becomes less.

[Brief explanation of drawings]

The drawing is a block diagram representing one embodiment of the invention. 1...Drive, 2...Controller, 4...Host system (computer), 5
・・・・・・Random access method (RA~1), 1
2...Address counter.

Claims (1)

[Claims] In a magnetic disk device that transfers data to and from a computer through a magnetic disk controller,
A magnetic disk device characterized in that the controller includes a random access memory that is located in a path line between the controller and the computer and temporarily stores transferred data.