JP3062513B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor (MPU) used in a computer system having a weight function.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of a conventional computer having a wait function. In the figure, 1 is MP
U and 2 are memories, 3 is a peripheral device connected to the MPU 1 via the signal line 6 and the data line 7, and 4 is a wait control circuit for controlling the wait state of the MPU 1.

When the MPU 1 reads data from the peripheral device 3 according to an instruction given from the memory 2 to the MPU 1, if the response speed of the peripheral device 3 is slower than the operation speed of the MPU 1, the MPU 1 is put into a wait state. Must be set. To this end, the wait control circuit 4 outputs a wait request signal to the MPU 1 for a certain period of time when a read signal is output from the MPU 1 to the peripheral device 3 via the signal line 6 to the peripheral device 3 to set the MPU 1 to the wait state. I do.

[0004]

Generally, since a large number of peripheral devices are connected to a computer, it is necessary to control the wait time of the MPU in accordance with the response speed of each peripheral device. Is very complicated.

If the wait time of the MPU is adapted to the peripheral device having the slowest response speed, the configuration of the wait control circuit can be simplified. As a result, the MPU is set in the wait state for an unnecessarily long period of time, so that the operation speed of the entire system is reduced.

The present invention has been made in view of the above problems, and provides a microprocessor which has a function of controlling a wait time according to the response speed of a peripheral device and does not require the provision of a wait control circuit. Is to do.

[0007]

In order to achieve the above object, a microprocessor according to the present invention comprises: means for transmitting an access signal to a peripheral device when given an instruction to access the peripheral device; , wherein the period corresponding to the wait time information indicating the number of wait cycles is added to the instruction, and means for setting the internal wait state.

[0008]

[Action] When the instruction sent from the memory is for instructing access to the peripheral device, the wait time information indicating the number of wait cycles in accordance with the response speed of the peripheral device while the instruction is being added. When the microprocessor receives this instruction, it sends an access signal to the peripheral device. At the same time, the wait time information processing circuit built in the microprocessor decodes the wait time information, sets the microprocessor to the wait state for the specified number of cycles, and waits for a response from the peripheral device. I do.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of one embodiment of a computer system having a microprocessor according to the present invention. In FIG. 1, a memory 11 is connected to an MPU 10 via a data line 14. Further, a plurality (three in this case) of peripheral devices 12a, 12b, and 12c are connected to the MPU 10 via a signal line 15 and a data line 14. The MPU 10 has a wait time information processing circuit 13
Is built-in.

Next, the operation of the computer system will be described. Here, it is assumed that the response speed of the peripheral devices 12a and 12b is relatively slow, the number of wait cycles required for the peripheral device 12a is 3, and the number of wait cycles required for the peripheral device 12b is 2. The response speed of the peripheral device 12c is relatively fast, and the number of wait cycles required for the peripheral device 12c is one.

[0011] Of the instructions stored in the memory 11,
Instructions for accessing peripheral devices, for example, "IN", "OU"
The instructions such as “T” and “LOAD” have wait time information added thereto.
When a command to access the peripheral device 12a is sent to the U10, at the same time, "3" is sent to the MPU 10 as wait time information. At this time, the MPU 10 sends an access signal to the peripheral device 12a via the signal line 15.
On the other hand, the wait time information processing circuit incorporated in the MPU 10 determines the MP time according to the wait time information “3”.
U10 is set in a wait state for a period of three wait cycles.

Similarly, when an instruction to access the peripheral device 12c is sent from the memory 11 to the MPU 10, "1" is sent to the MPU 10 as wait time information at the same time. At this time, the MPU 10 sends an access signal to the peripheral device 12c via the signal line 15. On the other hand, MPU
The wait time information processing circuit built in 10 sets the MPU 10 to the wait state for one wait cycle according to the wait time information “1”. As described above, the wait time of the MPU 10 depends on the peripheral devices 12a, 1
Optimum control is performed for each command according to the response speed of 2b and 12c.

As a method of adding wait time information to an instruction for instructing access to a peripheral device and storing the instruction in the memory 11, for example, one byte is composed of 10 bits, the instruction is represented by 8 bits as in the conventional case, and the remaining 2 bytes are used. The wait time information can be represented by bits. Alternatively, a new instruction may be defined in which 6 bits out of 8 bits represent an instruction and the remaining 2 bits represent wait time information.

[0014]

As described above, according to the present invention, the microprocessor of the present invention, when given an instruction for access to the peripheral device, means for sending an access signal to the peripheral device, added during the instruction Means for setting the inside to a wait state for a period according to the wait time information indicating the number of wait cycles. Therefore, in the computer system having the microprocessor of the present invention, the microprocessor does not need a weight input terminal, and even if a large number of peripheral devices having different response speeds are connected, without having to provide a complicated weight control circuit, The microprocessor can be set in the wait state for the number of cycles corresponding to the response speed of the peripheral device, and the system can operate at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a computer system having a microprocessor of the present invention.

FIG. 2 is a block diagram of a conventional computer system including a weight control circuit having a conventional microprocessor.

[Explanation of symbols]

 1, 10 MPU 2, 11 Memory 3, 12a to 12c Peripheral device 4 Weight control circuit 13 Wait time information processing circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Fumio Murooka 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Yukihiro Yoshida 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Sharp Corporation (56) References JP-A-2-162451 (JP, A) JP-A-59-91544 (JP, A)

Claims (1)

(57) [Claims] When 1. A given an instruction for access to the peripheral device, according to the wait time information indicating means for sending an access signal to the peripheral device, the number of wait cycles is added in the instruction Means for setting the inside to a wait state for a period of time.