JPH03286237A - Control system for storage device - Google Patents

Abstract

PURPOSE:To realize high-speed data transfer by providing an external storage access instruction different from an I/O control instruction so that an I/O processor controls an external memory device. CONSTITUTION:The I/O processor 3 receives the specified external storage access instruction 1' issued from a central processing unit 1. The processor 3 reads a command word string CCW for accessing the external memory device 6 out of the command address area of a main storage device 5, and analyzes it, and generates and outputs a read/write command, etc., for the device 6. By analyzing the command word string CCW, the processor 3 executes autonomously operation to transfer data shown by transferring quantity from the device 6 to the main storage device 5. At that time, the data of the transferring quantity designated by the command word string CCW is transferred to a memory control device 2 by the same control system as at the time of the data transfer from an input/output device 7.

Description

[Detailed Description of the Invention] [Summary] Regarding a control method for an external memory device, such as a semiconductor memory device, connected to a computer system having a ■/○ processor that controls multiple channels, the load on the central processing unit is increased. The purpose is to control large-capacity semiconductor memory devices faster than data transfer for input/output processing, without causing data transfer.
An external memory device different from the device is connected to the above-mentioned I/O processor and placed under it, and an external memory access instruction different from the I/O command is provided to create a command system different from the I/O control command. (2) The I/O processor is configured to control the external memory device.

[Industrial application field]

The present invention relates to a method for controlling a semiconductor memory device, which is different from an I/O device such as a semiconductor disk device.

In recent years, with the growth of applications, the lack of main memory space has become a problem. Therefore, there is a need for a new high-speed semiconductor memory device that has a vast address space separate from the main memory.

This is because if the address space of the main memory is expanded unnecessarily, the number of bits in the address register for the main memory will increase, making control from both software and hardware complicated. This is because not only does it reduce the access time of the device, but it also increases the load on the central processing unit.

Under these circumstances, there is a need for a storage device control method that can access the large-capacity semiconductor memory device without increasing the load on the central processing unit and at a higher speed than data transfer through an input/output interface.

[Prior art and problems to be solved by the invention] FIG. 2 is a diagram illustrating a conventional storage device control system, and (a)
(b) shows a case in which a semiconductor memory device is added to a memory control device, and (b) shows a case in which a semiconductor memory device is connected to a channel device (channel).

When adding a new semiconductor memory device 6 having an address space different from that of the main memory device 5, as shown in FIG. A possible method is to connect 6).

In this case, control of the external memory device 6 is performed by hardware according to specific instructions from the central processing bag W1.

Specifically, the format of the particular instruction is the same as a load/store instruction to main memory, but with an "operation code"
will be different.

Therefore, it is necessary to add to the memory control device 2 an interface (a connector, a control unit, etc.) 20 that supports memory access by the specific command.

Furthermore, in this method, the external memory device 6 is accessed by the central processing unit W1 executing the above-mentioned specific command, so there is a problem that the load on the central processing unit 1 increases.

Next, the semiconductor memory device (semiconductor disk device) is connected to the channel device (channel) 4 connected to the I/O processor 3 as shown in FIG. In the configuration in which a is connected, it is controlled by general I/O commands, has the same output interface as a normal I/O device, and uses the same transfer method. Specifically, the semiconductor memory device 7a operates with the same specifications as a magnetic disk device.

Therefore, in the case of the semiconductor memory device, that is, the semiconductor disk device 7a, data transfer with the I/O processor 3 is performed in the same manner as the conventional ■/○ transfer, so it is different from the conventional I/O device. There was a problem in that data transfer could only be performed at the same speed, and the high-speed access performance of the semiconductor memory device f7a could not be fully utilized.

In view of the above-mentioned drawbacks of the conventional art, the present invention provides a computer system having an I/O processor that controls a plurality of channels without increasing the load on the central processing unit (and the input/output device 1!! (I/O The purpose of this invention is to provide a method for controlling a large-capacity semiconductor memory device faster than data transfer to the device.

[Means to solve the problem]

The above problems can be solved by a control method for a semiconductor memory device configured as follows.

(1) In a computer system that has an I/O processor that controls multiple channels, connect an external memory device that has an address space different from the main storage device and is different from the I/O device to the I/O processor. Then, an external memory access command different from the ■/○ command is provided under it, and the I/O processor controls the external memory device by a command system ■ different from the I/O control command. Configure it to do so.

(2) The I/O processor is configured to control the external memory device by a microprogram.

[Effect]

That is, according to the present invention, an external memory device, for example, a semiconductor memory device, having a new address space different from the address space of the main memory device, has an interface with the main memory instead of a memory control device, and has an interface with the main memory, for example. , a dedicated external memory access instruction different from general I/O control instructions is provided under an I/O processor controlled by a microprogram, and the central processing unit executes the external memory access instruction. This allows the I/O processor to write a command string (CC) dedicated to the external memory device.
W) ■ is read from a predetermined command area of the main memory.

The I/O processor generates and executes a command from the command word string (CCW), thereby performing a known I/O
A memory transfer method that does not use a transfer protocol allows high-speed data transfer between a main memory device and the semiconductor memory device.

Furthermore, flexible control can be achieved by controlling the external memory device using, for example, a microprogram of an I/O processor.

Therefore, in the configuration of the present invention, the central processing unit issues a specific external memory access command that is a dedicated command to the external memory device, and this command is received by the taken I/O.
The processor issues a command different from normal I/O control commands to the external memory device, and executes this command (read/
Upon receiving the write/sense command), the external memory device performs a data transfer operation, a sense operation, etc., so that the transfer between the I/O processor and the memory control device is
It is possible to use a memory transfer method different from a normal I/O transfer operation (data transfer operation defined by an input/output interface), and there is an effect that the high-speed access performance of the external memory device can be utilized.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, in which (a) shows an example of a system configuration, (b) shows a formant example of an external storage access command, and (c) shows a command word. Column (
CCW), and the external memory device 6 is
The I/O processor 3 is connected to a specific interface of the O processor 3, and the external memory access command (■) is added to the command issued by the central processing unit 1, so that the I/O processor 3 recognizes that the external memory access command (2) has been issued. Then, a command word string (CCW) (2) for accessing the external memory device 6 is read from a specific address in the main storage device 5, and a command word string (CCW) (2) for accessing the external memory device 6 is read from the command word string (CCW) (2) for accessing the external memory device 6. Means for generating a command and accessing the external memory device 6 using the generated command is necessary for carrying out the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, a control method for a storage device according to the present invention will be explained with reference to FIG.

As mentioned above, when a large-capacity external memory device, for example, the semiconductor memory device 6 is connected as an extension of the main memory device,
Since it becomes necessary to increase the number of bits of the address register for the main memory device, in the present invention, the external memory device 6 is provided with a separate address space different from the main memory device 5.

Then, in order to access an address space different from the main memory 5, a dedicated external memory access instruction ((b
) is provided (see figure).

First, the I/O processor 3 receives the specific external storage access command (2) of the present invention issued by the central processing unit 1.

As a result, the I/O processor 3 reads the command word string (CCW) for accessing the external memory device 6 from the predetermined command address area (CAW) of the main memory device 5, and Read command string (
CCW) ■ and generates and outputs read/write commands, etc. for the external memory device 6.

The command word string (CCW) ■ is configured, for example, as shown in FIG. It consists of an address (external memory address), transfer amount (number of words), etc.

By analyzing this command word string (CCW) ■,
The I/O processor 3 autonomously performs the operation of transferring the data indicated by the transfer amount from the address of the external memory device 6 to the address of the main storage device 5 (or vice versa).

At this time, the input/output device (
(10) The same control method as when transferring data from device 7, for example, detecting an empty cycle of the main memory bus to main memory 5 and transferring byte data of the bus width to main memory 5. Repeat the above command string (C
C11) Transfer the amount of data indicated by ■.

When the data transfer is completed, similarly to the channel operation in input/output processing, an end status word is generated and the end status is stored in a predetermined status word area as the external memory device 6. After storing, an end interrupt is issued to the central processing unit 1.

In this way, the present invention provides a large capacity semiconductor memory device.
When the I/O processor connects to a specific interface of the I/O processor and receives a specific external storage access command issued by the central processing unit, the I/O processor performs a predetermined By reading the command string ■ on the main storage device, interpreting the command string ■, and sending a dedicated command to the external memory device, the main memory The feature is that data transfer is performed by stealing bus cycles.

〔Effect of the invention〕

As described above in detail, the storage device control method of the present invention is applicable to a computer system having an I/O processor that controls a plurality of channels, which has an address space different from that of the main storage device, and which has an I/O processor. An external memory device (for example, a semiconductor memory device) different from the O device is connected to the I/O processor and placed under it, and the I/O
By providing an external memory access command different from the I/
The command system ■, which is different from the O control command, allows the I/O
Since the processor controls the external memory device, an I/O device that has an interface with the main memory
The load on the central processing unit is reduced by making effective use of the /O processor for high-speed data transfer and by having the I/O processor with a microprogram perform this memory transfer operation, rather than under direct control of the central processing unit. However, there is an advantage that the external memory can be accessed in a flexible control manner by the microprogram.

In the drawing, l is the central processing unit, 2 is the memory control unit.

3 is an I/O processor.

4 is a channel device (channel).

5 is the main storage device.

6 is an external memory device or a semiconductor memory device.

7 is an I/O device or ■/○ device.

7a is a semiconductor memory device or a semiconductor disk device.

■ is an external memory access command.

■ is a command word string (CCW) or command system.

are shown respectively.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a diagram illustrating a conventional storage device control method. It is.

Claims (2)

[Claims] (1) In a computer system having an I/O processor (3) that controls multiple channels (4), the I/O device (7) has a different address space from the main memory (5) and A different external memory device (6) is connected to the above I.
External memory access instructions different from I/O instructions [(1)] are connected to /O processor (3) and placed under it.
A command system different from I/O control commands [(
2)], the I/O processor (3) controls the external memory device (6). (2) The storage device control method according to claim 1, wherein the I/O processor (3) controls the external memory device (6) by a microprogram.