JPS59200325A - Interruption processing system - Google Patents

Abstract

PURPOSE:To perform interruption processing at a high speed by discriminating previously the mode to an interruption at the processor side before an interruption signal is produced and storing the corresponding address information into a vector table. CONSTITUTION:The mode is discrminated previously to an interruption at the processor side before an interruption signal is produced and the corresponding address information is stored into a vector table. For instance, access processing is given to a disk device 7. In this case, a seek start instruction is delivered to a disk control part 6 from a CPU1 via a common bus 5. Then the mode is discriminated for the processing which should be carried out when an interruption signal is produced from the part 6. Based on the result of this discrimination, the address information of an interruption vector table 3 provided on a memory 4 is rewritten to the address value which indicates the processing to deliver a sector search instruction. Then the part 6 where the seek start instruction is executed produces an interruption signal to execute the interruption processing under the control of an interruption control part 2.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to an interrupt processing method, and particularly relates to an interrupt processing method in which a single interrupt has a plurality of modes, and processing is performed according to each mode. .

(b) Technical Background In a data processing system that includes a processing device and a plurality of lower-level devices (for example, input/output devices).

It is configured to issue processing requests to the processing device, processing completion notifications, etc. in the form of interrupts from lower-level devices. Furthermore, processing for interrupts from lower-level devices is further divided into stages (modes) in order to improve the efficiency of time-sharing processing by the processing device.

(C) Conventional technology and problems As a configuration on the side of a processing device that conventionally performs one-interrupt processing.

For example, as shown in FIG. 1, an interrupt control unit (PIC) 2 is provided that determines the type of interrupt signal supplied to a processing unit (hereinafter referred to as CPU) l. The interrupt control unit 2 determines the type of interrupt signal (for example, the type of lower-level device that generated the interrupt)
, and instructs the CPUI to perform an interrupt process.

FIG. 2 shows an interrupt vector table for instructing the CPUI to perform interrupt processing. Lid table 3 to this interrupt
There is a storage section Vec O,- according to the type of interrupt signal.
Vec n is provided.

And in each storage unit Vec O to Vec n.

Address information that instructs the CPUI to perform interrupt processing is stored.

Therefore, if an interrupt to the CPU occurs, the third
As shown in the flowchart in the figure, first, the interrupt control unit 2 outputs an interrupt request IRQ to the CPUI. A response IACK from the CPUI is returned in response to this request IRQ. Then, the interrupt control section 2 outputs a vector address VA indicating one storage section Veci on the lid table 3 to the interrupt corresponding to the two generated interrupts. This allows the CPU
I reads the address information stored in the storage section Vec i on the table 3 indicated by the vector address VA.

As a result, the interrupt processing program on the memory indicated by the read address information is read and executed.

However, as described above, when multiple processing modes exist for one interrupt, in the interrupt processing flow described above, the CPU It was configured to perform mode discrimination and proceed to a processing routine according to the result of the 5 discriminations. As a result, mode determination is repeated each time for the same interrupt, which is not desirable in terms of efficiency of CPUI interrupt processing.

(d) Purpose of the invention The present invention aims to eliminate the above-mentioned conventional disadvantages.

It is an object of the present invention to provide an interrupt processing method capable of speeding up interrupt processing by a processing device.

(el Structure of the invention In order to achieve the above object, one aspect of the present invention is as follows.

Before an interrupt signal is issued using the time spent waiting for an interrupt from a lower-level device, the processing device side determines the mode for that interrupt in advance, and the address indicates the interrupt processing according to the determined mode. The information is stored in a hector table.

Hereinafter, the present invention will be explained in detail using Examples.

(fl Embodiment of the Invention FIG. 4 is a diagram showing an embodiment of a system to which the interrupt processing method of the present invention is applied, and FIG. 5 is a flowchart showing the operation of the embodiment.

In FIG. 4, the same parts as in FIGS. 1 and 2 are designated by the same reference numerals, and 4 is a main memory, 5 is a common lot, 6 is a disk control unit, and 7 is a magnetic disk device.

In this embodiment, the CPUI interrupt processing operation in response to an interrupt from the disk control unit 6 is shown.

That is, as an access operation from the CPU to the disk device 7.

■ Issue a seek start command.

■ Issue a sector search command.

■ Issue read/write commands.

A process is performed to issue each of these to the disk control unit 6.

On the other hand, the disk control unit 6 executes each of the above-mentioned commands from the CPU.
It is configured to issue an interrupt signal int to the CPUI each time the processing for ~■ is completed. The interrupt type of this interrupt signal int is determined by the 2-interrupt control unit 2, and the address information storage unit V on the 9-interrupt vector table 3
ecQ.

As described above, the process to be executed by the CPUI is determined by the information of Vecl, -.

Conventionally, a storage section on the table 3 (for example, VecO
) The mode of the two interrupt signals was determined in the interrupt processing routine stored at the address location on the main memory 4 indicated by . That is, in this case.

It is determined during the interrupt processing which processing mode among the above-mentioned (1) to (4) the interrupt from the channel control unit 6 is made. In other words, the next process for the 2nd interrupt is determined in the 2nd interrupt processing routine.

A jump is made again to the processing routine corresponding to each process. As a result, mote determination is repeated every time an interrupt from the disk control unit 6 occurs, resulting in a delay in processing. In this example,
As shown in the flowchart of FIG. 5, the CPU 1 determines the mode for the interrupt in advance.

this is.

This method focuses on the fact that the processing for the disk control unit 6 is predetermined, and the processing mode for the occurrence of the 9th interrupt is uniquely determined. The operation of this embodiment will be explained below based on the flowchart shown in FIG.

When it becomes necessary to perform an access process to the disk device 7, the CPU first issues a seek activation command to the disk control unit 6 via the common bus 5 in accordance with the processing steps ① to ② above. After issuing the seek activation command, the CPUI determines the mode. That is.

When an interrupt signal int is generated from the disk control unit 6, the processing mode to be performed next is determined. In this case, the above ■
This process performs the following processing. Based on this determination result, CPU
rewrites the address information in the corresponding storage section (in this case, ■eco) of the interrupt vector table 3 provided on the memory 4 to an address value that instructs the process of issuing the sector search command in (■) above. In addition, each storage unit VecQ, V of table 3
ec1. − is set depending on the type of interrupt (type of input/output device that issued the interrupt). Therefore, it goes without saying that the same vector address is issued from the two interrupt control sections 2 for interrupt signals from the same device.

After rewriting the address of the storage unit VecO, epul
enters a state in which it waits for an interrupt from the disk control unit 6 or another input/output device (not shown). Thereafter, the disk control unit 6 that has completed the execution of the seek start command outputs an interrupt signal int. Then the CPUI.

Storage area on table 3 indicated by vector address VA given by interrupt control unit 2 (in this case ■eCO)
See. As a result, the process at the address indicated by the storage unit VecO is executed. That is, the CPUI can immediately perform the process (2) above and issue a sector search command to the two-disk control unit 6. As mentioned above, according to the two-line implementation sequence, 1
By using the time in the interrupt waiting state, it is possible to take a break in advance in processing for each mode in response to interrupts from input/output devices. As a result, it is possible to save time for mode determination processing, which conventionally would be redundantly performed after an interrupt occurs.

It is possible to speed up interrupt processing.

(6) Effects of the Invention As detailed above, according to the present invention, the time required for interrupt processing by the processing device can be shortened, and the processing efficiency of the entire system can be improved.

[Brief explanation of drawings]

1 to 3 are diagrams explaining conventionally used interrupt processing operations, FIG. 4 is a diagram showing an embodiment of a system to which the present invention is applicable, and FIG. 5 is a diagram illustrating an embodiment of the system shown in FIG. It is a flowchart showing the operation. 1 is a CPU (processing unit), 2 is an interrupt control section, 3 is an interrupt vector table, and 6 is a disk control section. Figure 1 Figure 2 Figure 3 ■ Figure 4 Figure 5

Claims (1)

[Scope of Claims] The processing device includes a processing device and a storage section in which instruction information instructing interrupt processing in response to an interrupt signal supplied to the processing device is stored, and the processing device An interrupt processing system that executes an interrupt process indicated by the instruction information by referring to the information, and also includes a plurality of processing modes for the interrupt signal and executes the interrupt process according to the processing mode. In. The processing device is configured to determine a processing mode of one interrupt signal before the interrupt signal is supplied. An interrupt processing method, characterized in that instruction information indicating interrupt processing according to the determined processing mode is stored in the storage section.