JPS6095671A - Common bus buffer controlling system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention provides a common bus/buffer control system that reduces response waiting time for input/output commands by preferentially reading response data for input/output commands from a buffer. It is related to the method.

[Conventional technology and problems]

Figure 1 shows a system in which a data processing device and multiple adapters are connected via a common bus using a synchronous split method.
It is a figure which shows an example. In Figure 1, 1 is a common bus, 2
is the main memory, 3 is the data processing device, 4 is the buffer, 5-1
and 5-2 indicate adapters, respectively. Further, in FIG. 1, dotted lines indicate the flow of data during cycle steal transfer, and dashed-dotted lines indicate the flow of data during data transfer by the 10th instruction.

In a system like the one shown in Figure 1, data transfer is
This is done by executing a 0 instruction or a cycle steal.

The buffer 4 temporarily stores data that is continuously sent from a plurality of adapters. I1 from the data processing device 3 to the adapter 5-i (i = 1.2)
When executing 0 instructions, an increase in the waiting time for a response from the adapter 5-i leads to a reduction in the instruction processing capacity of the data processing device.

[Purpose of the invention]

The present invention is based on the above considerations, and aims to provide a common bus buffer control method that can reduce the response waiting time of input/output commands in order to prevent the performance of a data processing device from decreasing. There is.

[Structure of the invention]

Therefore, the common bus buffer control method of the present invention transfers data to and from other devices by executing input/output commands and cycle steals via a common bus controlled by a synchronous split method. In a data processing device that has a buffer consisting of a plurality of buffer units that temporarily stores response data and cycle steal data for an input/output command that is sent from another device, the data sent from another device is The input/output command response identification circuit includes an input/output command response identification circuit that identifies data, and an address register that holds the address of a buffer in which response data of the input/output command is stored. The present invention is characterized in that when it is detected that the input/output command is data, the response data of the input/output command is preferentially read out from the buffer using the contents of the address register.

[Embodiments of the invention]

The present invention will be described below with reference to seven drawings. FIG. 2 is a block diagram of one embodiment of the present invention, and FIG. 3 is a diagram explaining the operation of the embodiment of FIG.

In FIG. 2, 6 is an I10 command response identification circuit, 7 is a write address register, 8 is a +1 circuit, 9 is a write address holding register, 10 is a read address register, 11
12 is a read address holding register, 13 is a comparison circuit, and G is a gate. Note that the same reference numerals as in FIG. 1 indicate the same parts.

The buffer 4 has a plurality of buffer units, and each of the plurality of buffer units has an address of 0°1, 2.3.
... has been assigned. The I10 response identification circuit 6 identifies whether the data sent from the adapter is for an I10 command or a cycle steal. Note that a header is added to the beginning of the data sent from the adapter, which includes the size information of the data and identification information indicating whether the data is cycle-scale or for an I10 instruction. There is. The write address register 7 indicates the buffer unit in which data is to be written, and its value is incremented by +1 by the +1 circuit 8 every write cycle. In the write address holding register 9, the I10 command response identification circuit 6
When the command response data is detected, the value of write address register 7 is set. When data transfer from the buffer 4 to the data processing device 3 becomes possible, the read address -
The value of 1/register 10 is transferred to read address holding register 12, and then the contents of write address holding register 9 are transferred to read address register 10, and the data of the corresponding buffer unit is read.

Thereafter, the value of read address holding register 12 is transferred to read address register 10vc. From this point on, the contents of the read address register 10 will be as follows for each read cycle:
+1 will be given. However, when the comparison circuit 13 outputs a match, the signal RIN'H is turned on, and data reading from the buffer 4 is prohibited. Note that the comparison circuit 13
After the response data of the 10th instruction is read from the buffer, it enters an operating state, and the value of the write address holding register 9 is compared with the value of the read address φ register 10.

FIG. 3 is a diagram illustrating the operation of the embodiment of FIG. 2. In the illustrated example, first, the cycle steal data CYS
TL-A is written to address 0 of buffer 4, cycle-steal music data CYSTL-B is written to address 1, response data for the I10 command is written to address 2, and address 2 is written at the same time. Cycle steal data CYSTL held in address holding register 9
-C is written to address 3. From buffer 4, the response data of the I10 instruction written at address 2 is first read out, then the cycle steal data CYSTL-A at address O is read out, and then the cycle steal fist data CYSTL at address 1 is read out. -B is read out, and then the value of the read address register 10 becomes 2'', but in this case, the signal RINH is turned on, so no data is read out from the buffer 4, and then the steal data C at address 3 is read out.
YSTL-C is read.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, I1
Since the response data of the 0 command is read from the buffer with priority, the response waiting time of the input/output command can be reduced, and an improvement in the processing performance of the data processing device can be expected.

[Brief explanation of the drawing]

Figure 1 shows a system in which a data processing device and multiple adapters are connected via a common bus using a synchronous split method.
Figure 2 is a block diagram of an embodiment of the present invention;
FIG. 3 is a diagram illustrating the operation of the embodiment of FIG. 2. DESCRIPTION OF SYMBOLS 1... Common bus, 2... Main memory, 3... Data processing device, 4... Buffer, 5-1 and 5-2... Adapter, 6... I10 command response identification circuit, 7...Write address φ register, 8...+1 circuit, 9...Write address holding register, 10...Read address register, 11...+1 circuit, 12...Read address holding Regisf, 13...Comparison circuit, G...Gate. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Kyotani 4 parts Ya 1 drawing MS, DPLj henna 3 drawings

Claims (1)

[Claims] Through a common bus controlled by the synchronous split method, data is transferred with other devices by executing input/output commands and cycle steals, and response data and cycle number steals of input/output commands sent from other devices are transferred. I/O command response identification for identifying that data sent from another device is response data to an I/O command in a data processing device that has a buffer consisting of multiple buffer units for temporarily storing data. The circuit is equipped with an address register that holds the address of a buffer in which response data of an input/output command is stored, and when the input/output command response identification circuit detects that the response data is the response data of an input/output command, the address register is provided. A common bus/buffer control system characterized in that response data for an input/output command is preferentially read from the buffer using the contents of a phrase register.