JPH01136238A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To utilize an external instruction memory large in capacity by providing at least two kinds of gate circuits which receive the address output of arithmetic control part and the output of a write control signal as input signals, and a counter circuit which receives the output of the gate circuits as a clock and a clear signal. CONSTITUTION:The arithmetic control part 1 drives the clock input terminal 32 or the clear terminal 31 of the counter circuit 3 by performing a write operation on an address set in advance. And a numeric value appearing at the output 35 of the counter circuit 3 is increased one by one by driving the clock input terminal 32. Also, the output 35 is set at '0' by driving the clear terminal 31. And to the address input 41 of an instruction memory 2, the address output 21 of the arithmetic control part 1 is connected as a first address, and the output 35 of the counter circuit 3 as a second address, and an instruction on the instruction memory 2 is designated by the sum of the first and second addresses.

Description

[Detailed description of the invention] (7 is the field of commercial use) The present invention relates to an arithmetic device.

(Prior Art) Conventionally, there have been arithmetic devices using one-chip microprocessors, one-chip signal processors, and the like. Generally, this type of arithmetic device has an internal instruction memory inside a processor chip, and performs arithmetic processing by interpreting and executing a sequence of instructions stored therein. However, there is a limit to the capacity of the internal instruction memory due to restrictions on the number of elements that can be integrated. In order to alleviate this constraint, there is an arithmetic device having a configuration in which an instruction memory is provided externally and instructions on the external instruction memory can be executed using addresses output from the processor chip.

For example, Nishitani et al. developed the ``Advanced Single Chip Signal Processor''('Advanced Sing
le-chip Signal Processor'
) is described in the ICASSP 1986 Lecture Preliminary Lecture Collection.

(Problems to be Solved by the Invention) In the conventional arithmetic unit described above, by using an external instruction memory installed outside, it is possible to alleviate the restriction on the capacity of instruction strings that can be loaded inside the processor chip. However, the above 1
In chip microprocessors and single-chip signal processors, many functions, mainly external input/output, are integrated into one LS.
Register in I package. For this reason, many of the external connection pins of the package are assigned to input/output pins, and it is often difficult to allocate many connection pins to address signal lines for specifying instruction locations on the external instruction memory. Therefore, even when an external instruction memory is connected, the capacity of the instruction string is reduced to f! On the other hand, there was a problem in that it was difficult to increase the size.

An object of the present invention is to provide an arithmetic device that solves these problems.

(Means for Solving the Problems) Means provided by the present invention to solve the above-mentioned problems includes an instruction memory for recording calculation processing procedures for performing calculations using numerical data, and an instruction memory for storing calculation processing procedures for performing calculations using numerical data. and an arithmetic control unit that executes arithmetic processing according to the arithmetic processing procedure read from the instruction memory, the operation of the arithmetic control unit being controlled according to the instruction sequence on the instruction memory, an instruction bus that transfers an instruction sequence to the arithmetic control unit;
an address bus that transfers address information of an instruction to be executed by the arithmetic control unit from the arithmetic control unit to the instruction bus; and at least two types that receive address outputs and write control signal outputs of the arithmetic control unit as input signals. a gate circuit, a counter circuit that receives the output of the gate circuit as a clock and a clear signal, an address memory that receives the output of the counter circuit as a read address, and an address output that is output from the arithmetic control section to the address bus. It is characterized by comprising means for generating a read address of the instruction memory from an output of the address memory.

(Example) Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. , which shows an arithmetic device in which the operation of the arithmetic control unit is controlled according to the instruction string on the instruction memory, the arithmetic control unit 1 is similar to the one in the prior art.
In the arithmetic device of this embodiment, the arithmetic control unit 1 and the instruction memory 2 are connected to the instruction bus 50, and the instruction memory 2 corresponds to the external instruction memory. connected by. The instruction string in the instruction memory 2 output from the instruction output 40 passes through the instruction bus 50 and is transferred from the instruction input terminal 20 to the arithmetic control section 1. At this time, the instruction to be executed on the instruction memory 2 is specified by the value of the address input 41,
When the readout control terminal 42 is selected, the signal is output to the arithmetic control section 1.

In the device of this embodiment, the address output 21 of the arithmetic control section 1
Gate circuits 10 and 11 are connected to the write control signal output 23 and the outputs of the gate circuits 10 and 11 are connected to the counter circuit 3. Furthermore, the output of the counter circuit 3 is connected to the address memory 4. According to the configuration shown in FIG. 31 can be driven. By driving the tarock input terminal 32, the numerical value appearing at the output 35 of the counter circuit 3 can be increased one by one. Further, by driving the clear terminal 31, the output 35 can be set to 0. The contents of the address memory 4 read out every time the output value of the counter circuit 3 changes are updated by writing in advance a sequence of execution start addresses of the instruction memory required in the address memory 4. Can be done.

On the other hand, the address input 41 of the instruction memory 2 is connected to the address output 21 of the arithmetic control unit 1 as the first and the output 35 of the counter circuit 3 as the second, and the address input 41 of the instruction memory 2 is connected to command is specified. According to the configuration shown in the figure, even if the number of bits of the address output 21 of the arithmetic control unit 1 is small and the usable range of the instruction memory 2 is limited in the conventional method, the bit number of the output 35 of the counter circuit 3 is small. By increasing the number, a larger capacity of the instruction memory 2 can be used as a whole. Furthermore, since the execution start instruction address to be written into the address memory 4 can be freely specified, there is a great advantage that an arbitrary area of the instruction memory 2 can be specified by changing the output of the counter circuit 3 one by one.

In the arithmetic device of this embodiment, the sequence of instructions to be executed continuously is specified by changing the address output 21 of the arithmetic control unit 1, and output is performed to the pre-specified address each time the type of processing is changed, etc. By doing this, the clock 32 of the counter circuit 3 is driven, and the counter circuit 3
Update the output 35 of . By connecting the output 36 of the address memory 4 to the upper bit side of the address input 41 of the instruction memory 2, the designated address of the instruction memory 2 can be arbitrarily changed by clock driving operation for the counter 3. It also has the great advantage that the operations required for the address change operation are simple and that only two words of the area of the instruction memory 2 are rendered unusable. If the designated addresses are to be sequentially switched and returned to the initial state due to a change in processing, the clear manual power 31 of the counter circuit 3 may be driven.

As an example, consider a case where the number of bits of the address output 21 of the arithmetic control section 1 is 10, the number of bits of the output 35 of the counter circuit 3 is 6, and the number of output bits of the address memory 4 is 6. In this case, if only the address output of the arithmetic control unit 1 is used, it is only possible to use an instruction string of 1024 words. However, according to the configuration of this embodiment, an additional 64 areas can be designated by the output of the counter circuit 3. Therefore, it is possible to use a large instruction sequence of 64 words in total. Further, according to the configuration of the embodiment shown in FIG. 1, it is possible to use a continuous area of 1024 words out of the 64 word instruction memory in any order. is 1024 words, but it can be used by dividing the processing of a group into 1024 words or less. Furthermore, when changing the area designation address in the instruction memory 2, it is only possible to change it in the order in which they are stored in the address memory 4.

To randomly specify an area, first press the clear terminal 31.
The procedure is somewhat complicated, as it is necessary to drive the clock terminal 32 multiple times until the output 35 of the counter circuit 3 reaches the specified value. In many application examples, a group of multiple processes is executed sequentially from the first step, and
When the process after & is completed, the process returns to the first step and the above steps are repeated. This process can be easily handled by the configuration shown in the figure.

FIG. 2 is a block diagram showing a second embodiment of the invention. A count-up manual power 32 and a count-down manual power 33 are prepared as clock manual power for changing the output 35 of the counter 1iI83. According to this configuration, it is easy to switch instruction addresses stored adjacently in the address memory.

FIG. 3 is a block diagram showing a third embodiment of the present invention. In this embodiment, the address output 21 of the arithmetic control section 1 and the output 36 of the address memory 4 are connected to the input of the adder 5. This is an example in which the addition result is the address 41 of the instruction memory 2. In the embodiment shown in FIG. 1, the arithmetic control section address output 21 is simply connected to the lower bits of the address input 41 of the instruction memory 2, and the address memory output 36 is simply connected to the upper bits.
Only addresses that are an integral multiple of the area defined by the width of the lower bits can be specified. Therefore, in the first embodiment, the execution start address that can be specified by the address memory 4 is limited to an integral multiple of 1024 words. Therefore, if the size of the sequence of instructions to be executed continuously is small, the efficiency of use of the memory 4 for one instruction may decrease.

On the other hand, in the embodiment shown in FIG. 3, by setting the output address bit width of the address memory 4 to be equal to the input address bit width of the instruction memory 2, all of the information on the instruction memory 2 can be It becomes possible to specify the address as the execution start address. - For example, the number of bits of the address output 21 of the arithmetic control unit 1 is 10, the number of bits of the output 35 of the counter circuit 3 is 6, the number of output bits of the address memory is 16, and the number of address input bits of the instruction memory 2 is 16. Consider the case where . At this time, a large area of 64 words can be used as the instruction memory 2, and the execution start address can be set in units of one word. In addition, since the number of output address bits of the arithmetic control unit 1 is 10, the instruction string that can be specified consecutively is 1024 words, and since the number of bits of the output 35 of the counter circuit is 6, the execution can be switched. There are 64 starting address sets. That is, according to the configuration of this embodiment, 64 words of up to 1024 words
A set of instruction sequences can be placed at any address in units of one word out of 64 words, and executed in a prespecified order. At this time, the address output prepared by the arithmetic control section 1 may be 10 bits.

The above embodiments have described a device in which the address output 21 and write control signal output 23 of the arithmetic control section 1 are connected to the gate circuits 10, 11, and 12 to increase, decrease, or clear the output value of the counter circuit 3. If it is not preferable to use two or three addresses for selecting the two or three types of gate circuits, the output data path of the arithmetic control unit 1 is further added to the input of the gate circuit and output to one address. The gate circuit can also be selected by changing the data. As mentioned above, it is clear that the configuration can be changed without departing from the spirit of the present invention. Detailed explanation will be omitted.

(Effects of the Invention) According to the present invention, an arithmetic unit that can utilize a large instruction memory even for a processor with a limited capacity of external instruction memory that can be accessed can be obtained. The operation required to change an address that exceeds the available memory capacity is simple because it is just a write operation to a fixed address, and the advantage is that only 2 to 3 words of the area in the instruction memory become unusable due to this. be. Another advantage is that by increasing the number of bits of the added counter circuit, there is no restriction on increasing the capacity of the instruction memory. Furthermore, since the address of the external instruction memory is determined by the contents of the address memory, it is possible to execute the instruction at any address in the external instruction memory even if the output value of the counter circuit only increases by 1. There is a big advantage to having one.

According to the present invention described above, an arithmetic device that solves the above-mentioned conventional problems can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a block diagram showing a second embodiment of the invention, and FIG. 3 is a block diagram showing a third embodiment of the invention. In the figure, 1 is an arithmetic control unit, 2 is an instruction memory, 3 is a counter circuit, 4 is an address memory, 1o, ii. 12 is a gate circuit, 50 is an instruction bus, and 51 is an address bus.

Claims (1)

[Claims] It has an instruction memory that records calculation processing procedures for performing calculations using numerical data, and an arithmetic control unit that executes arithmetic processing using the calculation processing procedures read from this instruction memory. In an arithmetic device in which the operation of the arithmetic control section is controlled according to a sequence of instructions, an instruction bus for transferring the instruction sequence in the instruction memory to the arithmetic control section and address information of an instruction to be executed by the arithmetic control section are provided. an address bus for transferring data from the arithmetic control section to the instruction bus; at least two types of gate circuits that receive address outputs and write control signal outputs of the arithmetic control section as input signals; and clock and clear outputs of the gate circuits. a counter circuit that receives the signal as a signal; an address memory that receives the output of the counter circuit as a read address;
An arithmetic device comprising means for generating a read address of the instruction memory from an address output output from the arithmetic control unit to the address bus and an output of the address memory.