JPH04360251A - Computer system - Google Patents

Abstract

PURPOSE:To read out data only within the original data reading time of a main memory even when a cache memory generates a miss. CONSTITUTION:When an MPU 1 generates a data reading request, data concerned are immediately read out from the main memory 2, and if the data are not stored in the cache memory 3, the data read out from the main memory 2 are inputted to the MPU 1. When the data are stored in the memory 3, the stored data are read out from the memory 3 and inputted to the MPU 1. Thereby when data corresponding to a data reading request generated from the MPU 1 are not stored in the cache memory 3, data read out from the main memory 2 are immediately inputted to the MPU 1.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a computer system,
More particularly, it relates to computer systems with cache memory.

0002

2. Description of the Related Art FIG. 6 is a block diagram showing an example of a conventional general configuration of a computer system equipped with a cache memory.

In FIG. 6, reference numeral 1 denotes a microprocessing unit (hereinafter referred to as M
(referred to as PU), and 2 is the main memory. The two are connected by an address bus 7 and a data bus 8.

Reference numeral 3 is a cache memory to which the above-mentioned address bus 7 and data bus 8 are connected. Although the cache memory 3 has a smaller capacity than the main memory 2, it operates at high speed, and is capable of holding a portion of the data stored in the main memory 2. A cache read start signal 9 is applied to the cache memory 3 from the MPU 1.

When the cache memory 3 holds data to be read by the MPU 1, this is called a cache hit, and the cache memory 3 outputs (makes active) a hit signal 13, thereby holding the data to be read by the MPU 1. If not, this is called a cache miss and the hit signal 13 is not output (does not become active). The hit signal 13 is given to the sequencer 4 and the read completion signal generator 5.

The sequencer 4 functions as a control circuit, and the sequencer 4 functions as a control circuit.
When PU1 reads data, cache memory 3
It does not operate when the hit signal 13 is given from the MPU 1, and when the hit signal 13 is not given, a signal similar to the signal output from the MPU 1 when reading data, that is, the main memory read start signal 10 is sent to the main memory. Output to 2. Further, when the hit signal 13 is given, the read completion signal generator 5 outputs the cache read completion signal 11 to the MPU 1 upon completion of reading data from the cache memory 3, and when the hit signal 13 is not given. In this case, when the main memory read completion signal 12 is given from the main memory 2, the cache read completion signal 11 is output to the MPU 1.

Note that a cache system 6 is composed of a cache memory 3, a sequencer 4, and a read completion signal generator 5.

FIGS. 7 and 8 are timing charts showing the operating state of such a conventional computer system.

[0009] Here, the data read operation by the MPU 1 requires a minimum of two cycles, and can be extended by one cycle if necessary. Further, the data read operation by the cache memory 3 requires a total of two cycles: one cycle for the hit/miss determination operation and one cycle for the subsequent data read operation. Furthermore, it is assumed that reading data from the main memory 2 requires three cycles.

First, the operation when the cache memory 3 is hit will be explained with reference to the timing chart shown in FIG.

In cycle S1, the MPU 1 outputs the address of data to be read to the address bus 7, and also sends a cache read start signal 9 to the cache memory 3.
By outputting , the data reading operation by the MPU 1 is started, as shown in FIG. 7(a).

As shown in FIG. 7(b), when the cache read start signal 9 is applied, the cache memory 3 reads the address output to the address bus 7 and holds the corresponding data. 2. In other words, a hit/miss determination operation is started. As a result of the determination operation in cycle S1, if the cache memory 3 holds data at the address, it determines that it is a hit and outputs a hit signal 13, and also outputs the data to the data bus 8 in cycle S2. .

The MPU 1 reads data output from the cache memory 3 to the data bus 8. The read completion signal generator 5 receives the hit signal 13 output from the cache memory 3 and outputs the cache read completion signal 11 to the MPU 1 in cycle S2. As described above, data reading by the MPU 1 is completed within cycle S2.

Note that when the hit signal 13 is output from the cache memory 3, the sequencer 4 does not operate;
Therefore, as shown in FIG. 7(c), the main memory 2 does not operate.

Next, the operation when the cache memory 3 misses will be explained with reference to the timing chart of FIG.

The fact that the MPU 1 starts the read operation in cycle S1 is the same as in the case of a hit described above, as shown in FIG. 8(a), and the cache memory 3 accordingly The determination operation is also performed in the same manner as shown in FIG. 8(b).

However, the cache memory 3
Since a mistake is determined in step 2, the hit signal 13 is not output. In this case, the sequencer 4 outputs the main memory read start signal 10 to the main memory 2 from cycle S2.

When the main memory 2 receives the main memory read start signal 10 output from the sequencer 4,
), the data read operation starts from cycle S2. That is, the main memory 2 reads the address output to the address bus 7 and outputs the corresponding data to the data bus 8 in cycle S4, and also outputs the main memory read completion signal 12 to the read completion signal generator 5. do.

The MPU 1 reads data output from the main memory 2 to the data bus 8. In addition, the read completion signal generator 5
Since the hit signal 13 was not output from the cache memory 3, the cache read completion signal 11 was output when the main memory read completion signal 12 was output from the main memory 2.
is output to MPU1. As described above, data reading by the MPU 1 is completed within cycle S4.

[0020]

[Problem to be Solved by the Invention] In conventional computer systems that operate as described above, if the cache memory does not hold data at the relevant address, that is, if there is a miss, a mistake is determined. Afterwards, data reading from the main memory begins. Therefore, even though reading data from the main memory itself can be done in three cycles, a total of four cycles are required from the time when the MPU starts the data reading operation.

The present invention has been made in view of the above circumstances, and aims to provide a computer system that can read data using only the data read time originally provided by the main memory even if the cache memory misses. do.

[0022]

[Means for solving the problems] The first invention of the present invention is
When the data processing means issues a data read request, the data is immediately read from the main memory, and if the data is not held in the cache memory, the data read from the main memory is read into the data processing means. ,
If the data is held in the cache memory, it is read from the cache memory and read into the data processing means.

A second aspect of the present invention also provides a control circuit for controlling such that when the data processing means issues a data read request, the data is immediately read from the main memory; and means for interrupting transmission of data read from the main memory to the data processing means when the data is held in the main memory.

Furthermore, the third aspect of the present invention is that when the data processing means issues a read request for data to be processed in a state where reading of data from the main memory has been completed, the data processing means immediately requests the main memory to read the data to be processed. read the data,
If the data processing means issues a read request for the data to be processed in a state where reading of data from the main memory has not been completed, if the data is held in the cache memory, no control is performed on the main memory; A control circuit that causes the main memory to read the data when the data processing means completes reading the data if the data is not held in the cache memory; and means for interrupting transmission of data read from the memory to the data processing means.

[0025]

[Operation] In the first and second aspects of the present invention, when the data processing means issues a data read request, if the data is not held in the cache memory, the data read from the main memory is immediately converted into a data read request. It is read into the processing means.

Further, in the third aspect of the present invention, when the data processing means issues a data read request in a state where the main memory has not completed reading the previous data, the data must be held in the cache memory. For example, the next data read starts immediately after the previous data read from the main memory is completed.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the configuration of a computer system according to the present invention. Note that in FIG. 1, the same reference numerals as in FIG. 6 referred to in the description of the conventional example described above indicate the same or corresponding parts.

In FIG. 1, reference numeral 1 denotes a microprocessing unit (hereinafter referred to as M
(referred to as PU), and 2 is the main memory. An address bus 7 connects the MPU 1 and the main memory 2. Further, data is transferred from the main memory 2 to the MPU 1 via a buffer 14,
The main memory 2 and the buffer 14 are connected by a local data bus 8b, and the buffer 14 and the MPU 1 are connected by a system data bus 8a.

When the buffer 14 receives a hit signal 13 output from the cache memory 3, which will be described later, the buffer 14 connects the local data bus 8b and the system data bus 8a.
If the hit signal 13 is not applied, the local data bus 8b and the system data bus 8a are connected.

Reference numeral 3 is a cache memory to which the above-mentioned address bus 7 and system data bus 8a are connected. Although the cache memory 3 has a smaller capacity than the main memory 2, it operates at high speed, and is capable of holding a portion of the data stored in the main memory 2. A cache read start signal 9 is applied to the cache memory 3 from the MPU 1. Note that this cache read start signal 9 is also given to a sequencer 4, which will be described later.

When the cache memory 3 holds the data to be read by the MPU 1, this is called a cache hit, and the cache memory 3 outputs (makes active) the hit signal 13, thereby holding the data to be read by the MPU 1. If not, this is called a cache miss and the hit signal 13 is not output (does not become active). The hit signal 13 is applied to the buffer 14 and read completion signal generator 5 mentioned above.

The read completion signal generator 5 generates a hit signal 1
3 is given, the cache read completion signal 11 is generated upon completion of reading data from the cache memory 3.
is output to the MPU 1, and if the hit signal 13 is not given, the main memory read completion signal 12 is output from the main memory 2.
At the time when is output, a read completion signal 11 is output to the MPU 1. Note that the main memory read completion signal 12 is also given to the sequencer 4.

The sequencer 4 functions as a control circuit, and the sequencer 4 functions as a control circuit.
When the PU 1 receives the cache read start signal 9 output when reading data, it outputs a signal similar to the signal output from the MPU 1 when reading data, that is, a main memory read start signal 10 to the main memory 2. . however,
Even when the cache read start signal 9 is applied, the sequencer 4 temporarily outputs the main memory read completion signal 12 from the main memory 2 in response to the previously applied cache read start signal 9. It waits for the main memory read start signal 10 to be output, and outputs the main memory read start signal 10 after the main memory read completion signal 12 is output from the main memory 2.

Note that a cache system 6 is composed of the cache memory 3, the sequencer 4, and the read completion signal generator 5.

FIGS. 2, 3, and 4 are timing charts showing the operating state of the computer system of the present invention having such a configuration.

Note that the data read operation by the MPU 1 requires at least two cycles, and can be extended by one cycle if necessary. Further, the data read operation by the cache memory 3 requires a total of two cycles: one cycle for the hit/miss determination operation and one cycle for the subsequent data read operation. Furthermore, it is assumed that reading data from the main memory 2 requires three cycles.

First, the operation when the cache memory 3 is hit will be explained with reference to the timing chart of FIG.

In cycle S1, the MPU 1 outputs the address of data to be read to the address bus 7, and also sends a cache read start signal 9 to the cache memory 3.
By outputting , the data reading operation by the MPU 1 is started, as shown in FIG. 2(a).

As shown in FIG. 2(b), when the cache read start signal 9 is applied, the cache memory 3 reads the address output to the address bus 7 and holds the corresponding data. 2. In other words, a hit/miss determination operation is started.

Furthermore, since the cache read start signal 9 outputted from the MPU 1 is also given to the sequencer 4,
Sequencer 4 outputs main memory read start signal 10 to main memory 2 . As a result, the main memory 2 starts a data read operation in cycle S1, as shown in FIG. 2(c).

As a result of the judgment operation in cycle S1, if the cache memory 3 holds the data at the address, it judges it as a hit and outputs the hit signal 13, and in cycle S2, the cache memory 3 transfers the data to the system data bus 8a. Output to. When the hit signal 13 is output from the cache memory 3, the buffer 14 cuts off the connection between the local data bus 8b and the system data bus 8a.

MPU 1 reads data output from cache memory 3 to system data bus 8a. Read completion signal generator 5 receives hit signal 13 output from cache memory 3 in cycle S2 and outputs cache read completion signal 11 to MPU 1. As described above, data reading by the MPU 1 is completed within cycle S2.

Note that by outputting the main memory read start signal 10 from the sequencer 4 to the main memory 2, the main memory 2 also starts the data read operation from cycle S1, and reads the data in three predetermined cycles up to cycle S3. Read operation is performed. Therefore, in cycle S3, the main memory 2 outputs the data to the local data bus 8b and also outputs the main memory read completion signal 12. However, the buffer 14 receives the hit signal 1 from the cache memory 3.
3 is given, the local data bus 8b
Since the connection between the main memory 2 and the system data bus 8a is cut off, data output from the main memory 2 to the local data bus 8b is not input to the MPU 1. Also,
The read completion signal generator 5 ignores the main memory read completion signal 12 output from the main memory 2.

Next, the operation when the cache memory 3 misses will be explained with reference to the timing chart of FIG.

The fact that the MPU 1 starts the read operation in cycle S1 is similar to the case where the cache memory 3 is hit, as shown in FIG. Similarly, as shown in FIG. 3(b), performs a hit/miss determination operation. Furthermore, the cache read start signal 9 output from the MPU 1 is also given to the sequencer 4,
This also causes the sequencer 4 to output the main memory read start signal 10 to the main memory 2.

However, the cache memory 3
Since a mistake is determined in step 2, the hit signal 13 is not output.

Regardless of the hit/miss determination result in the cache memory 3, when the main memory 2 receives the main memory read start signal 10 output from the sequencer 4, the main memory 2 performs the process as shown in FIG. 3(c). As shown, the data read operation starts from cycle S1. That is, in cycle S1, the main memory 2 reads the address output to the address bus 7, and in cycle S3, outputs the data to the local data bus 8b, and also outputs the main memory read completion signal 12 to the read completion signal generator 5 and Output to sequencer 4.

In this case, the buffer 14 receives the hit signal 13
local data bus 8b is not given.
and the system data bus 8a, the data output from the main memory 2 to the local data bus 8b is transferred via the buffer 14 and the system data bus 8a.
Read into PU1.

Furthermore, the main memory read completion signal 12 is output from the main memory 2 in cycle S3, but since the hit signal 13 is not given to the read completion signal generator 5, the read completion signal generator 5 outputs the main memory read completion signal 12. When the read completion signal 12 is given, the cache read completion signal 1
1 to MPU1.

Note that in cycle S1 of the timing chart of FIG. 3, if the previous reading of data from the main memory 2 has not been completed, the operation is performed as shown in the timing chart of FIG.

That is, at the start of cycle S1 when the cache read start signal 9 output from the MPU 1 is applied to the sequencer 4, data is read from the main memory 2 as shown in FIG. 4(c). If the main memory read completion signal 1 is not completed yet, the main memory read completion signal 1 is sent from the main memory 2.
2 is not being output, the sequencer 4 suspends outputting the main memory read start signal 10. And Figure 4 (
As shown in c), when the reading of data from the main memory 2 is completed at the end of the cycle S1 and the main memory read completion signal 12 is output, the sequencer 4 outputs the main memory read start signal 10. The data is output to the main memory 2 and the next data read operation is started from the start of cycle S2.

Therefore, in this case, a total of four cycles are required, starting from cycle S1 when the MPU 1 starts the data read operation and ending at cycle S4.

Next, a second alternative embodiment of the present invention will be described. In this embodiment, the hit signal 13 is also applied to the main memory 2, as indicated by the broken line in FIG. The main memory 2 is configured to stop the data read operation when this hit signal 13 is applied.

The operation when the cache memory 3 of another embodiment of the present invention is hit will be explained with reference to the timing chart of FIG.

As shown in FIGS. 5A and 5B, reading of data by the MPU 1 is started, a hit occurs in the cache memory 3, and a hit signal 13 is output. Further, as shown in FIG. 5C, the cache read start signal 9 is applied to the main memory 2, so the main memory 2 starts reading data in cycle S1. The operation up to this point is the same as that shown in the timing chart of FIG. 2 described above. However, in this embodiment, since the hit signal 13 is also input to the main memory 2, the main memory 2 stops the data read operation in cycle S2, as shown in FIG. 5(c).

If the situation shown in the timing chart of FIG. 2 occurs, that is, when the data read by the MPU 1 hits the cache memory 3 and then the data read by the MPU 1 misses, Figure 4
The state is as shown in Figure 2, cycle S4.
Reading of the next data from the main memory 2 starts from (cycle S2 in FIG. 4).

However, with the configuration of this embodiment, in such a case, data can be immediately read from the main memory 2 in cycle S3 in FIG. 2 (cycle S1 in FIG. 4).

[0059]

[Effects of the Invention] As detailed above, according to the present invention,
Since it is equipped with a sequencer that reads data from the main memory at the same time as the MPU starts reading data from the cache memory, the main memory can be read even if the cache memory does not hold the data that the MPU is trying to read. The time required to read data from memory is reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a computer system equipped with a cache memory according to the present invention.

FIG. 2 is a timing chart showing the operating state of the computer system of the present invention when a cache hit occurs.

FIG. 3 is a timing chart showing the operating state of the computer system of the present invention when a cache miss occurs.

FIG. 4 is a timing chart showing the operating state of the computer system of the present invention at the time of a cache miss.

FIG. 5 is a timing chart showing the operating state of another embodiment of the computer system of the present invention at the time of a cache hit.

FIG. 6 is a block diagram showing an example of a conventional general configuration of a computer system equipped with a cache memory.

FIG. 7 is a timing chart showing the operating state of a conventional computer system when a cache hit occurs.

FIG. 8 is a timing chart showing the operating state of a conventional computer system when a cache miss occurs.

[Explanation of symbols]

1 MPU 2 Main memory 3 Cache memory 4 Sequencer 14 Buffer

Claims (3)

[Claims] 1. A computer system comprising: a data processing means; a main memory storing data read by the data processing means; and a cache memory holding a part of the data stored in the main memory. , when the data processing means issues a data read request,
If the cache memory holds the data, the data is read from the cache memory and the main memory, respectively, and the data processing means is configured to read the data read from the cache memory. Characteristic computer system. 2. A method comprising: a data processing means; a main memory storing data read by the data processing means; and a cache memory holding a part of the data stored in the main memory; When the means issues a data read request, the cache memory determines whether or not it holds the data, and if the cache memory holds the data, the data is retrieved from the cache memory. In the computer system, the data is read out and read into the data processing means, and when the data is not held in the cache memory, the data is read out from the main memory and read into the data processing means. a control circuit that causes the main memory to read the data when the data processing means issues a data read request; and a control circuit that causes the main memory to read the data; A computer system comprising: means for blocking transmission of read data to the data processing means. 3. A method comprising: a data processing means; a main memory storing data read by the data processing means; and a cache memory holding a part of the data stored in the main memory; When the means issues a data read request, the cache memory determines whether or not it holds the data, and if the cache memory holds the data, the data is retrieved from the cache memory. In the computer system, the data is read out and read into the data processing means, and when the data is not held in the cache memory, the data is read out from the main memory and read into the data processing means. If the previous reading of data from the main memory has been completed when the data processing means issues a request to read the data to be processed, it causes the main memory to read the data, and If the previous reading of data from the main memory has not been completed when the processing means issues a request to read the data to be processed, if the data is held in the cache memory, the data is stored in the main memory. a control circuit that does not read data and causes the main memory to read the data when the data processing means completes reading the data when the cache memory does not hold the data; A computer system comprising: means for interrupting transmission of data read from the main memory to the data processing means when a cache memory holds the data.