JPH10312354A - Interruption processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To standardize software processing and to shorten an interruption processing time by eliminating contradiction between the processing by software and the state of hardware. SOLUTION: When an interruption generating units (IU) 41 or 42 initiate an interruption, an interruption gathering means (INTU) 40 receives the interruption, sets a flag 51-1 corresponding to the IU 41 or 42 having initiated the interruption, and interrupts a central processing unit(MPU) 60 when the flag 51-2 corresponding to the IU 42 is not set or does not interrupt the MPU 60 when the flag 51-2 is set. Further, when an instruction for clearing the flag 51-1 is executed by the MPU 60, the INTU 50 interrupts the MPU 60 if there is the set flag 51-2 present even after the clearing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an interrupt processing system in an information processing device, various computer control devices, and the like.

[0002]

2. Description of the Related Art In general, in an interrupt processing system such as an information processing apparatus and various computer control apparatuses, a central processing unit (hereinafter, referred to as an "MP") for program-controlling the entire system
U ") and devices such as input / output devices controlled by the MPU. A device such as an input / output device controlled by the MPU generates an interrupt in order to request the MPU to perform processing, and is referred to as an interrupt generating device in this specification. The MPU has a limit on the number of interrupt generation devices (hereinafter, referred to as “IUs”) that can accept interrupts, so the number of IUs that can be connected to one interrupt processing system is limited. Regarding the interrupt processing of the MPU, the MPU has a table (hereinafter, referred to as a “vector table”) in which a start address of a program to be processed when an interrupt occurs is stored. When the IU interrupts the MPU, the IU notifies the MPU of the number of the program indicated by the vector table corresponding to itself (this is called a "vector number"), thereby executing the appropriate program. Can be requested from the MPU.

When the number of IUs is small, the MPU and each IU are connected by one-to-one signal lines, and the MPU can recognize a vector number depending on which line interrupted. However, as the number of IUs increases, the number of signal lines also increases. Therefore, a method called a bus command interrupt is used to notify an interrupt from the IU to the MPU. The bus command interrupt method is defined as
When a bus command such as a write access to a specific address in U is performed, an interrupt is generated. At this time, the vector number is specified in a data portion or the like at the time of write access. In an interrupt processing system employing such a bus command interrupt system, when an MPU is connected to IUs that are equal to or more than the limited number of IUs that can accept an interrupt (that is, when the number of IUs becomes larger than the vector number). Conventionally, as a hardware configuration method, for example, there is a method as shown in FIG.

FIG. 2 is a configuration diagram showing an example of a conventional interrupt processing system. This interrupt handling system
It has a system bus 1 to which IUs 11 and 12 that generate interrupts with the same vector number are connected. Although only two IUs 11 and 12 are shown in FIG. 2, several tens or more IUs are generally connected. The system bus 1 is connected to an MPU 20 for program-controlling the IUs 11 and 12. MPU20
Is the processor on which the software runs (hereinafter "P
R ") 21 and an interrupt factor register (hereinafter, referred to as" R ").
24 (referred to as “IRR”). IRR24 is
Flags 24-1 and 24-2 are provided by the number of IU vector numbers supported by PR21. In FIG. 2, only the interrupt factor flag 24-1 for the vector number 1 and the interrupt factor flag 24-2 for the vector number 2 are shown. PR21 and IRR24 are connected to the MPU internal bus 22.
Is connected to the system bus 1 by the PR21.
And the IRR 24 are connected by an interrupt line 23.

[0005] An interrupt from the IU 11 or IU 12 to the MPU 20 is realized as a write access to the IRR 24 via the system bus 1 and the MPU internal bus 22. In the IRR 24, flags 24-1 and 24-2 corresponding to the corresponding vector number are set, and
By turning on the interrupt line 23 for R21, an interrupt process is requested. PR2 that received the interrupt
1 reads a vector number from the IRR 24 through the MPU internal bus 22 and requests interrupt processing to software (hereinafter, simply referred to as “soft”). The software is M
IU from the PU internal bus 22 via the system bus 1
11 and 12 are controlled. FIG. 3 is a flowchart showing an interrupt process when an interrupt to the MPU 20 occurs from the IUs 11 and 12 with the same vector number in the interrupt processing system of FIG. For simplicity, the IRR 24 has two flags 24-1 and 24-2.
Only -2 is shown.

This interrupt processing is performed in the following steps S1 to S1.
It is executed in the order of S9. Step S1: The MPU 20 (IRR2) is sent from the IU11.
In response to 4), an interrupt bus command is transmitted as write access from the IU 11 to the IRR 24. As the data of this write access, vector number 1
Is transferred. Step S2: IRR set for vector number 1 and PR
The IRR 24 that has received the interrupt bus command of the vector number 1 from the interrupt IU 11 sets the flag 24-1 of the IRR 24 corresponding to the vector number 1 from “0” to “1”,
Is turned on, and the PR 21 is notified. Step S3: Start of interrupt processing for vector number 1 of PR software The interrupted PR 21 obtains the interrupt vector number 1 from the IRR 24 and starts interrupt processing for the vector number 1. Step S4: The MPU 20 (IRR2
FIG. 3 shows a case where an interrupt of vector number 1 is generated from the IU 12 while the PR 21 is performing the processing of steps S2 and S3 for 4). In this case, IRR24
Have the same vector number 1 and therefore have the same flag 24-1.
Is set from “1” to “1”, and the value does not change.

Step S5: IRR by PR software
Clear Since the PR21 software has accepted the interrupt of the IU11, the IRR24 corresponding to the vector number 1 currently being processed is cleared.
Is cleared from "1" to "0". Step S6: Confirmation of Interrupt Source by PR Software The software on the PR 21 searches the IUs 11 and 12 having the vector number 1 in order to confirm whether the current interrupt has come from the IU 11 or 12. Step S7: Interrupt Processing for IU11 by PR Software Since there is an interrupt generation factor in IU11, the PR software executes interrupt processing for IU11. Step S8; Interrupt Processing for IU12 by PR Software Since the IU12 also has an interrupt generation factor, the PR software executes the interrupt processing for IU12. Step S9: Termination of Interrupt Processing of PR Software The PR software terminates the interrupt processing by a return instruction (RET).

[0008]

However, the conventional interrupt processing system has the following problems (1) to (4). (1) When the order of the interrupt bus command from the IU 12 in step S4 and the IRR clear from the PR 21 in step S5 are reversed, the flag 24-1 of the IRR 24 is set to "1" even after the end of the interrupt processing in step S9. In this state, the interrupt process of the PR 21 is executed again. As a result, since the interrupt occurrence factor has been processed, inconsistency between the software processing and the hardware state occurs. (2) In order to solve the problem (1), if the interrupt processing for the IU12 in step S8 is not performed, if the order of steps S4 and S5 is reversed in FIG. 3 is as shown in the flowchart of FIG. 3, the interruption to the IU 12 is eliminated. Such inconsistencies can cause software processing to
It occurs even if the order of clearing RR24 and interrupt processing is changed. For example, assuming that the IRR clear processing of step S5 is performed immediately before the processing of step S9, step S4
Of the bus command from the IU 12 of step S6
Occurs after the confirmation of the IU of the interrupt occurrence source, a contradiction occurs.

(3) In the procedure of the flowchart of FIG. 3, it is necessary to execute interrupts for a plurality of IUs 11 and 12 for the IU 11 and IU 12 in one interrupt process, so that software processing cannot be unified. At one time, an interrupt process for one IU 11 is performed from the start of the interrupt to the return process, and at another time, an interrupt process for a plurality of IUs 11 and 12 is performed during the same process. (4) In the flowchart of FIG. 3, as shown in step S6, all IUs 11, 12 having the same vector number 1
Must be searched, and the interrupt processing time becomes longer.
The present invention has the problems (1) to
It is an object of the present invention to solve the problem (4), eliminate an inconsistency between software processing and a hardware state, unify software processing, and provide an interrupt processing system in which an interrupt processing time is shortened.

[0010]

According to a first aspect of the present invention, there is provided an interrupt processing system in which a plurality of IUs for generating an interrupt bus command with the same vector number are connected. System bus,
Interrupt aggregating means (hereinafter referred to as “INT”) having first flags as many as the IUs connected to the system bus and generating the interrupt bus command with the same vector number
U "), connected to the system bus and having the same number of second flags as the vector numbers for IUs to perform interrupt processing, and having flag clear means,
And an MPU for program-controlling the INTU.

When the interrupt bus command is output from the IU to the system bus, the INTU fetches an interrupt bus command on the system bus and sets the first flag corresponding to the IU. At the same time, when the other first flag corresponding to another IU of the same vector number is not set, an interrupt bus command is newly generated and output to the system bus, and then the flag clear unit sets the interrupt bus command. When the set first flag is cleared and the other first flags are set, a new interrupt bus command is not generated, and the first flag set by the flag clear means is cleared. If there is another first flag of the same vector number that has been cleared but still set , And the new interrupt bus command to the configuration to be output to the system bus. The MPU
Captures a new interrupt bus command on the system bus when a new interrupt bus command is output from the INTU to the system bus, and sets the second flag corresponding to a corresponding vector number. Interrupt processing, and the flag clear means clears the corresponding first and second flags.

According to a second aspect of the present invention, the system bus and the MPU of the first aspect are connected between the system bus and an extended system bus to which a plurality of IUs are connected. And a bus expansion controller (hereinafter, referred to as "BEXU") for performing the operation, wherein the BTU is provided with the INTU according to claim 1 of the present invention. According to a third aspect of the present invention, in the interrupt processing system of the first or second aspect, a flag setting means for setting a first flag in the INTU under the control of the MPU is provided.

According to the present invention, since the interrupt processing system is configured as described above, when an interrupt occurs from one or more of a plurality of IUs having the same vector number, the interrupt is received by the INTU. And setting a first flag in the INTU corresponding to the IU in which the interrupt occurred, and executing an interrupt to the MPU if the first flag corresponding to another IU is not set. When the first flag corresponding to the IU is set, the MPU is not interrupted. Further, when an instruction for clearing the first flag is executed by the flag clear means of the MPU, if there is a first flag that has been set after clearing, the I flag is set.
A new interrupt is generated from the NTU to the MPU.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a configuration diagram of an interrupt processing system according to a first embodiment of the present invention. This interrupt handling system
A basic system bus 30 having a data line, an address line and a control line is provided. A plurality of IUs 41 and 42 (generally, several tens or more IUs) generating an interrupt with the same vector number are connected to the system bus 30. However, only two are shown for the sake of simplicity), the INTU 50 and the MPU 60 are connected. Note that the INTU 50 and the MPU 60 may be configured on the same board. INT
U50 is an auxiliary interrupt factor register (hereinafter referred to as “SIR
R ”). The SIRR 51 is provided with a first flag corresponding to each of the IUs 41 and 42 interrupted by the same vector number. In FIG. 1, for the sake of simplicity, an interrupt factor flag 51-1 for IU41 and an interrupt factor flag 51-2 for IU42 are shown as first flags. Generally, IU41, 42
The source and destination numbers are assigned to the interrupt bus commands output from the. This number is a number assigned to distinguish devices such as the MPU 60, IU 41, and IU 42 in the interrupt processing system. S
Which of the flags 51-1 and 51-2 of the IRR 51 is set is identified by the sender number.

The MPU 60 comprises IUs 41 and 42 and INT
The U50 is program-controlled and has PR61 and IRR64 on which software runs. These PR61 and IRR64 are connected to the system bus 30 by the MPU internal bus 62, and the PR61 and IRR64 are connected by the interrupt line 63. Have been. IRR64 is
The number of second flags is equal to the number of IU vector numbers supported by PR61. In FIG. 1, for simplicity of explanation, an interrupt factor flag 64-1 for vector number 1 and an interrupt factor flag 64-2 for vector number 2 are shown as second flags. The PR software is connected to the IU4 via the MPU internal bus 62 and the system bus 30.
1, 42 and the INTU 50.

Here, the functions of the INTU 50 and the MPU 60 will be described. An interrupt from the IU 41 or 42 to the MPU 60 is sent to the MPU 60 via the system bus 30.
Implemented as a write access to the IRR 64 in 60, the INTU 50 intercepts the write access,
Set SIRR51 and set IU41 or 42
It has a function of prohibiting transmission of the interrupt write access from the MPU 60 to the MPU 60. INTU50 is SIRR
When the flag 51-2 (for example, 51-1) is set and the flag 51-2 of the other SIRR 51 is not set, the interrupt bus command of the vector number 1 is generated from the INTU 50 to the MPU 60. If the flag 51-2 of the other SIRR 51 is set, it has a function of not generating an interrupt cycle for the MPU 60. In addition, the INTU 50 transmits the S
A function (means) for clearing the IRR 51 for each of the flags 51-1 and 51-2, and when cleared from the MPU 60, other flags 51-2 of the SIRR 51 even if cleared.
Is set, the INTU 50 to the MPU 60
Has the function of generating a new bus command interrupt cycle for

When the IRR 64 in the MPU 60 receives an interrupt bus command from the system bus 30, a flag 64-1 or 64-
2 as well as interrupt line 6 for PR61
By turning on 3, an interrupt process is requested.
Upon receiving the interrupt, the PR 61 reads the vector number from the IRR 64 through the MPU internal bus 62 and requests the PR software for an interrupt process. Thus, the PR software controls the IUs 41 and 42 and the INTU 50 via the MPU internal bus 62 and the system bus 30.

FIG. 4 is a block diagram of the interrupt processing system shown in FIG.
9 is a flowchart showing an interrupt process when an interrupt occurs for the first embodiment. This interrupt processing is executed in the order of the following steps S11 to S24. Step S11: Interruption from IU41 An interrupt request from IU41 is transmitted on system bus 30 as write access to IRR64. IN
The TU 50 fetches the interrupt write command on the system bus 30 and sets the flag 51-1 corresponding to the IU 41 of the SIRR 51 from "0" to "1". The INTU 50 also determines that the interrupt bus command is MP
Prohibit transmission to U60. INTU50 is SIR
Since the other flag 51-2 of R51 is not set, an interrupt bus command for the MPU 60 is newly generated. As a result, the flag 64-1 corresponding to the vector number 1 of the IRR 64 in the MPU 60 is set from “0” to “1”.

Step S12: Set interrupt factor flag for vector number 1 and interrupt for PR61 Turn on the interrupt line 63 from IRR64 to PR61 and notify PR61. Step S13: Start interrupt processing for vector number 1 The interrupted PR 61 obtains the interrupt vector number 1 from the IRR 64 and starts the interrupt processing for the vector number 1. Step S14: Interruption from IU 42 FIG. 4 shows a case where an interrupt of vector number 1 is generated from the IU 42 while the PR 61 is performing the processing of steps S12 and S13. Step S11
Similarly, the INTU 50 fetches an interrupt command from the IU 42 to the MPU 60, and
Is set from "0" to "1". Further, transmission of the interrupt bus command to the MPU 60 is prohibited. INTU50 is SIRR51
Since the other flag 51-1 is set, the MPU
No new interrupt bus command is issued for 60.

Step S15: IR by PR software
R clear The PR61 software has accepted the interrupt of the vector number 1, so the IRR corresponding to the vector number 1 currently being processed is
The 64 flags 64-1 are cleared from "1" to "0". Step S16: Checking the source of the interrupt by the PR software The software on the PR 61 reads the SIRR 51 in the INTU 50 to check which IU 41 or 42 the current interrupt came from, and generates an interrupt from which IU 41 or 42. Make sure that In FIG. 4, IU
The flag 51-1 corresponding to the IU 41 and the flag 51-2 corresponding to the IU 42 are both set. In this case, it is determined that an interrupt from the IU 41 has occurred. That is, when a plurality of flags 51-1 and 51-2 are set, the first flag is made valid, and subsequent flags are ignored. The PR61 software recognizes that an interrupt request from the IU41 has occurred, and
The flag 51-1 corresponding to the IU41 of R51 is cleared from "1" to "0".

Step S17: S by INTU50
IRR Reset Processing When the flag 51-1 of the SIRR 51 is cleared, the INTU 50 issues an interrupt bus command to the MPU 60 because there is another flag 51-2 set. Step S18: IU41 Interrupt Processing by PR Software The PR61 software executes IU41 interrupt processing because the IU41 has an interrupt generation factor. Step S19; End of Interrupt Processing for IU41 of PR Software The PR61 software ends the interrupt processing by a return instruction (RET). Step S20: Re-Generation of Interrupt for Vector Number 1 After the interrupt processing for the IU 41 is completed, the flag 64-1 of the IRR 64 is reset in step S17, so that an interrupt is again generated for the PR 61. Steps S21 to S24; Interrupt Processing for IU 42 In the software processing theory of the interrupt processing for the IU 42, the interrupt processing for the IU 42 is executed this time by the same processing as the steps S15, S16, S18, and S19.

As described above, in the first embodiment,
The following effects (i) to (iii) are obtained. (I) One interrupt is always generated in response to an interrupt from one IU 41 or 42. Therefore, IU4
No inconsistency occurs between the occurrence of an interrupt from 1 or 42 and the timing of clearing the interrupt occurrence factor flag IRR64 from the PR 61. That is, despite the presence of the IU 41 or 42 of the interrupt request, the PR 61 does not generate an interrupt, or the absence of the IU 41 or 42 of the interrupt request,
There is no inconsistency such as occurrence of an interrupt in R61. (Ii) As shown in the flowchart of FIG.
The above software is always one IU for one interrupt
It is only necessary to perform the processing for 41 or 42, and the software processing can be the same. (iii) Since the SIRR 51 of the INTU 50 is provided, the time for searching which IU 41 or 42 is causing the interrupt is reduced.

Second Embodiment FIG. 5 is a block diagram of an interrupt processing system according to a second embodiment of the present invention. Common elements to those in FIG. 1 showing the first embodiment are common. Are given. Generally, the vector number for IU supported by the MPU 60 of FIG. IU4 that this number is insufficient
It is impossible to physically connect 1, 42 with one unit. Therefore, it is common to provide a device for expanding the basic system bus 30. In the second embodiment, the basic system bus 30 of FIG.
The basic system bus 30 is expanded by providing the XU 70 and connecting the expansion system bus 31. 1 is provided in the BEXU 70. IUs 41 and 42 are connected to the basic system bus 30, and IUs 43 and 44 are connected to the extended system bus 31. IUs 41 and 42 connected to the basic system bus 30 are assigned vector numbers independently of vector numbers 1 and 2, respectively, and IUs 43 and 44 connected to the extended system bus 31 have the same vector numbers. 3 is assigned. Although the number of IUs is generally several tens or more, FIG. 5 shows only four IUs 41 to 44 for simplicity of explanation.

The BEXU 70 has a bus extension control means 71 and an INTU 50. Bus extension control means 71
Is the basic system bus 3 on which the MPU 60 is mounted.
0 and the system bus command relay function between the extended system bus 31 on which the MPU 60 is not mounted. This makes it possible to accommodate devices that cannot be accommodated in one system bus 30 structurally or electrically in the system. INTU provided in BEXU70
50 has a SIRR51, in which SIRR51,
A first flag is provided for each IU 43, 44 interrupted by the same vector number 3. In FIG. 5, the IU 43 interrupt factor flag 51-3 is used as the first flag.
And the interrupt factor flag 51-4 for the IU44. Due to the expansion of the bus, the interrupt factor flag 64-1 for vector number 1, the interrupt factor flag 64-2 for vector number 2, and the interrupt factor flag 64-3 for vector number 3 are included in the IRR 64 of FIG. It is shown.

In the interrupt processing system having such a configuration, when an interrupt is generated from the IUs 41 and 42, the interrupt processing is directly performed by the MPU 60. IU43,44
In response to an interrupt from
The information is transmitted to the MPU 60 via the TU 50, and the interrupt processing is executed. As a result, the IUs 43 and 44 under the extension system bus 31 communicate with the ITU 50 in the BEXU 70.
Thus, the interrupt at the same vector number 3 can be performed without contradiction. In addition, I on the basic system bus 30
The U41 and U42 have different vector numbers from the IU43 and 44, so that the PR61 in the MPU60 can perform interrupt processing without inconsistency. As described above, the interrupt system according to the second embodiment has substantially the same effects as those of the first embodiment, and also has the following effects. Compared to providing a new circuit board for the INTU 50 as shown in FIG. 1, the INTU 50 is provided in the BEXU 70, so that there is no need to install a new circuit board for the INTU 50 and the amount of hardware can be reduced. Further, the allocation of the vector numbers 1, 2, 3 is in accordance with the physical arrangement, and the management becomes easy.

Third Embodiment In the interrupt processing system of FIG. 1 or FIG.
PR61 in U60 to SIRR51 in INTU50
Flag setting means for setting the flags 51-1 to 51-4. The flag setting means PR6
1 and a setting mechanism of the SIRR 51. If such a flag setting means is provided, PR
Also when the flags 51-1 to 51-4 of the SIRR 51 are set from 61 to 61, the logic determination is performed and an interrupt to the MPU 60 is generated in the same manner as when the flags are set to SIRR 51 from the IUs 41,. Therefore, for example, INT
When testing the circuit of U50, the IU4
.. Are not prepared by the number of flags 51-1,... Of the SIRR 51, and the circuit test of the INTU 50 can be performed only by accessing from the PR 61 by software. Also,
In the processing of the PR61 software, if there is a case where it is desired to generate a pseudo interrupt, the PR
This is made possible by setting R51. Note that the present invention is not limited to the above embodiment, and various modifications are possible, for example, changing the procedure of the interrupt processing of FIG. 4 to another processing procedure.

[0027]

As described in detail above, according to the first aspect of the present invention, since the ITU is provided between the IU and the MPU that processes the interrupt, the following (a) to (c) are provided. Has a significant effect. (A) One interrupt always occurs for an interrupt from one IU. Therefore, regardless of the timing of the occurrence of an interrupt from the IU and the timing of the second flag clear, despite the presence of the interrupt request IU, the MP
There is no inconsistency such as a state in which an interrupt does not occur in U and a state in which an interrupt occurs in the MPU even though there is no interrupt request IU. (B) The software in the MPU only needs to perform the processing for one IU for one interrupt, and the software processing can be the same. (C) Since the INTU having the first flag is provided,
It is possible to shorten the time for searching which IU has generated the interrupt.

According to the second aspect of the present invention, the I
Since the NTU is provided, the IU under the extension system bus is B
Interrupts with the same vector number can be performed without contradiction by the INTU in the EXU, and IUs on the basic system bus can perform interrupt processing in the MPU without contradiction because the vector numbers are different. Therefore, in addition to having substantially the same effects as the first aspect of the present invention, there is no need to install a new circuit board, and the amount of hardware is reduced, as compared with the case where a new circuit board is provided for INTU as in the first aspect. Can be reduced. Moreover, the allocation of the vector numbers is in accordance with the physical arrangement, and the management becomes easy. According to the third aspect of the present invention, the flag setting means for setting the first flag in the INTU under the control of the MPU is provided.
In order to test the circuit of U, the IUs are not prepared by the number of the first flags at this test,
The circuit test of the INTU can be easily performed only by the access from the U. In addition, when there is a case in which a pseudo interrupt is desired to be generated in the processing of software of the MPU, it is easily possible by setting the first flag by the software of the MPU.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an interrupt processing system according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional interrupt processing system.

FIG. 3 is a flowchart of an interrupt process of FIG. 2;

FIG. 4 is a flowchart of an interrupt process of FIG. 1;

FIG. 5 is a configuration diagram of an interrupt processing system according to a second embodiment of the present invention.

[Explanation of symbols]

30 Basic System Bus 31 Extended System Bus 41-44 IU (Interrupt Generator) 50 INTU (Interrupt Aggregation Means) 51 SIRR (Auxiliary Interruption Factor Register) 51-1 to 51-4 Interruption Factor Flag 60 MPU (Central Processing Unit) 61 PR (processor) 64 IRR (interrupt cause register) 64-1 to 64-3 interrupt cause flag 70 BEXU (bus expansion control device) 71 bus expansion control means

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideyuki Murakami 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Katsuyuki Okada 3-192-2 Nishishinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Michihiro Aoki Inventor 3-192-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Seiji Deya 3-192-2, Nishi-Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (3)

[Claims] 1. A system bus to which a plurality of interrupt generating devices for generating an interrupt bus command with the same vector number are connected, and said interrupt generation connected to said system bus and generating said interrupt bus command with said same vector number. Interrupt aggregating means having first flags as many as the number of devices, and having as many second flags as the number of vector numbers for interrupt generating devices connected to the system bus and performing interrupt processing, and flag clear means. A central processing unit for program-controlling the interrupt generating device and the interrupt aggregating device, wherein the interrupt aggregating device is configured to output the interrupt bus command to the system bus from the interrupt generating device. Captures an interrupt bus command on the bus and sends it to the interrupt generator. When the corresponding first flag is set and another first flag corresponding to the other interrupt generating device having the same vector number is not set, an interrupt bus command is newly generated to When the first flag that has been set is cleared by the flag clear means after outputting to the system bus and another first flag is set, a new interrupt bus command is not generated,
Further, if the first flag set by the flag clearing means is cleared but another first flag of the same vector number still set remains, a new interrupt bus command is issued to the system. When a new interrupt bus command is output from the interrupt aggregating means to the system bus, the central processing unit fetches a new interrupt bus command on the system bus, and An interrupt processing system, wherein the second flag corresponding to a vector number is set to execute an interrupt process, and the flag clear means clears the corresponding first and second flags. 2. A system bus and a central processing unit according to claim 1, connected between the system bus and an extended system bus to which a plurality of interrupt generating devices are connected, and controls an interface between these two system buses. An interrupt processing system, comprising: a bus extension controller; and a bus aggregation controller according to claim 1. 3. The interrupt processing system according to claim 1, further comprising a flag setting means for setting a first flag in said interrupt aggregation means under the control of said central processing unit. system.