JP2969817B2 - Information processing system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system in which two systems each including a processing device, a main storage device, and a system control device are connected. The present invention relates to an information processing system capable of directly referencing and updating both the main storage device of another system and the main storage device of another system from the system control device of the own system.

[Conventional technology]

Conventionally, in an information processing system in which a processing device can directly refer to and update a main storage device of its own system and a main storage device of another system directly from its own system control device. In addition, the history memory that holds the main storage reference update history of the own system needs to hold the reference update history of the main storage device of the other system together with the main storage device of the own system.

[Problems to be solved by the invention]

As described above, in the conventional information processing system, it is necessary to retain the reference update history of the main memory of another system together with the main memory of the own memory of the history memory for retaining the history. Are required one by one,
There is a problem that the amount of hardware increases.

An object of the present invention is to provide an information processing system capable of reducing the capacity of the history memory and reducing the amount of hardware by solving the conventional disadvantages.

[Means for solving the problem]

The information processing system of the present invention holds a reference update history of its own main storage device, and a history memory controlled by its own system control device, and its own system control device refers to another main storage device. Notification means for notifying the system controller of the other system when updating or requesting the reference or update of the history memory of the other system, and referring to or updating the main storage device of the own system from the notification means. The history memory access means for referring to and updating the history memory of the own system and the history memory access means of the other system when receiving a notification of the execution or when receiving a request for referring to or updating the history memory of the own system. The read reference data of the other system memory is received, and the reference data reception device generates data indicating that the main memory of the other system has been updated when the system controller of the other system is not connected. And a means.

[Action]

In the present invention, the history memory of the own system (other system) holds only the reference update history of the main storage device of the own system (other system), and the system controller of the own system stores the reference update history of the other system. Refer to and update storage devices, refer to other system's history memory,
When an update is requested, that fact is notified to the system control device of the other system, and upon receiving this notification, the history memory of the other system is referenced and updated. As a result, in the own system control device, the reference data receiving unit can refer to the other system history memory, and the own system history memory does not hold the reference update history of the other system main storage device. However, the reference update history of the main storage device of another system can be grasped.

〔Example〕

Next, the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of an embodiment of an information processing system according to the present invention.

Referring to FIG. 1, the information processing system according to the present embodiment is configured by connecting two systems 10 and 11 having the same configuration, and each system 10 and 11 includes a processing device 1 and 5, It has system control devices 2 and 6, history memories 3 and 7, and main storage devices 4 and 8. In addition, each of the system control devices 2 and 6 has a command decode notification unit 21 and 61, history memory access units 22 and 62, and history data reception units 23 and 63, respectively.

Since the two systems 10 and 11 have the same configuration, for simplicity, attention is focused on one system 10 and the mutual relationship between the system 10 and the other system 11 will be described. System controller 2 for system 10
Centrally manages requests from the processing devices 1 of the own system 10 and
The 10 main storage devices 4 and the main storage device 8 of the other system 11 can be directly referenced and updated. The history memory 3 holds only the reference update history of the main storage device 4 of the own system 10 and is controlled by the system controller 2 of the own system 10.

The system control device 2 of the own system 10 is replaced with the main storage device 8 of the other system 11
When the system controller 2 of the own system 10 receives a request for reference or update of the history memory 7 of the other system 11 from the processor 1 of the own system 10, 2 command decode notification section
21 notifies the system controller 6 of the other system 11 that the main memory 8 is to be referred to or updated, or that the history memory 7 is to be referred to or updated.

When the system control device 2 of the own system 10 receives a notification from the command decode notifying unit 6 of the other system 11 to refer to or update the main storage device 4 of the own system 10, the system control device 2 of the The history memory access unit 22 accesses the history memory 3 of the own system 10, writes update data indicating that the main storage device 4 of the own system 10 has been referenced or updated, and updates the history memory 3. Perform and own system 10
When the system control device 2 receives a request to refer to or update the history memory 3 of the own system 10 from the command decode notification unit 61 of the other system 11, the system control device 2 refers to or updates the history memory 3 of the own system 10. In the case of referring to the memory 3, predetermined data is read from the history memory 3 and is read from the other system 11.
Is transmitted to the system controller 6.

The history data receiving unit 23 of the system control device 2 of the own system 10 reads out the history memory access unit 62 of the other system 11 from the history memory 7 of the other system 11 in response to a request from the system control device 2 of the own system 10. While accepting reference data,
When the eleven system controllers 6 are not connected,
Data indicating that the main storage device 8 of the other system 11 has been updated is generated and output as a substitute for the reference data.

FIG. 2 is a diagram showing a specific example of the history data receiving unit 23. In FIG. 2, the history data receiving unit 23 is "1" when the system control device 6 is not connected, and "1" when the system control device 6 is connected. 0 "
And an OR gate 2 that takes the logical sum of the output of the flip-flop 231 and the reference data RRD1 from the history memory 7 of the other system 11 and outputs the result as data RRDXO
32. Note that the history data receiving unit 63 has the same configuration as that of FIG.

Next, a specific operation of the information processing system having such a configuration will be described. Now, the main storage devices 4,8 of each system 10,11
Is assumed to have a capacity of 128 bytes, and is designated by an 8-bit address. The main storage device 4 is selected when the most significant bit of the address is "0", and when the most significant bit is "1". It is assumed that the storage device 8 is selected. In addition, a history memory that holds reference update histories of the main storage devices 4 and 8, respectively.
Each of 3, 7 holds a history for every 16 bytes of the main memory. In the following description, a number with “#” indicates that the number is represented in hexadecimal.

First, a case where the processing device 1 of the system 10 updates the address “08 #” of the main storage device 4 of the system 10 will be described. In this case, the processing device 1 updates the main memory with the command signal CMDO. , The address signal ADO is set to “08 #”, and the data to be written is specified by the data signal DTO. The command decode notification unit 21 decodes the signal CMDO and outputs the signal ADO
MMWO indicating the update to the main storage device 4 with reference to the most significant bit of The main storage device 4 stores the signals ADO, DT
O via the system controller 2 and the signal MMW
O is received, and data DTO is written to address “08 #”.
On the other hand, the history memory access unit 22 outputs the data “1” indicating that the main storage device 4 has been updated by the signals MMWO and ADO.
1 "is embedded in the signal RWDO, the first to third bits" 000 "counted from the most significant bit of the signal ADO are embedded in the RADO, and the write enable signal RWEO of the history memory 3 is sent out. Data “11” is written to the address “000” of the memory 3.

Next, the processing device 1 of the own system 10 becomes the main storage device 8 of the other system 11.
The case where reference is made to the address “94 #” will be described. In this case, the processing device 1 specifies the main memory reference by the signal CMDO, and sets the address signal ADO to “94 #”. The command decode notifying unit 21 decodes the signal CMDO, refers to the most significant bit of the signal ADO, and sends out a signal HMRO indicating a reference to the main storage device 8. As a result, the main memory 8 of the other system 11 sends the signal ADO to the system controller 2.
HMRO and the address “94
The data “#” is read out, embedded in the signal MRD1, and returned to the processing device 1 via the system control device 2. On the other hand, the other system 11
The history memory access unit 62 of signal RMD1 outputs data “10” indicating that the main storage device 8 has been referred to by the signal HMRO.
The first to third bits “001” counted from the most significant bit of the signal ADO are embedded in RAD 1, and a write enable signal RWE 1 is sent to the history memory 7. As a result, data "10" is written to the address "001" of the history memory 7.

Next, a case where the processing device 1 writes data “10” to the address “010” of the history memory 7 will be described. In this case, the address specification is such that the first to third bits counted from the most significant bit are "010", and the most significant bit, that is, the zeroth bit is the update of the history memory 7 of the other system 11, so "1" And Since the fourth to seventh bits are vacant, the update data “10” is embedded therein to be “0010”. Thus, the address becomes “10100010”. According to this,
The processing device 1 specifies the update of the history data with the signal CMDO,
The signal ADO is set to “A2 #”. Command decode notification unit 21
Decodes the signal CMDO, refers to the most significant bit of the signal ADO, and outputs a signal HR indicating an update to the history memory 7.
Send WO. The history memory access unit 62 embeds “010” in the signal RAD1 and embeds data “10” in the signal RWD1 with reference to the signal ADO. At the same time, the signal RWE1 is transmitted by the signal HRWO. As a result, data "10" is written to address "010" of history memory 7.

Next, a case where the processing device 1 refers to the data at the address “010” in the history memory 7 will be described. In this case, the address is specified as "1010" from the most significant bit to the 0th to 3rd bits in the same manner as the update of the history memory 7, and the 4th to 7th bits are not referred to.
The address becomes "10100000". The processor 1 designates the reference to the history memory 7 with the signal CMDO and sets the signal ADO to "A0 #". , Decode the signal CMDO and signal ADO
HRRO indicating the reference to the history memory 7 is transmitted. The history memory access unit 62
With reference to the signal ADO, "010" is embedded in the signal RADO, and the signal RRO is transmitted by the signal HRRO. As a result, the data "10" written at the time of updating the history memory 7 is read from the address "010" of the history memory 7 and embedded in the signal RRD1. The history data receiving unit 23 receives the data of the signal RRD1, embeds the data in the signal RRDDO, and returns it to the processing device 1.

Next, a case where the history memory 7 is referred to when the system control device is not connected will be described. In this case, the history data receiving unit 23 is informed in advance that the system controller is not connected to the flip-flop 23.
Record using 1. The processing device 1 sends CMDO and ADO as in the case where the system control device 1 is in the connected state, and the command decode notifying unit 21 also sends the signal HRRO in the same manner. As a result, the signal RRD1 which is the return value of the history data
Is undefined, but the history data receiving unit 23 outputs the signal RRDX according to the record that the system controller 6 is in the unconnected state.
In O, data “11” indicating that the main storage device 8 has been updated is embedded. Thus, the processing device 1 can recognize that the data has been read from the history memory 7 without being aware that the system control device 6 is not connected.

The above is the operation from the processing device 1 of the system 11,
The same applies to the operation from the processing device 5.

〔The invention's effect〕

As described above, according to the present invention, the history memory of the own system only needs to hold the history of the main storage device of the own system, so that the capacity of the memory can be reduced and the amount of hardware can be reduced. This has the effect.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of an information processing system according to the present invention, and FIG. 2 is a diagram illustrating a configuration example of a history data receiving unit shown in FIG. In the figure, 1,5 ... processing device, 2,6 ... system control device, 3,7 ... history memory, 4,8 ... main storage device, 10,11 ...
... system, 21, 61 ... command decode notification unit, 22, 62 ... history memory access unit, 23, 63 ... history data reception unit, 231
…… Flip-flop, 232 …… OR gate.

Claims (1)

(57) [Claims] An information processing system which can refer to and update a main storage device of its own system and a main storage device of another system from its own system control device. A history memory that holds the reference update history of the device and is controlled by the system controller of the own system, and the system controller of the own system refers to and updates the main storage device of the other system, and refers to and updates the history memory of the other system. And a notification unit for notifying the system controller of the other system when the request is made, and a notification that the main storage device of the own system is referred to or updated from the notification unit or the history of the own system is received. When a request to refer to or update a memory is received, the history memory access means for referring to and updating the history memory of the own system and the reference data of the history memory of the other system read by the history memory access means of the other system are received. An information processing system comprising: reference data receiving means for generating data indicating that the main storage device of the other system has been updated when the system control device of the other system is not connected. .