JPH02162451A - Microprocessor - Google Patents

Abstract

PURPOSE:To shorten the access time by using plural wait terminals for direct input of chip selection signals and preparing a wait generator to produce a wait request signal in accordance with the contents of the input chip selection signal. CONSTITUTION:A microprocessor 11 contains the wait terminals 4-6 for direct input of chip selection signals and a wait generator 7 which produces a wait request signal in accordance with a content of the input chip selection signal. Then an access is given to a peripheral IC to be selected by the chip selection signal when a chip selection signal line 3 is connected to the terminals 4 and 5. In this case, the microprocessor 11 produces automatically a weighted wait request signal via the generator 7. Then the access time is increased in response to the wait request signal. Thus it is possible to decrease the external hardware required for generation of a wait request and to shorten the access time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor that performs arithmetic operations and control for processing data.

[Prior Art] FIG. 2 is a block diagram showing the main structure of a conventional microprocessor and its peripheral circuits. In the figure, 1 is a microprocessor that performs calculations and controls for processing data, 2 is a chip select signal generation circuit that generates a chip select signal for selecting peripheral ICs (integrated circuits), and 3 is a chip select signal. A chip select signal line connected to the generation circuit 2; 8 a wait request generation circuit for generating a wait request signal to the microprocessor 1; 9 a microprocessor for inputting the wait request signal from the wait request generation circuit 8. 1 weight terminal.

Next, the operation will be explained. When a wait request to the microprocessor 1 is generated by software, an instruction for generating the wait request signal is written in the program. As a result, the microprocessor 1 executes the instruction and performs wait processing, but depending on the configuration of the microprocessor 1, the subsequent access time is twice or three times the access time before executing that instruction.
It will be more than doubled. On the other hand, when a wait request is generated by external hardware, a wait request signal is generated from the wait request generation circuit 8, and this wait request signal is input to the microprocessor 1 via the wait terminal 9. As in the case of , the access time of the microprocessor 1 is extended.

[Problem to be solved by the invention]

Conventional microprocessors are configured as described above, so when accessing peripheral ICs with slow access times, it is necessary to add external hardware to generate wait requests, and it is also necessary to add external hardware to generate wait requests using software. In this case, the number of waits remains constant even when peripheral ICs having different access times are accessed, resulting in a problem that the access time becomes longer.

This invention was made to solve the above-mentioned problems, and aims to provide a microprocessor that can reduce external hardware for generating wait requests and shorten access time. .

[Means to solve the problem]

The microprocessor 11 according to the present invention includes wait terminals 4, 4, and 4 for inputting a chip select signal for selecting a chip. 5. 6, and is characterized by having a built-in weight generator 7 that generates a wait request signal corresponding to the content of the chip select signal input to the weight terminals 4, 5, and 6.

[Effect]

A wait request signal is generated by the weight generator 7 in accordance with the contents of the chip select signal inputted to the wait terminals 4, 5.6.

[Embodiments of the invention]

FIG. 1 is a block diagram showing the main structure of a microprocessor and its peripheral circuits according to an embodiment of the present invention.

In the figure, 2 is a chip select signal generation circuit that generates a chip select signal, 3 is a chip select signal line through which a chip select signal flows, and 11 is a microprocessor. The microprocessor 11 has wait terminals 4, 5.6 to which the above-mentioned chip select signal for selecting a chip is directly input, and these wait terminals 4.
, 5.6. Wait terminal 4 is used when the chip select signal is 1 bit, and wait terminal 4 is used when the chip select signal is 2 bits.
For bits, weight terminals 4 and 5 are used. Also,
When the chip select signal is 3 bits, wait terminal 4,
5°6 is used.

Next, the operation will be explained. As shown in FIG. 1, when the chip select signal line 3 is connected to the wait terminals 4 and 5, when accessing the peripheral IC selected by the chip select signal on the chip select signal line 3, the micro In the processor 11, for example, 2'+
The weight generator 7 automatically generates a weighted weight request signal having a weight number of 2'=3,
The access time is extended according to the wait request signal.

However, since the microprocessor 11 does not generate a wait request signal when accessing another peripheral IC, the access time is not extended and the other peripheral IC is accessed in a predetermined access time. In the above embodiment, three weight terminals are provided, but any number may be used.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a plurality of wait terminals into which chip select signals for selecting chips are directly input, and the wait terminals are configured to correspond to the content of the chip select signals input manually to these wait terminals. Since the configuration includes a built-in wait generator that generates wait request signals, external hardware to generate wait requests is not required, and the number of waits can be easily set using multiple wait terminals, making it easy to access. The effect is that the time can be shortened.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing the configuration of a main part of a microprocessor and its peripheral circuits according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the main part structure of a conventional microprocessor and its peripheral circuits. FIG. 3...Chip select signal line, 4,5.6...Wait terminal, 7...Weight generator, 11...Microprocessor, agent Masu Oiwa MC and 2 people) 1st leap, 2nd figure 3 Tono 7 @ E rect signal phantom 4.5, 6; Quebuto n6-J2 (spontaneous) l, Indication of case 2, Title of invention Japanese Patent Application No. 1983-319007 0 Contents of amendment fi + Specification page 3 "Software" in the 8th line is corrected to "Software". (2) Used in lines 1 to 6 of page 5 of the same book. ” will be deleted. (3) The drawings and Figure 1 shall be amended as shown in the attached sheet. ``Tip... and 3, the person who makes the correction - Representative

Claims (1)

[Claims] It has multiple wait terminals for inputting chip select signals for chip selection, and has a built-in weight generator that generates wait request signals corresponding to the contents of the chip select signals input to these wait terminals. A microprocessor characterized by: