JPH0219982A - Microprocessor - Google Patents

Abstract

PURPOSE:To make a bank control circuit unnecessary and to shorten processing time by determining whether a privileged mode signal is to be masked or the above-mentioned privileged mode signal is to be outputted as it is according to the contents of a programmable register and respective status signals. CONSTITUTION:A microprocessor 10 is equipped with an internal interrupt control part 1 to receive a privileged interrupt requesting signal SV1 and output a privileged mode signal SVMO, a status signal generating part 2 to output plural status signals WSS and RSS to indicate the state of a bus cycle, and a register 31 to be able to change the contents of a hold signal and an output signal by a mode control signal MO. Further, the microprocessor 10 is equipped with a programmable decoder 3 to output a mask control signal according to the output signal of the register 31 and the status signals WSS and RSS and a mask circuit 4 composed of a 3-input AND circuit and either mask the previleged mode signal SVMO or output the signal SVMO as it is according to the mask control signal. Thus, the bank control circuit becomes unnecessary, and the processing time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor, and more particularly to a microprocessor that receives a privileged interrupt request signal and outputs a privileged mode signal.

[Conventional technology]

Conventionally, this type of microprocessor includes an internal interrupt control section that receives a privileged interrupt request signal and outputs a privileged mode signal, and a status signal generation section that outputs a plurality of status signals indicating the status of a pass cycle. It was often used in emulation devices, etc.

FIG. 3 is a block diagram showing an example of an emulation device using this microprocessor.

Since the user program is written in the alternative memory 20B and is not in the privileged mode while emulation is being executed, the level of the privileged mode signal SVM becomes "O" and the output of the bank control circuit 30 causes the alternate - The alternative memory 20A is inactive because the chip select signal C8 is "0#," and the alternative memory 1J20B is the chip select signal C8.
is in the active state at '1', and the user program on the alternative memory 20B is executed.

When transitioning from the emulation state to the break state, the privileged interrupt request signal SVI is first input, and the internal interrupt control unit 1 activates a privileged interrupt. Then, the privileged mode signal SVM becomes 11''.

Due to the change in this signal, the output of the bank control circuit 3o changes, and the alternate memory IJ20A becomes an active state when the chip select signal C8 becomes 1'', and the alternative memory 20B becomes an active state when the chip select signal C8 becomes 10#. ,
The control program microprocessor IOB written in the alternate memory 20A is executed and enters a break state.

In this way, in the break state, the alternate memo 'J
20A is active, the control program on this alternate memory 20A is executed, and the alternate memo! 7
20B is inactive.

Now write the contents of the alternate memory 20B to the alternate memo 1J.
20A, the bank control circuit 30 first activates the alternate memory 20B, reads and holds its contents, then activates the bank control circuit 30 to the alternate memory 20A, and transfers the held data. Write. The configuration is such that the above procedure is performed as many times as the number of data to be transferred.

[Problem to be solved by the invention]

The above-mentioned conventional microprocessor IOB is used for an emulation device, etc., and is used as an alternative memory 20 during a break.
B and alternate memory 20. When transferring data between the bank control circuit 30 and the alternative memory 20B
? Since the activation and inactivation states of the alternate memory 20A are controlled, there are disadvantages in that complicated procedures are required and processing time is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor that can simplify procedures and shorten processing time by eliminating bank control circuits.

[Means to solve the problem]

The microprocessor of the present invention includes an internal interrupt control unit that receives a privileged interrupt request signal and outputs a privileged mode signal, a status generation unit that outputs a plurality of status signals indicating the state of a pass cycle, and a programmable decoder comprising a register capable of changing the contents of the signal and the output signal and outputting a mask control signal according to the output signal of the register and each of the status signals; and masking the privileged mode signal according to the mask control signal. It also has a mask circuit that outputs the data as is.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram when the first embodiment of the present invention is applied to an emulation device.

The microprocessor 10 of this embodiment includes an internal interrupt control unit 1 which receives a privileged interrupt request signal SVI and outputs a privileged mode signal SVMO, and a plurality of status signals indicating the state of a pass cycle.

In addition to a status signal generator 2 that outputs a data write status signal WSS and a data read status signal ratio SS, it also includes a register 31 and a register 31 that can change the contents of the holding signal and output signal using a mode control signal MO. The output signal of this register 31 and the data write/status signal WSS are provided with gate circuits G, , G2.
and a programmable decoder 3 that outputs a mask control signal according to the data read/status signal R8S;
The configuration includes a mask circuit 4 which is composed of a three-manpower ANL) circuit and masks the privileged mode signal SVMO or outputs it as is in accordance with a mask control signal.

When this microprocessor 10 is applied to an emulation device, the output signal SVM of the mask circuit 4
Directly Alternate Memo IJ20A and Alternative Memo L72
The configuration is such that it is applied to the 0B chip select signal.

Next, the operation of this embodiment and the emulation device will be explained.

First, during normal operation, the holding signals W and R of the register 31 are set to @0''K by the mode control signal M0.

Since the output signals W and R of the register 31 are each "0", the output of the two-man NAND gate circuits OS and O2 is the data write status signal WSS.

Data read status 1 regardless of the state of kLss
# is output respectively, and the output of mask circuit 4 (SVM)
becomes 3 when the privileged mode signal SVMO2>E is “1”.
When all human power is "1#", @1# is output, and when the privileged mode signal sVMO becomes 0#, "O#" is output.

Therefore, when the privileged interrupt request signal SVI becomes "L", the privileged mode signal SVMO is changed to '1#' by the internal interrupt control unit 1, and this is output as is from the masking circuit 4, and the alternate memory 20A is activated. Alternate Memo! J20B is inactivated due to negative logic input, and memory access is restricted to Alternate Memo! j Performed for 20A.

Similarly, when the privileged mode signal SVMO becomes 0# after executing a return instruction from a privileged interrupt, the alternate memory '
j20A is deactivated, alternative memory 1j20B is activated, and memory access is performed to alternative memory 20a.

Here, during privileged mode, the thumb alternate memory 20
While executing the program A, the alternate memory 20A and the alternate memory 20. The following describes the procedure for transferring data between.

First, from the alternate memory 20B to the alternate memory 20A
When transferring data to, the holding signal W of the register 31,
i(, 'i are set to 10'' and '1'', respectively.

During program 7 etching, the data write status signal WSS and the data read status signal kLSS both remain at 10#, so the privilege mode signal SVMO is set to 1.
# is output as is from the mask circuit 4 and the program is fetched from the alternate memory 20A.

When a data read cycle occurs and the data write status signal WSS becomes @0#, and the data read status signal RISS becomes "1", the output of gate circuit G becomes "1" and the output of gate circuit G2 becomes 10#. Then, the output of the mask circuit 4 becomes 0'', and the substitute memory 20B is activated, and data is read from the substitute memory 20B and held.

Next, when a data write cycle occurs and the data write status signal WSS becomes '1' and the data read status signal R8S becomes '10', the gate circuit G1. The outputs of G2 are both "1#", and the privileged mode signal SVMO "1" is output as is from the mask circuit 4, which is an alternate memo! J20A is activated and the held data is written.

When transferring data from the alternate memory 20M to the alternate memory 20B, the holding signals W and R of the register 31 may be set to 1 l# and @O#, respectively.

In this way, by changing the holding signal of the register 31 using the mode control signal MO, it is possible to easily transfer data between the alternate memory 20 and the alternate memory 1J20B without a bank control circuit.

FIG. 2 is a block diagram when the second embodiment of the present invention is applied to an emulation device.

The microprocessor IOA of this embodiment receives the data write/status signal WS from the status signal control unit 2A.
s, data read/status signal R8S, and data segment 0 signal D80.

This is an example of generating stack segment signal SS, program segment signal PS, and data segment 1 signal DSI, and register 31 is generated by mode control signal MO.
A's holding signals A, B, S are programmed, and the selector 32 selects the aforementioned segment signals DS0, 88 . A programmable decoder which selects one of Pa and DSI, inverts it, outputs it, inputs it together with the output signal S of the 31 registers to a two-man OR gate circuit G3, and extracts a controlled mask control signal from this gate circuit G3. The structure is such that three people are provided to apply the mask control signal to a two-person mask circuit (ANL).

During normal operation, the holding signal S of the register 31A is @1
By setting it to ``, the output of gate circuit G3 becomes @''1.
#, and the output (SVM) of the i-framework circuit 4A becomes the same as the privileged mode signal SVMO.

Here, during privileged mode, the thumb alternate memory 20
Orientate memo while running program A! j 20
The procedure for transferring data between A and the alternative memory 20B will be described.

The selection operation of the selector 32 is as shown in Table 1, and the holding signals A, B, and 8 of the register 31A are
By setting it to 0'', the data segment O signal D8
0 and set it to ``1#'' to activate the alternative memory 20B, read and hold the data using the data read status signal SS, activate the alternative memory 20A shown in Table 1, and write the data.
Write the data held by the status signal WSS.

Data transfer from alternate memory 20A to alternate memory 20B is performed by selecting data segment 1 signal DSI.

〔Effect of the invention〕

As explained above, the present invention eliminates the need for an external bank control circuit by determining whether to mask a privileged mode signal or output it as is based on the contents of a programmable register and each status signal. Furthermore, data can be transferred between the geo-alternate memory and the substitute memory through a simple procedure, and the processing time can be shortened.

Set the data segment 0 signal DSO to 101.

[Brief explanation of the drawing]

1 and 2 are block diagrams when the first and second embodiments of the present invention are applied to an emulation device, respectively, and FIG. 3 is a block diagram when a conventional microprocessor is applied to an emulation device. be. 1... Internal interrupt control unit s 2y2A... Status signal generation unit, 3, 3A... Programmable decoder, 4.4A... Mask circuit, 10. l0AIIO
B...Microprocessor, 20m...Alternator
30... Bank control circuit, 31, 31m... Register, 32... Selector, 01 to Gs... Gate circuit.

Claims (1)

[Claims] An internal interrupt control section that receives a privileged interrupt request signal and outputs a privileged mode signal, a status generation section that outputs multiple status signals indicating the status of a pass cycle, and a mode control signal that changes the contents of hold signals and output signals. a programmable decoder that outputs a mask control signal according to an output signal of the register and each of the status signals; and a mask circuit that masks the privileged mode signal or outputs it as is according to the mask control signal. A microprocessor comprising: