JPS60209885A - Icカ−ド - Google Patents

Icカ−ド

Info

Publication number
JPS60209885A
JPS60209885A JP59066352A JP6635284A JPS60209885A JP S60209885 A JPS60209885 A JP S60209885A JP 59066352 A JP59066352 A JP 59066352A JP 6635284 A JP6635284 A JP 6635284A JP S60209885 A JPS60209885 A JP S60209885A
Authority
JP
Japan
Prior art keywords
chip
card
recess
gap
conductor pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59066352A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0416836B2 (enrdf_load_stackoverflow
Inventor
Shuji Hiranuma
平沼 修二
Yoshikatsu Fukumoto
福本 好克
Hiroshi Ohira
洋 大平
Masayuki Ouchi
正之 大内
Tamio Saito
斎藤 民雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59066352A priority Critical patent/JPS60209885A/ja
Publication of JPS60209885A publication Critical patent/JPS60209885A/ja
Publication of JPH0416836B2 publication Critical patent/JPH0416836B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
  • Credit Cards Or The Like (AREA)
JP59066352A 1984-04-02 1984-04-02 Icカ−ド Granted JPS60209885A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59066352A JPS60209885A (ja) 1984-04-02 1984-04-02 Icカ−ド

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59066352A JPS60209885A (ja) 1984-04-02 1984-04-02 Icカ−ド

Publications (2)

Publication Number Publication Date
JPS60209885A true JPS60209885A (ja) 1985-10-22
JPH0416836B2 JPH0416836B2 (enrdf_load_stackoverflow) 1992-03-25

Family

ID=13313375

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59066352A Granted JPS60209885A (ja) 1984-04-02 1984-04-02 Icカ−ド

Country Status (1)

Country Link
JP (1) JPS60209885A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62212196A (ja) * 1986-03-14 1987-09-18 カシオ計算機株式会社 Icカ−ド
JPS63290796A (ja) * 1987-05-22 1988-11-28 大日本印刷株式会社 Icカード用リードフレーム
FR2732796A1 (fr) * 1995-04-07 1996-10-11 Solaic Sa Procede pour fixer un element fonctionnel dans un corps de carte electronique a l'aide d'une matiere expansible

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5748175A (en) * 1980-07-09 1982-03-19 Philips Nv Portable identifying structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5748175A (en) * 1980-07-09 1982-03-19 Philips Nv Portable identifying structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62212196A (ja) * 1986-03-14 1987-09-18 カシオ計算機株式会社 Icカ−ド
JPS63290796A (ja) * 1987-05-22 1988-11-28 大日本印刷株式会社 Icカード用リードフレーム
FR2732796A1 (fr) * 1995-04-07 1996-10-11 Solaic Sa Procede pour fixer un element fonctionnel dans un corps de carte electronique a l'aide d'une matiere expansible

Also Published As

Publication number Publication date
JPH0416836B2 (enrdf_load_stackoverflow) 1992-03-25

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