JPS60207363A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS60207363A
JPS60207363A JP59063567A JP6356784A JPS60207363A JP S60207363 A JPS60207363 A JP S60207363A JP 59063567 A JP59063567 A JP 59063567A JP 6356784 A JP6356784 A JP 6356784A JP S60207363 A JPS60207363 A JP S60207363A
Authority
JP
Japan
Prior art keywords
substrate
dielectric
semiconductor
manufacturing process
isolated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59063567A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0147019B2 (https=
Inventor
Toshiro Usami
俊郎 宇佐美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59063567A priority Critical patent/JPS60207363A/ja
Publication of JPS60207363A publication Critical patent/JPS60207363A/ja
Priority to US07/206,903 priority patent/US4879585A/en
Publication of JPH0147019B2 publication Critical patent/JPH0147019B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1912—Preparing SOI wafers using selective deposition, e.g. epitaxial lateral overgrowth [ELO] or selective deposition of single crystal silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP59063567A 1984-03-31 1984-03-31 半導体装置 Granted JPS60207363A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP59063567A JPS60207363A (ja) 1984-03-31 1984-03-31 半導体装置
US07/206,903 US4879585A (en) 1984-03-31 1988-06-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59063567A JPS60207363A (ja) 1984-03-31 1984-03-31 半導体装置

Publications (2)

Publication Number Publication Date
JPS60207363A true JPS60207363A (ja) 1985-10-18
JPH0147019B2 JPH0147019B2 (https=) 1989-10-12

Family

ID=13232945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59063567A Granted JPS60207363A (ja) 1984-03-31 1984-03-31 半導体装置

Country Status (1)

Country Link
JP (1) JPS60207363A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01155655A (ja) * 1987-12-14 1989-06-19 Hitachi Ltd 半導体集積回路
JPH0338857A (ja) * 1989-06-30 1991-02-19 Honeywell Inc 半導体装置および半導体分離構造を製造する方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01155655A (ja) * 1987-12-14 1989-06-19 Hitachi Ltd 半導体集積回路
JPH0338857A (ja) * 1989-06-30 1991-02-19 Honeywell Inc 半導体装置および半導体分離構造を製造する方法

Also Published As

Publication number Publication date
JPH0147019B2 (https=) 1989-10-12

Similar Documents

Publication Publication Date Title
US3849216A (en) Method of manufacturing a semiconductor device and semiconductor device manufactured by using the method
US4110125A (en) Method for fabricating semiconductor devices
KR910009783B1 (ko) 반도체 장치의 제조방법
JPH02256267A (ja) 薄膜ｓｏｉ　ｃ―ｍｏｓ素子及びその製造方法
JPS6038866A (ja) 金属―酸化膜―半導体集積回路の製造方法
EP0031367A1 (en) METHOD FOR FORMING A VOLTAGE INVARIANT CAPACITOR FOR A MOS INTEGRATED CIRCUIT DEVICE.
EP0076147B1 (en) Method of producing a semiconductor device comprising an isolation region
JPS60207363A (ja) 半導体装置
US4942449A (en) Fabrication method and structure for field isolation in field effect transistors on integrated circuit chips
US4512076A (en) Semiconductor device fabrication process
US3776786A (en) Method of producing high speed transistors and resistors simultaneously
JPH0465528B2 (https=)
JPS5885560A (ja) 集積回路構成方法
US3910804A (en) Manufacturing method for self-aligned mos transistor
JPS5923476B2 (ja) 半導体装置の製造方法
US3783048A (en) High frequency transistor fabrication
JPH05190658A (ja) 誘電体分離ウエハの製造方法
JPH07249634A (ja) ゲッタリング方法およびそれを用いた半導体集積回路装置
JPS60117658A (ja) Ｍｏｓダイナミツクメモリ装置の製造方法
JPS6115372A (ja) 半導体装置およびその製造方法
JPH0744231B2 (ja) 半導体集積回路およびその製造方法
JPS60133740A (ja) 半導体装置の製造方法
JPS5928993B2 (ja) 半導体装置とその製造方法
JPH06196553A (ja) 半導体装置
JPS628029B2 (https=)

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term