EP0031367A1 - Method for forming voltage-invariant capacitors for mos type integrated circuit device. - Google Patents

Method for forming voltage-invariant capacitors for mos type integrated circuit device.

Info

Publication number
EP0031367A1
EP0031367A1 EP80901442A EP80901442A EP0031367A1 EP 0031367 A1 EP0031367 A1 EP 0031367A1 EP 80901442 A EP80901442 A EP 80901442A EP 80901442 A EP80901442 A EP 80901442A EP 0031367 A1 EP0031367 A1 EP 0031367A1
Authority
EP
European Patent Office
Prior art keywords
layer
areas
oxide
capacitor
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP80901442A
Other languages
German (de)
French (fr)
Other versions
EP0031367A4 (en
EP0031367B1 (en
Inventor
Edward R Lane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
American Microsystems Holding Corp
Original Assignee
American Microsystems Holding Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Microsystems Holding Corp filed Critical American Microsystems Holding Corp
Publication of EP0031367A1 publication Critical patent/EP0031367A1/en
Publication of EP0031367A4 publication Critical patent/EP0031367A4/en
Application granted granted Critical
Publication of EP0031367B1 publication Critical patent/EP0031367B1/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Definitions

  • This invention relates to integrated circuit semi ⁇ conductor devices having voltage invariant capacitor elements, and more particularly, to a method for making such devices.
  • inte ⁇ grated circuits such as microprocessors or devices used for digital data transmission and communication systems, such as coder-decoder circuits
  • analog to digital and/or digital to analog converters are formed from capacitor.
  • ladders comprised of large numbers of capacitors, all of which must be sized to specifications within close tolerance limits.
  • Another object of the present invention is to provide . a process for making MOS-type integrated circuit devices also having numerous capacitors wherein the dielectric layer for the capacitors is formed by an oxide regrowth during the processing steps for the MOS elements.
  • Yet another object of the present invention is to provide a process for making MOS-type integrated circuit devices having numerous transistors and relatively large capacitors wherein the specified design capacitance of the capacitors does not vary appreciably with applied voltage.
  • an integrated semi-conductor device having both .transistor and numerous capacitors is made by first using conventiona processing steps.
  • the P doped substrate is marked and treated in the con ⁇ ventional manner to provide N+ diffused regions and field oxide areas.
  • Polycrystalline silicon is formed in the gate areas for the N-channel transistors and also in
  • vapox phosphorous doped oxide
  • a contact mask of photoresist material is normally used with ultra-violet
  • CMr a controlled ambient temperature level, not only are the sharp oxide edges rounded and smoothed off, but a thi.n - oxide layer is grown in field oxide areas designated by the contact mask to form capacitors. Thereafter, another oversized contact mask is used to retain the thin oxide layer in the capacitor areas while clearing out the oxide in the desired contact areas. The thin oxide thus retained in the capacitor areas forms the required dielectric between a subsequently deposited layer of metal and the polycrystalline silicon gate of the MOS device.
  • the result is an electrically efficient capacitor whose physi ⁇ cal dimensions and electrical characteristics can be predetermined and controlled within the required close tolerances. Yet, the process for forming such capacitors on the same chip with a multiplicity of MOS transistors is completely compatible with the conventional process.
  • Fig. 1 is a view in elevation and is a section of a ⁇ partially completed semiconductor device ' in the process of being formed in accordance with the principles of the present invention
  • Fig. 2 is a view similar to Fig. 1, showing portions of an upper layer of photoresist material etched away to expose contact and capacitor areas;
  • Fig. 3 is a view similar to Fig. 2, showing a thin oxide layer in the contact and capacitor areas;
  • Fig. 4 is a view similar to Fig. 1, showing the same section of semiconductor device as it appears when com ⁇ pleted with its capacitor in place. Detailed DescriDtion of the Embodiment
  • Fig. 1 shows in cross- section, a portion of a partially fabricated N-channel MOS device 10. as it appears before a metallization layer for contacts has been applied.
  • the method steps for fabri ⁇ cating the semiconductor structure to this point are well-known and can be accomplished using conventional techniques.
  • a silicon substrate 12 typically has spaced-apart N+ diffused regions 14 and 16 that form the source and drain of an MOS device having a poly- crystalline silicon gate 18 extending between these source and drain regions.
  • Separating MOS elements on the sub ⁇ strate is a relatively thick field oxide region 20 which is also covered by a polycrystalline silicon layer 22, o having a thickness in the range of 3500 to 4500 A.
  • this layer 24 of phosphorous doped oxide (vapox) is another layer 24 of phosphorous doped oxide (vapox).
  • vapox phosphorous doped oxide
  • this photoresist layer is con- ; verted to a contact mask by forming unpolymerized photo- ; resist in selected areas so that the vapox can be removed in these selected areas by a suitable etchant to provide the MOS device contact areas.
  • this contact mask is also formed with unpolymerized areas to provide for capacitors on the poly ⁇ crystalline silicon layer in the field oxide area.
  • the structure appears as shown in Fig. 2 with a relatively small contact opening 28 over the N+ diffusion 16 and a relatively large opening 30 to the exposed polysilicon layer 22.
  • the etching process has created sharp edges on the . etched borders of the vapox layer for the openings 28 and 30. These sharp edges in the contact area are undesirable
  • a reflow cycle is performed. During this step, the entire chip is heated in an ambient of oxygen to a temperature of around 1070 degrees centigrade. At this point, as shown in Fig. 3, thin oxide layers 32 and 34 are grown in the exposed areas within the opening 28 and 30.
  • the layer 34
  • the thickness of the dielectric layer 34 can be o
  • a layer of metal . is deposited using a metallization mask (not shown) configured so that a metal contact 36 is formed in the opening 28. over an N+ diffusion region and a metal plate 38 is formed over the thin dielectric layer to complete the capacitor.
  • the capacitor thus is comprised of the top metal layer 38, the thin intermediate dielectric layer 34 and the bottom conductive layer 22 of polysilicon.
  • a suitable contact or lead extending to the top layer is not shown, but may be provided wherever convenient. Covering the entire device is a protective passivation layer 40 . which is applied in the usual manner.
  • the ' present invention provides a highly efficient and economi ⁇ cal method for producing semiconductor devices with both MOS transistors and voltage invariant capacitors.
  • the invention thus solves the problem of economically manu ⁇ facturing large numbers of multi-function chips wherein logic, memory and analog-to-digital (or vice-versa) capabi lities, using large capacitor arrays are required.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Pour un dispositif semi-conducteur a circuit integre (10) ayant une pluralite d'elements MOSFET, des condensateurs d'invariant-tension (14-16-18), ayant chacun un metal (38) comme premiere plaque et soit du polysilicium (22) soit une diffusion de drainage de source comme seconde plaque sont crees en reformant une fine couche d'oxyde (34) pour produire le dielectrique du condensateur pendant la sequence normale de traitement MOSFET.For an integrated circuit semiconductor device (10) having a plurality of MOSFET elements, invariant-voltage capacitors (14-16-18), each having a metal (38) as the first plate and either polysilicon ( 22) or a source drainage diffusion as a second plate are created by reforming a thin oxide layer (34) to produce the dielectric of the capacitor during the normal MOSFET treatment sequence.

Description

- - ETHOD FOR FORMING VOLTAGE-INVARIANT CAPACITORS FOR MOS TYPE INTEGRATED CIRCUIT DEVICE
S P E C I F I C A T I O N
Background of the Invention
This invention relates to integrated circuit semi¬ conductor devices having voltage invariant capacitor elements, and more particularly, to a method for making such devices.
In certain types of relatively large integrated circuits, it is necessary to provide numerous voltage invariant capacitors in addition to the many transistors used for logic or memory sections. For example, in inte¬ grated circuits such as microprocessors or devices used for digital data transmission and communication systems, such as coder-decoder circuits, analog to digital and/or digital to analog converters are formed from capacitor. ladders comprised of large numbers of capacitors, all of which must be sized to specifications within close tolerance limits.
Heretofore, in order to provide the necessary capacitor elements in an integrated circuit comprised of many tran¬ sistors, separate process steps were required to form external capacitor elements. This greatly increased the cost of such integrated circuits. Moreover, it adversely affected the production yield attainable because of process complications and it required integrated circuit chips of greater area. The present invention provides a solution to this problem.
Brief Summary of the Invention
It is, therefore, one object of the present invention to provide a new and improved process for making integrated circuit devices with a multiplicity of transistors and
OMPI capacitors.
Another object of the present invention is to provide . a process for making MOS-type integrated circuit devices also having numerous capacitors wherein the dielectric layer for the capacitors is formed by an oxide regrowth during the processing steps for the MOS elements.
Yet another object of the present invention is to provide a process for making MOS-type integrated circuit devices having numerous transistors and relatively large capacitors wherein the specified design capacitance of the capacitors does not vary appreciably with applied voltage.
In accordance with the principles of the invention, an integrated semi-conductor device having both .transistor and numerous capacitors is made by first using conventiona processing steps. For example, with N-channel devices, the P doped substrate is marked and treated in the con¬ ventional manner to provide N+ diffused regions and field oxide areas. Polycrystalline silicon is formed in the gate areas for the N-channel transistors and also in
; preselected regions on the upper surface of prescribed field oxide areas. At this point, the device is normally covered with a layer of phosphorous doped oxide (vapox).
During the basic silicon gate process, a contact mask of photoresist material is normally used with ultra-violet
: light to define gate and contact regions wherein the phosphorous doped oxide is thereafter etched away. Fol¬ lowing this etching step the oxide edges are nearly verti¬ cal and the corners are too sharp to allow good metal step coverage when metal is subsequently deposited. To remove these edges and allow good metal step coverage, a procedur heretofore used was to subject the wafer to heat in an ambient that causes the oxide to become slightly molten.
: This so-called "reflow" process results in sloped edges and rounded corners on the oxide material. In the present invention, prior to any reflow step, a contact mask is used to define and etch away areas where capacitors are to be formed. Now as the aforesaid reflow step is applied at
IξZEm
CMr a controlled ambient temperature level, not only are the sharp oxide edges rounded and smoothed off, but a thi.n - oxide layer is grown in field oxide areas designated by the contact mask to form capacitors. Thereafter, another oversized contact mask is used to retain the thin oxide layer in the capacitor areas while clearing out the oxide in the desired contact areas. The thin oxide thus retained in the capacitor areas forms the required dielectric between a subsequently deposited layer of metal and the polycrystalline silicon gate of the MOS device. The result is an electrically efficient capacitor whose physi¬ cal dimensions and electrical characteristics can be predetermined and controlled within the required close tolerances. Yet, the process for forming such capacitors on the same chip with a multiplicity of MOS transistors is completely compatible with the conventional process.
Other objects, advantages and features of the in¬ vention will become apparant from the following detailed description presented with the accompanying drawing.
Brief Description of the Drawing
Fig. 1 is a view in elevation and is a section of a ■ partially completed semiconductor device' in the process of being formed in accordance with the principles of the present invention;
Fig. 2 is a view similar to Fig. 1, showing portions of an upper layer of photoresist material etched away to expose contact and capacitor areas;
Fig. 3 is a view similar to Fig. 2, showing a thin oxide layer in the contact and capacitor areas; and
Fig. 4 is a view similar to Fig. 1, showing the same section of semiconductor device as it appears when com¬ pleted with its capacitor in place. Detailed DescriDtion of the Embodiment
With reference to the drawing, Fig. 1 shows in cross- section, a portion of a partially fabricated N-channel MOS device 10. as it appears before a metallization layer for contacts has been applied. The method steps for fabri¬ cating the semiconductor structure to this point are well-known and can be accomplished using conventional techniques. As shown, a silicon substrate 12 typically has spaced-apart N+ diffused regions 14 and 16 that form the source and drain of an MOS device having a poly- crystalline silicon gate 18 extending between these source and drain regions. Separating MOS elements on the sub¬ strate is a relatively thick field oxide region 20 which is also covered by a polycrystalline silicon layer 22, o having a thickness in the range of 3500 to 4500 A. Cover¬ ing the entire chip area at this point, including N+ diffused regions, the polycrystalline gates and field oxide layer, is another layer 24 of phosphorous doped oxide (vapox). This latter layer must be removed at certain locations to expose the substrate surface and provide areas for subsequent metal contacts with each MOS device. Therefore, another layer 26 of polymerized photo¬ resist material is formed over the vapox layer 24. Using conventional techniques, this photoresist layer is con- ; verted to a contact mask by forming unpolymerized photo- ; resist in selected areas so that the vapox can be removed in these selected areas by a suitable etchant to provide the MOS device contact areas. In accordance with the present invention, this contact mask is also formed with unpolymerized areas to provide for capacitors on the poly¬ crystalline silicon layer in the field oxide area.
Thus, after the aforesaid etching step, the structure appears as shown in Fig. 2 with a relatively small contact opening 28 over the N+ diffusion 16 and a relatively large opening 30 to the exposed polysilicon layer 22. At this point, the etching process has created sharp edges on the . etched borders of the vapox layer for the openings 28 and 30. These sharp edges in the contact area are undesirable
. because they prevent good metal step coverage and cause possible fractures or discontinuities within subsequently deposited metal.
Now, to form the dielectric layer for each capacitor of the integrated circuit device according to the invention, a reflow cycle is performed. During this step, the entire chip is heated in an ambient of oxygen to a temperature of around 1070 degrees centigrade. At this point, as shown in Fig. 3, thin oxide layers 32 and 34 are grown in the exposed areas within the opening 28 and 30. The layer 34
1 will eventually form the intermediate dielectric layer for the capacitor. By controlling the amount of heat, in
■ other words, the time of heat application and the tempera-
; ture, the thickness of the dielectric layer 34 can be o
-. controlled to the desired limits (e.g., 650 to 750 A).
When the aforesaid reflow cycle is complete, it is necessary"to remove the oxide layer 32 from the MOS contact area before metal can be deposited. Thus, another mask is utilized which has openings or features slightly larger (e.g., 1 micron per side) than those for the contact openings on the contact mask. This latter mask has no opening for the capacitor areas in which the thin di¬ electric layer 34 has been formed. Thus, when this latter mask is used, the oxide layer 32 is removed from all of the MOS contact areas, and thereafter, the device is ready for metallization.
During conventional techniques, a layer of metal .is deposited using a metallization mask (not shown) configured so that a metal contact 36 is formed in the opening 28. over an N+ diffusion region and a metal plate 38 is formed over the thin dielectric layer to complete the capacitor. (See Fig. 4.) The capacitor thus is comprised of the top metal layer 38, the thin intermediate dielectric layer 34 and the bottom conductive layer 22 of polysilicon. A suitable contact or lead extending to the top layer is not shown, but may be provided wherever convenient. Covering the entire device is a protective passivation layer 40 . which is applied in the usual manner.
From the foregoing, it should be apparent that the ' present invention provides a highly efficient and economi¬ cal method for producing semiconductor devices with both MOS transistors and voltage invariant capacitors. The invention thus solves the problem of economically manu¬ facturing large numbers of multi-function chips wherein logic, memory and analog-to-digital (or vice-versa) capabi lities, using large capacitor arrays are required.
To those skilled in the art to which this invention relates, many changes in construction and widely differing embodiments and applications of the invention will suggest themselves without departing from the spirit and scope of the invention. The disclosures and the description herein are purely illustrative and are not intended to be in any sense limiting.
O FI

Claims

IN THE CLAIMS :. _
1. A method for fabricating a semiconductor device having MOS transistors and voltage invariant capacitors comprising the steps of: forming on a silicon substrate, pairs of preselected diffused regions having the opposite conductivity from that of said substrate and field oxide regions adjacent said diffused regions; forming a layer of conductive material in gate areas between diffused regions of said pairs and in preselected areas on said field oxide regions; covering said substrate, including said diffused regions, said areas of conductive material and said field oxide, with a layer of phosphorous doped oxide; forming openings in said layer of phosphorous doped oxide, including contact areas, aligned with preselected diffused regions and also, preselected capacitor areas of said layer of conductive material on said field oxide; reflowing said phosphorous doped oxide by heating in an oxygen ambient to reduce sharp edges at said openings and simultaneously grow a thin oxide layer in said contact and capacitor areas; removing the thin oxide layer in said contact areas; providing a layer of metal in said contact areas and also in said capacitor areas, thereby forming the upper conductor plate of the capacitor.
2. The method as described in Claim 1, wherein said o thin oxide layer to a thickness between 650-750 A.
3. The method as described in Claim 1, wherein said layer of conductive material with polycrystalline silicon, o having a thickness in the range of 3500 to 4500 A.
4. The method as described in Claim 1, wherein the removal of the thin oxide layer in said contact areas is accomplished with a mark having openings for the contact areas that are slightly larger than the openings in the mark for originally forming the openings in the phospho¬ rous doped oxide.
OM
EP80901442A 1979-07-06 1981-01-26 Method for forming voltage-invariant capacitors for mos type integrated circuit device Expired EP0031367B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US55170 1979-07-06
US06/055,170 US4261772A (en) 1979-07-06 1979-07-06 Method for forming voltage-invariant capacitors for MOS type integrated circuit device utilizing oxidation and reflow techniques

Publications (3)

Publication Number Publication Date
EP0031367A1 true EP0031367A1 (en) 1981-07-08
EP0031367A4 EP0031367A4 (en) 1984-04-27
EP0031367B1 EP0031367B1 (en) 1986-08-27

Family

ID=21996093

Family Applications (1)

Application Number Title Priority Date Filing Date
EP80901442A Expired EP0031367B1 (en) 1979-07-06 1981-01-26 Method for forming voltage-invariant capacitors for mos type integrated circuit device

Country Status (7)

Country Link
US (1) US4261772A (en)
EP (1) EP0031367B1 (en)
JP (1) JPS6335107B2 (en)
DE (1) DE3038773C2 (en)
GB (1) GB2067014B (en)
NL (1) NL190210C (en)
WO (1) WO1981000171A1 (en)

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FR2526225B1 (en) * 1982-04-30 1985-11-08 Radiotechnique Compelec METHOD FOR PRODUCING AN INTEGRATED CAPACITOR, AND DEVICE THUS OBTAINED
US4419812A (en) * 1982-08-23 1983-12-13 Ncr Corporation Method of fabricating an integrated circuit voltage multiplier containing a parallel plate capacitor
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US5202751A (en) * 1984-03-30 1993-04-13 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
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IT1224656B (en) * 1987-12-23 1990-10-18 Sgs Thomson Microelectronics PROCEDURE FOR THE MANUFACTURE OF CAPACITORS INTEGRATED IN MOS TECHNOLOGY.
DE4343983C2 (en) * 1993-12-22 1996-09-05 Siemens Ag Integrated semiconductor circuit with capacitors of precisely defined capacitance and method for producing such a circuit
JP3474332B2 (en) * 1994-10-11 2003-12-08 台灣茂▲夕▼電子股▲分▼有限公司 Self-tuning capacitor bottom plate local interconnect method for DRAM
US5686751A (en) * 1996-06-28 1997-11-11 Winbond Electronics Corp. Electrostatic discharge protection circuit triggered by capacitive-coupling
KR101677701B1 (en) * 2015-11-04 2016-11-21 충북대학교 산학협력단 Artificial Translucent Chip Having Non Halogen and Method for Manufacture of the same

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Also Published As

Publication number Publication date
GB2067014A (en) 1981-07-15
JPS6335107B2 (en) 1988-07-13
WO1981000171A1 (en) 1981-01-22
EP0031367A4 (en) 1984-04-27
NL190210C (en) 1993-12-01
EP0031367B1 (en) 1986-08-27
DE3038773C2 (en) 1985-05-02
DE3038773T1 (en) 1982-02-11
US4261772A (en) 1981-04-14
NL190210B (en) 1993-07-01
JPS56500631A (en) 1981-05-07
GB2067014B (en) 1983-06-15
NL8020272A (en) 1981-03-31

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