GB2106315A - >Manufacture of integrated circuits - Google Patents

>Manufacture of integrated circuits Download PDF

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Publication number
GB2106315A
GB2106315A GB08220264A GB8220264A GB2106315A GB 2106315 A GB2106315 A GB 2106315A GB 08220264 A GB08220264 A GB 08220264A GB 8220264 A GB8220264 A GB 8220264A GB 2106315 A GB2106315 A GB 2106315A
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Prior art keywords
layer
polysilicon
silicon
portions
silicon nitride
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Application number
GB08220264A
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GB2106315B (en
Inventor
Gary Lee Heimbigner
Gordon Charles Godejahn
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Boeing North American Inc
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Rockwell International Corp
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Priority claimed from US05/909,886 external-priority patent/US4277881A/en
Priority claimed from US05/913,182 external-priority patent/US4221044A/en
Application filed by Rockwell International Corp filed Critical Rockwell International Corp
Publication of GB2106315A publication Critical patent/GB2106315A/en
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Publication of GB2106315B publication Critical patent/GB2106315B/en
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
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    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract

A VLSI device is manufactured on monocrystalline silicon and comprises FET's (S,G,D), polysilicon connections 102 and diffused connections 101. The silicon is oxidized to form a first oxide layer which is covered with a first nitride layer. The latter is selectively removed to leave FET and diffused connection areas 100, 101 masked. Unmasked areas are oxidized to field oxide and doped polysilicon is applied and oxidized to a second oxide layer which is covered with a second nitride layer. This is oxidized to an oxynitride layer which is doped. Masking and etching steps remove the oxynitride and second nitride except where there are to be polysilicon contacts 103 and remove the polysilicon except for the lines 102 including the gate electrodes G and then remove the first nitride and oxide except for the FET area 405 and diffused connection contact area 406. The device is completed by batch removal steps and applying conducting lines to the polysilicon and diffused contact areas Pc, Nc. The line 101 is doped by driving in the dopant from the silicon oxynitride layer. <IMAGE>

Description

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GB 2 106 315 A 1
SPECIFICATION
Manufacture of integrated circuits
The invention relates to the manufacture of integrated circuits, more particularly to the fabrication of very large scale integrated circuit (VLSI) having increased density and reliability and containing FET devices, polysilicon and diffused N+ interconnect lines and metallized interconnect lines interfacing with the polysilicon and N+ diffused lines.
The semiconductor art has been concerned with reducing the size and power consumption of individual devices and integrated circuits in order to increase the logic power of these circuits per unit area. A particular effort has been extended in the area of monolithic random access memories (RAM's) and read only memories (ROM's) having very large memory capacity. Many things have been done over the years in an attempt to reduce the size of devices and improve tolerances with which they are fabricated. Such efforts have included, inter alia, fine line lithography, improved mask generation and alignment machines, improved tolerances on mask alignment, and self-aligned gates. These techniques have reduced the area required for the fabrication of individual FET devices used in these integrated circuits.
However, because of alignment tolerances, the FET devices must be designed with larger geometry than they would have to be if perfect mask alignment were obtained. Furthermore, because of alignment tolerances, the FET devices must be spaced further apart than otherwise necessary in order to allow for the misalignment in the formation of the inter-connection lines. Consequently, there is a need for an improved integrated circuit fabrication technique for producing VLSI circuits including FET devices and conducting lines having reduced sensitivity to mask alignment.
Summary of the invention
In a process in accordance with the invention, both the gate oxide layer of the active FET devices of the integrated circuit as well as a silicon nitride layer are formed on the surface of a silicon substrate. Both layers are surrounded by a field oxide layer and simultaneously formed on areas in which diffused N+ conducting lines are to be formed. A poly-silicon layer formed on the nitride layer, is delineated to provide the polysilicon conductor of the gates of the FET devices as well as being delineated for additional interconnection lines and then may be partially oxidized in reliance on the masking effect of the nitride layer. This affords minimal oxide layer thickness on the gate polysilicon layer and again contributes to the reduced device size. Subsequently, silicon nitride, silicon oxynitride, silicon dioxide, and photoresist layers are then employed in various masking and selective etch processes to provide self-aligned gates and contacts for FET devices and self-aligned interconnection interfaces. The fact that silicon nitride,
silicon oxynitride, silicon dioxide, photoresist, and silicon all have different etch removal rates when exposed to various etching processes makes it feasible for the number of masking steps to be reduced in comparison to prior art methods and further allows self-alignment features not previously obtainable. In addition, the method described below in accordance with the present invention allows the simultaneous doping of two or more regions. This is advantageous in that the resulting integrated circuit device has more uniform characteristics.
The processes of the present invention permit direct contact to the gate electrode as well as floating gate contact configurations. Diffused conducting lines permit a first level inter-' connect to source and drain as well as being compatible with a direct gate contact configuration. Conversely a remote gate contact with direct source and drain contacts may also be afforded. Theoretically, simultaneous and direct source, gate, and drain contacts may be provided although current technology limits the miniaturization of device size and configuration by virtue of the dimensions of the conducting lines in such a simultaneous direct contact device configuration.
These and other objects and advantages of the invention will be apparent from the following detailed description of certain preferred embodiments thereof.
Brief description of the drawings
Fig. 1 illustrates a partial plan view of the surface of the semiconductor wafer to be processed in accordance with the present invention. The cross-hatched portions correspond to the various photolithographic masks used in performing the process in accordance with the present invention. Section lines A—A, B—B and C—C are provided so as to reference Figures 2 through 11,13, and 15—17.
Figs. 2—17 illustrate partial plan and cross-sectional views of the semiconductor wafer illustrated in Fig. 1. These figures illustrate in chronological order the semiconductor wafer after having undergone the various steps enumerated below.
Fig. 18 illustrates an electrical integrated circuit which may be a portion of a VLSI circuit.
Fig. 19 is the equivalent electrical schematic of the structure of Fig. 18.
Description of the preferred embodiments First preferred embodiment
The following description of the first preferred embodiment provides the chronological sequence of process steps performed in accordance with the present invention. Each of these process steps has been given a numerical designation for ease of identification.
Step 1. The process starts with a semiconductor wafer having a monocrystalline device quality layer of P-type silicon. The wafer can be either of monolithic configuration or may be a
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composite wafer having a silicon layer 1 on top of a substrate of different material (e.g. silicon-on-sapphire composite). In addition, while the process has been illustrated as beginning with P-type substrate it is of course understood that the process is amenable to N-type substrates as well. The dopant materials used in such a case would be different from those indicated below. The wafer is first cleaned by conventional means to remove the normal surface impurities. Fig. 2 illustrates a partial cross-sectional view of a monolithic silicon wafer 1.
Step 2. The now cleaned wafer is subjected to a conventional oxidation process (e.g., thermal oxidation) which serves to form a silicon dioxide layer 5 on top of the silicon layer 1. A typical thickness for the silicon dioxide layer 5 would be somewhere on the order of 600 A. Fig. 3 illustrates a partial cross-sectional view of the wafer after having been processed in accordance with this step.
Step 3a. A first nitride layer 6 is deposited on top of the silicon dioxide layer 5 using conventional nitride deposition techniques. The nitride layer 6 deposited may typically be on the order of 575 A thick.
Step 3b. The wafer is then optionally subjected to a short steam cycle to form a thin silicon oxynitride layer 400 on top of the silicon nitride layer 6. This oxynitride layer 400 allows for greater adherence of the photoresist regions 100 and 101 applied in step 4a below. However, it has been found that this oxynitride layer is not absolutely necessary. Fig. 4 illustrates the wafer after being processed in accordance with step 3b.
Step 4a. A photoresist layer is then deposited on top of the silicon nitride and oxynitride layers and this photoresist layer is exposed to actinic radiation through a N-mask. The N-mask is substantially transparent to actinic radiation except for a plurality of protective regions (i.e. —100 and 101 as illustrated in Fig. 1) which are opaque to the actinic radiation. The photoresist regions 100 and 101 which have been shielded by the opaque protective regions of the N-mask are nonsoluble in an appropriate photoresist developer while the remainder of the photoresist which had been exposed to the actinic radiation becomes soluble in the same appropriate photoresist developer. Thus, by placing the wafer in an appropriate developer solution, the photoresist layer is selectively removed in accordance with the configuration of the protective regions 100 and 101 of the N-mask.
Step 4b. The wafer is then subjected to sequential selective oxynitride and nitride removal processes using removal processes that attack the oxynitride layer 400 and the nitride layer 6 but do not attack the photoresist layer. Thus, the oxynitride layer 400 and the nitride layer 6 are selectively removed from the entire surface of the silicon dioxide layer at all regions except where protected by the remaining regions 100 and 101 of the photoresist layer. A plasma etching process is but one example of such a selective nitride
GB 2 106 315 A 2
removal process. The remaining oxynitride and nitride regions cover those areas of the wafer in which the FET devices will be located (i.e. —
region 100) and further cover the areas of the chip in which N+ diffused interconnecting lines will eventually be formed i.e. — region 101).
Figs. 1, 5 and 6 illustrate the two photoresist layer regions 100 and 101 which the N mask has protected.
Step 5. The wafer is then subjected to a dopant implant step in which dopant ions (e.g. — boron ions) are implanted into the surface of the entire silicon layer except for those areas directly underneath the remaining photoresist regions 100 and 101. The photoresist layer is a shield against the dopant ions. The arrows 150, in Fig. 6, indicate the path of the dopant ions. After the ion implantation step, the photoresist regions 100 and 101 are removed by conventional techniques (e.g., sulphuric/persulfate acid bath). The ion implantation serves to dope the silicon substrate 1 in those regions which will ultimately be used for isolating the active devices and the N+ interconnecting lines.
Step 6. The wafer is then subjected to an annealing process which serves to stabilize and equalize the above noted ion implantation step. This annealing step may be combined with the field oxidation step (step 7) described below.
Step 7. The wafer is then subjected to a thermal field oxidation process which thermally oxidizes the surface of the field portions of the silicon layer 1 except under the remaining portions of the silicon oxynitride and nitride layers 400 and 6. The silicon nitride layer portions 6 serve to protect the underlying silicon from thermal oxidation. Typically, the thermal oxidation process can be used to form silicon dioxide layers 2, 3, and 4 having a thickness on the order 1 5,500 A. In addition, such a thermal oxidation process of sufficient duration to produce a 1 5,500 A silicon dioxide thickness will produce an oxynitride layer 7 having a 200 A thickness. The oxynitride layer 7 combines with the optional oxynitride layer 400 to form a single oxynitride layer. This single combined layer will subsequently be referred to as oxynitride layer 400 for convenience. The thermally grown silicon dioxide field oxide layers 2, 3 and 4 will ultimately serve to electrically isolate the FET devices and N+ diffused interconnections. Fig. 7 illustrates a cross-sectional view of the semiconductor wafer illustrated in Figure 1 after having undergone processing steps 1 to 7. Note that the thick field oxide regions 2, 3 and 4 have been grown everywhere but in regions 8 and 10. Region 8 illustrates the cross-section taken along section line A—A of Figure 1 while area 9 illustrates a cross-section taken along section line B—B of Figure 1. Area 10 is a cross-sectional view taken along section line C—C of Figure 1. In areas 8 and 10, the silicon substrate 1 is covered by the gate oxide layer 5, the silicon nitride layer 6, and the oxynitride layer 400. Present but not shown in Fig. 7 are the regions of silicon layer 1 underneath
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the field oxide layer 2, 3, and 4 which have dopant ions which have been implanted by step 5. While the process indicates the use of a nitride layer, it is understood that other materials having characteristics similar to silicon nitride may be substituted.
Step 8. A layer of polycrystalline silicon (polysilicon) 11 is then deposited on top of the surface of the water. Typically, a phosphorus or arsenic doped polysilicon is used and a polysilicon layer 11 having a thickness on the order of 8,000 A is deposited. The polysilicon layer 11 will eventually be selectively removed so as to form the gate electrodes and remote gate interconnect lines.
Step 9. The polysilicon layer 11 is then oxidized using conventional oxidation techniques (e.g. steam treatment) to form a layer of silicon dioxide 12 on top of the polysilicon layer 11. Typically, a silicon dioxide layer 12 of between 600 to 1,200 A is formed.
Step 10. The wafer is then subjected to a second nitride deposition process which deposits a layer of silicon nitride 13 on top of the silicon dioxide layer 12. Typically, this second nitride layer 13 is on the order of 400 A thick. Fig. 8 illustrates the wafer after being processed in accordance with step 10.
Step 11. A photoresist layer 401 is then applied on top of the second nitride layer 13 and exposed to actinic radiation through a PC-mask. This mask has its opaque protective regions 103, illustrated in Fig. 1, configured so as to render the photoresist layer insoluble at that region on the wafer wherein the polysilicon contact to a subsequently formed metalized interconnect line is to be located. The photoresist layer is then developed with the appropriate photoresist developer solution to remove the unwanted photoresist layer.
Step 12a. The wafer is then subjected to a selective nitride layer removal process (e.g., plasma etching) to selectively remove all of the second nitride layer 13 except those portions protected by the remaining photoresist layer 401.
Figure 9 illustrates a cross-sectional view of a semiconductor wafer 1 of Figure 1 after having undergone processing up to and including step 12a in accordance with the present invention. The polysilicon layer 11 is covered at the PC contact site by a silicon dioxide layer 12, the second silicon nitride layer 13, and the photoresist region 401 which covers the illustrated polysilicon contact.
Step 12b. The remaining photoresist layer 401 is then removed. Thus, the PC contact area is protected by the second nitride layer 13, while the remainder of the wafer has a surface layer of silicon dioxide 12.
Step 13. Apply a layer 402 of material such as boron doped chemically vapor deposited silicon dioxide (Silox) which has a lower etch rate than oxynitride layers when exposed to the same etchants.Other substitute materials may be used.
Step 14a. Apply a layer of photoresist to the silicon wafer and expose same to actinic radiation through a G-mask and then remove the unwanted photoresist layer using the appropriate developer solution. This leaves regions 403 and 404 of photoresist 14 atop the exposed Silox layer 402 atop the second nitride layer 13 and silicon dioxide layer 12 at those locations where the polysilicon interconnect and polysilicon gate lines are located (illustrated as area 102 in Fig. 1). Fig. 10 illustrates a partial cross-sectional view of the wafer after being processed in accordance with step 14. Note that the G-mask resist areas 403 and 404 are juxtaposed directly above the gate and polysilicon line regions. Also note that as illustrated in Fig. 1, because of the fact that the PC mask and N mask regions 103 and 100 are larger than the polysilicon line and gate mask 102, the alignment tolerance of the G mask is not stringent.
Step 15a. Using a selective oxide removal process, selectively remove those portions of the silox layer 402 not protected by the G-mask resist regions 403 and 404.
Step 15b. Using a selective nitride removal process (e.g., plasma etch), selectively remove those portions of the second silicon nitride layer 13 not protected by the photoresist regions 403 and 404.
Step 15c. Using a selective oxide removal process, selectively remove those portions of the silicon dioxide layer 12 not protected by the G-mask resist regions 403 and 404.
Step 15d. Using a selective polysilicon removal process selectively remove those portions of the polysilicon layer 11 not protected by the photoresist regions 403 and 404. Fig. 11 illustrates a partial cross-sectional view of the wafer after having undergone processing in accordance with step 15d. Note that the G-mask region in area 8 (i.e. — the gate region) comprises the silicon 1, covered by silicon dioxide 5, silicon nitride 6, and silicon oxynitride 400, covered in turn by polysilicon 11, silicon dioxide 12, Silox 402, and finally covered by the G-mask resist region 403. The G-mask region in area 9 (i.e. — the PC polysilicon contact region) consists of the silicon 1 covered by the field oxide 3, covered by polysilicon 11, silicon dioxide 12, covered in turn by the second nitride layer 13, the Silox 402, and finally covered by the G-mask resist region 404. The source, drain, and N+ diffused line areas consist of the silicon 1 covered by silicon dioxide 5, silicon nitride 6, and silicon oxynitride 400.
Step 15e. Remove the remaining portions of the photoresist layer using conventional techniques.
Step 16. Apply a layer of photoresist to the silicon wafer and expose same to actinic radiation through a C-mask and then remove the unwanted photoresist layer using the appropriate developer solution. This leaves a layer of photoresist atop the wafer at those regions shown in cross-hatch lines as regions 405 and 406 of Fig. 12. Areas 501—506 respectively illustrate the polysilicon line 501, source 502, gate 503, and drain 504 of
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an FET device, N+ diffused line 505 and N+ contact 506. These regions are over areas which will ultimately be the contact interface between the source and drain lines, (i.e. — region 405) the 5 diffused N+ lines (i.e.— region 406) and the subsequently formed metalized interconnection lines. As illustrated in Fig. 1, the C mask areas 405 and 406 do not require stringent placement alignment tolerances, since they are larger than 10 the areas to be protected.
Step 17a. Using a selective oxynitride removal process, selectively remove those portions of the oxynitride layer not protected by the photoresist regions 405 and 406.
1 5 Step 17b 1. Using a selective nitride removal process selectively remove those portions of the nitride layer not protected by the photoresist regions 405 and 406.
Step 1 7b2. Remove the underlying oxide 20 exposed by the nitride removal process in step 17b 1.
Step 17b3. Deposit a phosphorus or arsenic dopant on the surface of the wafer and perform a dopant drive process to dope the N+ line. 25 Step 17c. Remove the photoresist regions 405 and 406 using conventional techniques.
Step 17d1. Oxidize the exposed polysilicon interconnect line and N+ interconnect line using conventional oxidization techniques (e.g., steam 30 processing) to fabricate a thick silicon dioxide layer 15 thereon. Typically, a 4000 to 5000 A thick layer may be produced. It is important to note that in region 8 and in the region 10 protected in the earlier steps by photoresist 35 regions 405 and 406, the oxynitride layer 400 and underlying nitride layer 6 protect the underlying source, drain and N+ contact areas from oxidation. Note that the sides of the polysilicon gate and line, since they are not protected 40 by a silicon nitride or oxynitride layer, are oxidized simultaneously with the formation of oxide layer 15. These additional oxidized side areas 475 are extremely important since their presence prevents the subsequently applied metalized inter-45 connection to the source, drain, and N+ contacts, from shorting to the sides of the polysilicon gate and line if misalignment should occur. The oxidation process also partially oxidizes the top of polysilicon layer 11 not protected by the second 50 silicon nitride layer. Figure 13 illustrates dopant ions present in the Silox layer 402. Fig. 13 illustrates the wafer cross-section after being processed in accordance with step 17.
Step 18. Subject the wafer to a dip etch 55 process to remove all of the exposed Silox layer 402. Alternatively, (see Alternate step 18 below) the wafer can be subjected to a C2-mask step to leave a Silox layer covering the poly line except at the PC poly line contact site. Fig. 14 illustrates 60 such a C2-mask. The use of the Cz mask step, as described below in Alternate step 18, leaves the Silox layer 402 covering the polysilicon line except at the PC contact site. Because of the presence of the Silox layer, the polysilicon line 65 would not be doped by step 20. However,
additional doping of the already doped polysilicon may not be required. For the remaining discussion, it will be assumed that step 18 has been performed instead of Alternate step 18.
Alternate Step 18. A photoresist layer is applied to the surface of the wafer and exposed to actinic radiation through a C2-mask and the unwanted portions of the photoresist layer are then removed using an appropriate developer solution. The C2-mask contains opaque protective regions so as to leave a photoresist layer over the entire surface except at those areas in which polysilicon line contacts are to be formed. The exposed Silox layer 402 is then removed and the C2-mask photoresist layer removed, leaving a N+ contact area protected by a nitride/oxynitride button.
Step 19a. Subject the wafer to a selective oxynitride removal process (e.g., wet or plasma etching) to selectively remove the exposed oxynitride layer off of the source, drain, and N+
line contact located under the oxynitride layer.
Step 19b. Subject the wafer to a nitride removal process (e.g., plasma or wet etching) to selectively remove those portions of the first and second nitride layers covering the source, drain, N+ line contacts and polysilicon line contact sites. Fig. 15 illustrates a cross-sectional view of the silicon wafer 1 after having undergone the nitride removal process of step 19b. Note that the source, drain, polysilicon contact and N+ contact now all have just a thin oxide layer cover. Dip etch the wafer to remove the oxide layer covering the regions to be doped.
Step 20. Deposit a layer of phosphorous using, for example, conventional P0C13 techniques or deposit arsenic using a layer of arsenic doped Silox or polysilicon. Using conventional techniques, the wafer is then subjected to a doping process which drives the phosphorus or arsenic ions simultaneously into the source, drain, N+ contact and polysilicon contact regions.
Step 21. Deglaze if a conventional P0C13 doping procedure is performed, by a dip (batch) etching procedure. This dip etching serves also to remove any thin oxide layer covering the contact sites formed in step 20. Fig. 1 6 is a partial cross-sectional view of the wafer after having been processed in accordance with step 21.
Step 22. Apply a Silox layer 410 to the surface of the wafer and densify by normal densification techniques. Then apply a layer of photoresist and expose same to actinic radiation through a second C-mask and then remove the unwanted photoresist layer using the appropriate developer solution. The second C-mask has opaque portions arranged so as to leave unprotected the previously formed contact sites. The wafer is then subjected to a selective oxide removal process (e.g., etching) so as to provide windows into the contact sites. Note that the oxide removal process may be used to etch a window through both the Silox layer 410 and any remaining portions of the silicon dioxide layer 5. The second C-mask does not require stringent alignment tolerances since
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all the contact regions have already been formed and are separated by insulating materials, and since all of the edges 475 of the polysilicon line 11 are protected by an insulating oxide.
5 Step 23. Apply a metallization layer 20 and a photoresist layer and expose same to actinic radiation through a M-mask and then remove the unwanted photoresist layer using standard removal techniques. The M-mask is arranged to 10 leave protective portions of photoresist layer on those areas of the conductive metalization layer wherein interconnections to the contacts are to be formed. The wafer is then subjected to a standard metalization layer removal process (e.g., 15 etching) to remove the unwanted metalization layer and the wafer is then subjected to a photoresist removal process. Other materials (e.g., — polysilicon could be substituted for the metalization layer 20.
20 Step 24. The wafer is then exposed to a hydrogen annealing process to anneal the previously formed metalization layer. Fig. 17 illustrates the silicon wafer of Fig. 1 after this step.
25 Step 25. The wafer is then subjected to the usual finishing procedures (e.g., sandblasting, cleaning, passivating) in accordance with conventional procedures.
Alternate embodiment I
30 This embodiment is essentially a modification of the first embodiment described above with the distinction being that the boron doped Silox deposition step (Step 13) is replaced by the boron doping of an oxynitride layer (greater than 80 A 35 thick) formed over the second silicon nitride film. In other words, after step 10 of the first embodiment, we would add:
Step 10a. Steam nitride layer to form an oxynitride layer thereon.
40 Step 10b. Subject the wafer to a boron deposition process (e.g., boron deposition at 1030° with BBr3) to deposit boron ions on the just formed oxynitride layer.
Step 13 of course would be deleted and in 45 Steps 15a and 18 we would of course selectively etch the boron doped oxynitride layer rather than a Silox layer. The remaining processing steps would be identical to those of the first embodiment.
50 Alternate embodiment II
This embodiment is an improvement over the embodiments described above in that a layer of silicon nitride is used instead of the boron doped Silox or boron doped oxynitride layers. Since the 55 silicon nitride layer (designed silicon nitride III) may be as thin as 400 A, one can more accurately etch the polysilicon lines than, for example, when using the Silox or nitride II layer which must be thicker typically than the silicon nitride layer. 60 Since the processes of this embodiment are quite similar to those of the first embodiment, the different processes described below with regard to this embodiment will not be stated in such comprehensive detail as that provided for the first embodiment.
Step 1. Perform the steps of the first embodiment up to and including Step 10 (deposit silicon nitride layer II).
Step 2. Steam silicon nitride II layer to form a layer of silicon oxynitride (e.g.,—greater than 80A thick).
Step 3. PC mask
Step 3a. Remove unwanted resist so as to leave resist on the PC mask as in first .embodiment.
Step 3b. Etch the unprotected oxynitride layer.
Step 3c. Remove the exposed field nitride layer using, for example, a plasma etch process.
Step 4. Deposit a silicon nitride layer III (e.g., 400 A thick), and steam the nitride layer to form a silicon oxynitride layer.
Step 5. G mask.
Step 5a. Remove unwanted photoresist layer so as to leave resist over the PC strip and over the polysilicon interconnection lines.
Step 5b. Etch the exposed oxynitride off of the field areas.
Step 5c. Etch the nitride off of the field using, for example, a plasma etch process so as to leave nitride covering the oxynitride strip on the PC pad and over the oxidized polysilicon interconnection lines.
Step 5d. Remove the remaining photoresist and etch the exposed oxide and polysilicon lines using, for example, wet or dry plasma etching techniques.
Step 6. C mask (as in first embodiment).
Step 6a. Remove unwanted photoresist so as to leave resist areas on the N+ diffused line contact region and the source and drain regions.
Step 6b. Using a selective removal procedure, (e.g.— selective etch) etch the oxynitride layer off of the N+ lines.
Step 6c. Remove the remaining photoresist layer using conventional methods.
Step 6d. Plasma etch the silicon nitride off of the N+ lines and the polysilicon lines and then dip etch the entire wafer to remove the underlying silicon dioxide layer so as to expose the bare silicon, thus exposing the N+ and polysilicon lines.
Step 7. Deposit arsenic or phosphorus using conventional techniques or alternatively implant arsenic or phosphorus ions using ion implant techniques. Deglaze the wafer if necessary.
Step 8. Drive the junctions in the N+ lines and oxidize the N+ lines and polysilicon lines to any desired oxide thickness. For example, if a 5,000A thick oxide layer is desired, a 90—120 minute steam process would be desirable for phosphorus type doping. A different cycle would be necessary for arsenic doping to achieve a similar result.
Step 9. Dip etch oxynitride layer off the contact sites.
Step 10. Plasma etch the exposed nitride layer off of the contact sites.
Step 11. Phosphorus or arsenic dope the source, drain, N+ contacts and PC contacts as in
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the first embodiment. Note that in this embodiment, the N+ and polysilicon lines are doped in a separate step.
Step 12. Continue with Step 21 of the first 5 embodiment and complete the processing of the wafer.
Alternate embodiment III
As an extension of alternate embodiment II, the following improved variation is offered: 10 At Step 4 of alternate embodiment II, a photoresist layer can be substituted for the third silicon nitride layer and left in place after the G masking steps (Steps 5 and 5a of alternate embodiment II). After Step 5b of alternate 1 5 embodiment II is completed, the oxynitride layer is removed, and the polysilicon layer plasma etched to delineate the polysilicon lines. The plasma etching method usually improves the resist adherence through perhaps an additional 20 polymerization. This is a highly desirable feature, since in this alternate embodiment, the G mask resist is left in place as a protective covering for the polysilicon contact stripe PC of oxynitride coated nitride during the C layer etching step of 25 the oxynitride layer over the N+ lines (i.e., the resist for the C layer is next applied over the resist remaining from the G layer masking steps. The processing then continues to Step 6b of alternate embodiment II and the oxynitride layer is etched 30 off the N+ fines. Subsequently, in Step 6c the resist from both the C and the G masking operations is removed. Step 6d is then performed to plasma etch the first silicon nitride layer from the N+ lines. The wafer is then dip etched to 35 remove the underlying oxide layer and the processing proceeds to Step 7 of alternate embodiment II and continues to completion of the wafer.
Alternate embodiment IV
40 In order to reduce the deleterious effect of the first silicon nitride regions edge lifting and cracking after Step 7, (i.e. the field oxidation step of ali the various embodiments) the first silicon nitride layer can be stripped by a plasma etching 45 technique after the field oxidation, and then the wafer can be subjected to a wet etching to remove the underlying oxide layer. A new gate oxide and gate silicon nitride layer are then regrown. For example, the wafer is first processed 50 in accordance with Steps 1 through 7 of the first embodiment. The wafer is then processed as follows:
Step 2a. Remove the oxynitride layer off the N mask regions by conventional etching techniques 55 (e.g., wet acid etching).
Step 2b. Remove the exposed silicon nitride layer by conventional plasma etching techniques.
Step 2c. Remove the exposed underlying oxide layer if desired.
60 Step 2d. Subject the wafer to a reoxidation process to regrow the gate oxide to a thickness of about 600A. It is noted that the removal of the underlying oxide (Step c) will preferentially attack the "bird beak" formed during the original field oxidation step and reduce its height and stress contributing factors. This preferential attacking of the "bird beak" oxide occurs because the "bird beak" oxide is more highly stressed. By reoxidizing the intended gate region and re-depositing a silicon nitride layer, the resultant oxide/nitride sandwich layer has a better integrity and fewer defects. Furthermore, by regrowing the oxide and then depositing with silicon nitride, the field oxide regions are covered with an additional silicon nitride layer to provide additional isolation of the polysilicon lines and the field oxide. Furthermore, the silicon nitride layer atop the field oxide provides a different type of surface for nucleating the polysilicon layer to be applied later and usually produces a finer grained polysilicon texture.
Step 2e. Subject the wafer to a steam treatment to convert the exposed nitride film to an oxynitride. An added advantage of this newly formed silicon nitride layer is that it will prevent oxide growth of the field regions during subsequent diffusion steps and act as an etch stop during later oxide etch steps. The wafer is then processed in accordance with the remaining steps of the various embodiments (i.e., deposit a layer of polysilicon as in Step 8).
Alternate embodiment V
An improvement can be made in the above noted embodiments by the use of a doped chemically vapor deposited silicon dioxide layer (Silox). The Silox layer (doped either with phosphorus or arsenic for example) is used as a diffusion source for all of the N+ areas and enables the simultaneous diffusion of the source, drain, N+ lines, polysilicon lines, and polysilicon contacts. The doped Silox is left in place after the dopant diffusion process to serve as an electrical insulating layer. Particularly, it serves as an electrical insulator between the polysilicon lines and the metalized interconnection lines overlying the polysilicon lines. Another feature of this embodiment is the elimination of the first C masking step since a later C mask over the doped Silox layer will be used to open contacts to all of the desired contact regions. This C mask will have enlarged contact geometries, (for example, larger than the width of the polysilicon lines or N+
lines), to enable a non-stringent C mask positional alignment tolerance. Additionally, the polysilicon lines are oxidized to form for example 5,000A of silicon dioxide after the G masking step used to delineate the polysilicon lines but before the nitride layer is selectively removed from the N+ lines, source, drain, and polysilicon contacts. The basic sequence of masks used in this embodiment are: N. PC, G, C, and M. A short description of the sequence of steps in this embodiment is noted below:
Proceed to process the wafer in accordance with alternate embodiment IV as noted above up to and including the G mask process. After the photoresist layer has been exposed to the G layer
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mask to delineate the polysilicon lines, the wafer is dip etched to remove the oxynitride layer on the PC nitrided surface pad and the wafer is then subjected to a piasma etching process to remove 5 the nitride extensions beyond the PC mask stripe.
The wafer is then subjected to a wet etching process to remove the field oxide layer on top of the poly layer and the wafer is then plasma etched to remove the polysilicon field. As an 10 alternative to the plasma etching process, the remaining photoresist layer can be removed and the wafer subjected to a wet etching process to remove the polysilicon field.
The polysilicon lines are now delineated and 15 after removing the remaining photoresist layer (if necessary) the polysilicon lines are oxidized to form a silicon dioxide layer thereon of typically between 3,000 and 5,000A thick.
The wafer is then subjected to a dip etching 20 process to remove all of the oxynitride layer over the N+ lines. The oxynitride is also removed by the same process from the source and drain regions and the polysilicon contact sites.
The wafer is then subjected to a plasma 25 etching process to remove the protective nitride I layer from the N+ lines, source, drain, and polysilicon contacts. Accordingly, the underlying oxide layer is dip etched. A layer of doped Silox (for example phosphorus doped) is then deposited 30 and the wafer subjected to a drive process to simultaneously dope the source, drain, N+ lines, N+ contacts and polysilicon contacts.
A photoresist layer is then applied and exposed to actinic radiation through a C mask having 35 typically enlarged contact geometries (perhaps with the exception of the PC stripe) on each side beyond the respective lines to be contacted. This allows for less stringent alignment tolerances.
After conventional photolithographic 40 processing steps, the windows in the Silox are etched using conventional etching techniques.
An optical Silox reflow step may be performed here to smooth the Silox layer and aid in the subsequent metalization steps and it further 45 causes a beneficial additional dopant diffusion into the contact sites. However, this step is not absolutely necessary and in fact may not be preferable in some cases.
The wafer is then subjected to an acid dip etch 50 and then metalized as in the case of the previous embodiments.
Figure 18 is a partial plan view of a portion of a semiconductor substrate containing elements fabricated in accordance with the present 55 invention. Illustrated are field effect transistor devices Q, and Q2 each having a source, gate and drain. Connected to the respective sources of transistors Q, and Q2 are diffused N+ lines 801 and 803 which have been inter-connected by 60 means of diffused N+ line 806. Similarly, the drains of transistors Q, and Q2 are interconnected to each other by means of diffused N+ lines 802, 805, and 807. All of these diffused lines may be delineated simultaneously by means 65 of the N-mask step. As illustrated in Figure 18,
diffused N+ lines 806 and 807 can extend in various directions on the substrate so as to interconnect with a plurality of additional devices. It is of course also possible to provide one or more contact regions to directly interconnect the N+ diffused lines 806 and 807 to the subsequent metalized interconnections delineated in the M-mask step.
The gates of transistors Q, and Q2 are illustrated as being connected to polysilicon lines 800 and 804, respectively. These remote polysilicon lines could be connected to other portions of the circuitry contained on the substrate. In many cases, however, a direct contact rather than a remote contact would be provided so as to directly connect the gates of the transistors to the metalized interconnections delineated by the M-mask step.
Figure 19 schematically illustrates the portion of the substrate circuitry illustrated in Figure 18. Like designators of the elements in Figure 19 correspond to like elements in Figure 18.
An important usage for the circuitry shown in Figures 18 and 19 would be in the fabrication of monolithic random access memories or read only memories having a large number of memory elements. As indicated in the Summary of the Invention, the disclosed fabrication process lends itself to the fabrication of circuits having active devices and associated interconnects having substantially reduced surface area in comparison to circuitry fabricated by prior art methods. Since there are inherent size limitations in the surface area of the silicon substrates contained in integrated circuit chips, the advantageous reduction of the overall surface area of the elements fabricated in accordance with the present invention allows for the production of integrated circuit chips having greater numbers of memory elements. For example, the invention renders it feasible to produce random access memory chips in accordance with the present invention having 256 kilobits of memory storage capability whereas present day prior art fabrication techniques have only been able to produce commercially feasible random access memory chips having 32 kilobits of memory storage capability.
Numerous modifications and variations of the process and device structures and configurations and of integrated circuit designs incorporating such devices will be apparent to those of skill in the art. Whereas N channel devices have been disclosed, it will be apparent that P channel devices instead can be made by this process. The processes have been illustrated as employing bulk silicon, but silicon layers on other substrates, such as silicon-on-sapphire, may be employed in the alternative.

Claims (1)

  1. Claims
    1. A process for fabricating on a layer of mono-crystalline silicon a very large scale integrated circuit device containing field effect transistors,
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    polysilicon interconnect lines, and diffused interconnect lines, comprising the steps of:
    oxidizing said silicon layer to form a first silicon dioxide layer on the surface thereof;
    5 applying a first layer of silicon nitride over the surface of the first silicon dioxide layer;
    selectively removing portions of said first silicon nitride layer, leaving portions of said first silicon nitride layer juxtaposed over selected areas 10 wherein field effect transistors and diffused interconnect lines are to be formed;
    oxidizing portions of said silicon layer to produce a field oxide over said surface of the silicon layer except at those areas juxtaposed 15 beneath the remaining portions of said first silicon nitride layer;
    depositing a layer of polysilicon having dopant ions therein over said surface of the device;
    oxidizing the surface of said polysilicon layer to 20 form a second layer of silicon dioxide thereon;
    applying a second layer of silicon nitride on the surface of the second silicon dioxide layer;
    oxidizing said second silicon nitride layer to form an oxynitride layer thereon; 25 depositing doping ions in said oxynitride layer of said second silicon nitride layer;
    removing by a selective removal process, all of said doped oxynitride layer of said second silicon nitride layer and all of said second nitride layer 30 except for button-like portion thereof juxtaposed over the location in each selected area at which a contact to a polysilicon interconnect line is to be formed;
    removing the exposed portions of said second 35 silicon dioxide layer exposed by the aforesaid, successive removals of said portions of said oxynitride layer of said second silicon nitride layer and of the corresponding portions of said second silicon nitride layer;
    40 removing the portions of said polysilicon layer exposed by the removal of the exposed portions of said second silicon dioxide layer thereby to define gate electrodes for the field effect transistors and said polysilicon interconnect lines; 45 removing all of the exposed portions of said first silicon nitride layer except for button-like portions thereof juxtaposed over areas of the surface of said layer of monocrystalline silicon which are to be formed into said field effect 50 transistors and at which contacts to said diffused interconnect lines which are to be formed therein are located;
    oxidizing said device whereby an additional layer of silicon dioxide is formed over exposed 55 portions of said diffused interconnect lines and of said polysilicon interconnect lines;
    batch removing said doped silicon oxynitride layer formed from said second silicon nitride layer;
    60 batch removing all portions of said second silicon nitride layer exposed by the removal of said doped silicon nitride dioxide exposed by removal of said doped silicon oxynitride layer formed thereon and simultaneously removing any 65 exposed portions of said firsl silicon nitride layer including said button-like portions thereof;
    batch removing any of said remaining silicon dioxide layers from the areas wherein there are to be formed sources and drains of said field effect devices, polysilicon interconnect line contacts, and diffused interconnect line contacts; and selectively applying conducting interconnection lines to said contact areas exposed by the removal of said remaining silicon dioxide layers.
    2. A process for forming a self-aligned contact to a polysilicon line conductor to be formed at least in part on the field oxide of a semiconductor substrate and to form a gate electrode for a field effect device to be formed in said substrate in a selected area not covered by said field oxide, comprising:
    depositing a polysilicon layer having dopant ions therein on said substrate extending at least over said field oxide;
    oxidizing the surface of said polysilicon layers to form a silicon dioxide layer thereon;
    forming a protective button including a layer of silicon nitride and a superposed layer of silicon oxynitride on the oxidized surface of said polysilicon layer, juxtaposed on the location of a desired contact to a corresponding said polysilicon line conductor to be formed from said layer, and of greater width than said line conductor;
    delineating the portion of said polysilicon layer selected to form said polysilicon line conductor:
    selectively removing portions of said button so as to conform said button in width and location to said delineated polysilicon line conductor;
    selectively removing portions of said polysilicon layer so as to form said polysilicon line conductor with said conformed button juxtaposed thereon, and to form said gate electrode;
    thermally oxidizing said polysilicon line conductor and said gate electrode to form an insulating oxide layer on the exposed surfaces thereof while said button prevents thermal oxidation of the line conductor portion on which it is juxtaposed;
    removing said button by a material selective removal process which does not affect said insulating thermal oxide, thereby to expose the underlying silicon dioxide layer on the surface portion of said polysilicon line conductor; and removing the exposed silicon dioxide layer thereby to expose the underlying surface of said polysilicon line conductor as a contact.
    3. A process as recited in claim 2, further comprising a step of providing conductor lines on said semiconductor substrate extending over said field oxide and onto said polysilicon line contact for providing electrical connection thereto.
    4. A process as recited in claim 2, wherein said button comprises a silicon nitride layer, and said step of removing said button comprises applying an etchant material to said substrate which selectively removes nitride and has no substantial affect on said insulating oxide layer.
    5. A process as recited in claims 2, 3 or 4,
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    wherein the step of delineating said polysilicon line conductor includes forming said polysilicon line conductor in common with said gate electrode as an extension thereof, to afford 5 electrical connection to the gate of said field effect device at the contact provided to said polysilicon line conductor.
    6. A process for fabricating on a layer of mono-crystalline silicon a very large scale integrated 10 circuit device, containing field effect transistors, polysilicon interconnect lines, and diffused interconnect lines, comprising the steps of:
    oxidizing said silicon layer to form a first silicon dioxide layer on the surface thereof; 1 5 applying a first layer of silicon nitride over the surface of the first silicon dioxide layer;
    selectively removing portions of said first silicon nitride layer, leaving portions of said first silicon nitride layer juxtaposed over selected areas 20 wherein field effect transistors and diffused interconnect lines are to be formed;
    oxidizing portions of said silicon layer to produce a field oxide over said surface of the silicon layer except at those areas juxtaposed 25 beneath the remaining portions of said first silicon nitride layer;
    depositing a layer of polysilicon having dopant ions therein over said surface of the device; oxidizing the surface of said polysilicon layer to 30 form a second layer of silicon dioxide thereon;
    applying a second layer of silicon nitride on the surface of the second silicon dioxide layer;
    oxidizing said second silicon nitride layer to form an oxynitride layer thereon;
    35 depositing doping ions in said oxynitride layer of said second silicon nitride layer;
    removing, by a selective removal process, all of said doped oxynitride layer of said second silicon nitride layer and all of said second nitride layer 40 except for button-like portion thereof juxtaposed over the location in each selected area at which a contact to a polysilicon interconnect line is to be formed;
    removing the exposed portions of said second 45 silicon dioxide layer exposed by the aforesaid, successive removals of said portions of said oxynitride layer of said second silicon nitride layer and of the corresponding portions of said second silicon nitride layer;
    50 removing the portions of said polysilicon layer exposed by the removal of the exposed portions of said second silicon dioxide layer thereby to define gate electrodes for the field effect transistors and said polysilicon interconnect lines; 55 . removing all of the exposed portions of said first silicon nitride layer except for button-like portions thereof juxtaposed over areas of the surface of said layer of monocrystalline silicon which are to be formed into said field effect 60 transistors and which contacts to said diffused interconnect lines which are to be formed therein are located;
    removing any portions of said first silicon dioxide layer exposed by removal of said exposed 65 portions of said first silicon nitride layer;
    doping said diffused interconnect lines except at said contact areas thereof covered by remaining portions of said first silicon nitride layer;
    oxidizing said device whereby an additional layer of silicon dioxide is formed over exposed portions of said diffused interconnect lines and of said polysilicon interconnect lines;
    batch removing said doped silicon oxynitride layer formed from said second silicon nitride layer;
    batch removing all portions of said second silicon nitride layer exposed by removal of said doped silicon oxynitride layer formed thereon and simultaneously removing any exposed portions of said first silicon nitride layer including said button-like portions thereof;
    batch removing any of said remaining silicon dioxide layers from the areas wherein there are to be formed sources and drains of said field effect devices, polysilicon interconnect line contacts, and diffused interconnect line contacts;
    simultaneously doping said sources and drains, polysilicon interconnect line contacts, and diffused interconnect line contacts; and selectively applying conducting interconnection lines to said contact areas exposed by the removal of said remaining silicon dioxide layers.
    7. A process for fabricating on a layer of mono-crystalline silicon a very large scale integrated circuit device, containing field effect transistors, polysilicon interconnect lines, and diffused interconnect lines, comprising the steps of:
    defining selected areas of the surface of said monocrystalline silicon layer on which field effect transistors and diffused interconnect lines are to be formed and remaining areas on which a field oxide is to be formed;
    forming said field oxide on all said remaining portions of said monocrystalline silicon layer,
    forming a first silicon dioxide layer of a thickness suitable for the gate insulator layer of the gate structure of said field effect transistors on at least all of said selected areas,
    applying a first layer of silicon nitride at least over said first silicon dioxide layer;
    depositing a layer of polysilicon having dopant ions therein over the surface of the device;
    oxidizing the surface of said polysilicon layer to form a second layer of silicon dioxide thereon;
    applying a second layer of silicon nitride on the surface of the second silicon dioxide layer;
    oxidizing said second silicon nitride layer to form an oxynitride layer thereon;
    depositing doping ions in said oxynitride layer of said second silicon nitride layer;
    removing, by a selective removal process, all of said doped oxynitride layer of said second silicon nitride layer and all of said second nitride layer except for button-like portion thereof juxtaposed over the location in each selected area at which a contact to a polysilicon interconnect line is to be formed;
    removing the exposed portions of said second silicon dioxide layer exposed by the aforesaid
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    successive removals of said portions of said oxynitride layer of said second silicon nitride layer and of the corresponding portions of said second silicon nitride layer;
    5 removing the portions of said polysilicon layer exposed by the removal of the exposed portions of said second silicon dioxide layer thereby to define gate electrodes for the field effect transistors and said polysilicon interconnect lines; 1 o removing all of the exposed portions of said first silicon nitride layer except for button-like portions thereof juxtaposed over areas of the surface of said layer of monocrystalline silicon which are to be formed into said field effect 1 5 transistors and at which contacts to said diffused interconnect lines which are to be formed therein are located oxidizing said device whereby an additional layer of silicon dioxide is formed over exposed 20 portions of said diffused interconnect lines and of said polysilicon interconnect lines;
    batch removing said doped silicon oxynitride layer formed from said second silicon nitride layer;
    25 batch removing all portions of said second silicon nitride layer exposed by the removal of said doped silicon nitride dioxide exposed by removal of said doped silicon oxynitride layer formed thereon and simultaneously removing any 30 exposed portions of said first silicon nitride layer including said button-like portions thereof;
    batch removing any of said remaining silicon dioxide layers from the areas wherein there are to be formed sources and drains of said field effect 35 devices, polysilicon interconnect line contacts, and diffused interconnect line contacts; and selectively applying conducting interconnection lines to said contact areas exposed by the removal of said remaining silicon 40 dioxide layers.
    8. A process as in claim 1 or 7 further comprising, prior to oxidizing said device for forming an additional layer of silicon dioxide over exposed portions of said diffused interconnect 45 lines;
    doping said diffused interconnect lines except for the portions thereof comprising said contact areas of said diffused interconnect lines.
    9. A process as in claim 1 or 7 further 50 comprising, prior to the step of selectively applying conducting interconnection lines to said contact areas exposed by the removal of said remaining silicon dioxide layers:
    simultaneously doping all of said areas 55 exposed by the removal of said remaining silicon dioxide layers.
    10. A process as in claim 8 further comprising, prior to the step of selectively applying conducting interconnection lines to said contact
    60 areas exposed by the removal of said remaining silicon dioxide layers;
    simultaneously doping all of said areas exposed by the removal of said remaining silicon dioxide layers.
    65 11. A process as in claim 9, wherein said simultaneous doping step comprises the steps of: applying a layer of material containing dopant ions;
    heating said material to diffuse said dopant 70 ions into said exposed regions; and deglazing said device to remove said layer of material containing dopant ions and any oxide material formed on said contact areas as a result of said heating for doping thereof. 75 12. A process as in claim 10 wherein said simultaneous doping step comprises the steps of: applying a layer of material containing dopant ions;
    heating said material to diffuse said dopant 80 ions into said exposed regions; and deglazing said device to remove said layer of material containing dopant ions and any oxide material formed on said contact areas as a result of said heating for doping thereof. 85 13. A process as in claim 1 or 7, further comprising, prior to the formation of said field oxide in said remaining areas of said monocrystalline silicon layer, ion implanting doping ions into said remaining areas of said 90 surface where said field oxide is to be formed.
    Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1983. Published by the Patent Office, 25 Southampton Buildings, London, WC2A 1AY, from which copies may be obtained
GB08220264A 1978-05-26 1982-07-13 Manufacture of integrated circuits Expired GB2106315B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/909,886 US4277881A (en) 1978-05-26 1978-05-26 Process for fabrication of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US05/913,182 US4221044A (en) 1978-06-06 1978-06-06 Self-alignment of gate contacts at local or remote sites

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0200603A2 (en) * 1985-04-01 1986-11-05 Fairchild Semiconductor Corporation A small contactless ram cell
EP0660395A3 (en) * 1993-12-17 1997-05-14 Sgs Thomson Microelectronics Self-aligned contact with zero offset to gate.
US6051864A (en) * 1993-12-17 2000-04-18 Stmicroelectronics, Inc. Memory masking for periphery salicidation of active regions
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503601A (en) * 1983-04-18 1985-03-12 Ncr Corporation Oxide trench structure for polysilicon gates and interconnects
DE69424388T2 (en) * 1993-12-23 2000-08-31 St Microelectronics Inc Process and dielectric structure to facilitate metal overetching without damaging the intermediate dielectric

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0200603A2 (en) * 1985-04-01 1986-11-05 Fairchild Semiconductor Corporation A small contactless ram cell
EP0200603A3 (en) * 1985-04-01 1987-03-25 Fairchild Semiconductor Corporation A small contactless ram cell
EP0660395A3 (en) * 1993-12-17 1997-05-14 Sgs Thomson Microelectronics Self-aligned contact with zero offset to gate.
US5793114A (en) * 1993-12-17 1998-08-11 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6051864A (en) * 1993-12-17 2000-04-18 Stmicroelectronics, Inc. Memory masking for periphery salicidation of active regions
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US6284584B1 (en) * 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
US6514811B2 (en) 1993-12-17 2003-02-04 Stmicroelectronics, Inc. Method for memory masking for periphery salicidation of active regions
US6661064B2 (en) 1993-12-17 2003-12-09 Stmicroelectronics, Inc. Memory masking for periphery salicidation of active regions

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GB2106315B (en) 1983-08-03
GB2104285B (en) 1983-07-06
GB2024505A (en) 1980-01-09
GB2104285A (en) 1983-03-02

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