GB2104285A - Manufacture of integrated circuits - Google Patents

Manufacture of integrated circuits Download PDF

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Publication number
GB2104285A
GB2104285A GB08220289A GB8220289A GB2104285A GB 2104285 A GB2104285 A GB 2104285A GB 08220289 A GB08220289 A GB 08220289A GB 8220289 A GB8220289 A GB 8220289A GB 2104285 A GB2104285 A GB 2104285A
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United Kingdom
Prior art keywords
layer
lines
portions
polysilicon
silicon
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Granted
Application number
GB08220289A
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GB2104285B (en
Inventor
Gordon Charles Godejahn
Gary Lee Heimbigner
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Boeing North American Inc
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Rockwell International Corp
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Priority claimed from US05/909,886 external-priority patent/US4277881A/en
Priority claimed from US05/913,182 external-priority patent/US4221044A/en
Application filed by Rockwell International Corp filed Critical Rockwell International Corp
Publication of GB2104285A publication Critical patent/GB2104285A/en
Application granted granted Critical
Publication of GB2104285B publication Critical patent/GB2104285B/en
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A VLSI device is formed on monocrystalline silicon and comprises FET's (G, S, D) and diffused connections 101 surrounded by field oxide and polysilicon interconnections 102. First oxide and nitride layers are formed (for the gate insulator) and doped polysilicon is applied, oxidised to a second oxide layer and covered with a second nitride layer which is oxidised to an oxynitride layer. The last two layers are masked and etched except where polysilicon contacts 103 are required. A third silicon nitride layer is applied and oxidised to an oxynitride layer and these layers are masked and etched to define the polysilicon connection 102 including gate electrodes G. Then the exposed second nitride with its oxynitride and then polysilicon are removed. The first nitride and its oxynitride are masked and etched to define the FET areas 405 and diffused line contact areas 406. Batch etching steps are followed by doping the diffused and polysilicon lines 101, 102 thereby exposed. More batch etching steps are followed by doping the source and drain regions thereby exposed. Oxide is removed from contact areas Pc, Nc and interconnection lines are applied. <IMAGE>

Description

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GB 2 104 285 A
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SPECIFICATION
Manufacture of integrated circuits
5 The invention relates to the manufacture of integrated circuits, more particularly to the fabrication of very large scale integrated circuits (VLSI) having increased density and reliability and containing FET devices, polysilicon and diffused N+ interconnect 10 lines, and metallized interconnect lines interfacing with the polysilicon and N+ diffused lines.
The semiconductor art has been concerned with reducing the size and power consumption of individual devices and integrated circuits in order to 15 increase the logic power of these circuits in order to increase the logic power of these circuits per unit area. A particular effort has been extended in the area of monolithic random access memories (RAM's) and read only memories (ROM's) having 20 very large memory capacity. Many things have been done over the years in an attempt to reduce the size of devices and improve tolerances with which they are fabricated. Such efforts have included, inter alia, fine line lithography, improved mask generation and 25 alignment machines, improved tolerances on mask alignment, and self-aligned gates. These techniques have reduced the area required forthe fabrication of the individual FET devices used in these integrated circuits. However, because of alignment tolerances, 30 the FET devices must be designed with larger geometry than they would have to be if perfect mask alignment were obtained. Furthermore, because of alignment tolerances, the FET devices must be spaced further apart than otherwise necessary in 35 order to allow for the misalignment in the formation of the interconnection lines. Consequently, there is a need for an improved integrated circuit fabrication technique for producing VLSI circuits including FET devices and conducting lines having reduced sensi-40 tivity to mask alignment.
Summary of the invention
In a process in accordance with the invention, both the gate oxide layer of the active FET devices of the 45 integrated circuit as well as a silicon nitride layer are formed on the surface of a silicon substrate. Both layers are surrounded by a field oxide layer and simultaneously formed on areas in which diffused N+ conducting lines are to be formed. A polysilicon 50 layer formed on the nitride layer, is delineated to provide the polysilicon conductor of the gates of the FET devices as well as being delineated for additional interconnection lines and then may be partially oxidized in reliance on the masking effect of the 55 nitride layer. This affords minimal oxide layer thickness on the gate polysilicon layer and again contributes to the reduced device size. Subsequently, silicon nitride, silicon oxynitride, silicon dioxide, and photoresist layers are then employed in various 60 masking and selective etch processes to provide self-aligned gates and contacts for FET devices and self-aligned interconnection interfaces. The fact that silicon nitride, silicon oxynitride, silicon dioxide, photoresist, and silicon all have different etch re-65 moval rates when exposed to various etching processes makes it feasible for the number of masking steps to be reduced in comparison to prior art methods and further allows self-alignment features not previously obtainable. In addition, the method described below in accordance with the present invention allows the simultaneous doping of two or more regions. This is advantageous in that the resulting integrated circuit device has more uniform characteristics.
The processes of the present invention permit direct contact to the gate electrode as well as floating gate contact configurations. Diffused conducting lines permit a first level interconnect to source and drain as well as being compatible with a direct gate contact configuration. Conversely a remote gate contact with direct source and drain contacts may also be afforded. Theoretically, simultaneous and direct source, gate, and drain contacts may be provided although current technology limits the miniaturization of device size and configuration by virtue of the dimensions of the conducting lines in such a simultaneous direct contact device configuration.
These and other objects and advantages of the invention will be apparent from the following detailed description of certain preferred embodiments thereof.
Brief description of the drawings
Figure 1 illustrates a partial plan view of the surface of the semiconductor wafer to be processed in accordance with the present invention. The cross-hatched portions correspond to the various photolithographic masks used in performing the process in accordance with the present invention. Section lines A-A, B-B and C-C are provided so as to reference Figures 2 through 11,13 and 15-17.
Figures 2-17 illustrate partial plan and cross-sectional views of the semiconductor wafer illustrated in Figure 1. These figures illustrate in chronological order the semiconductor wafer after having undergone the various steps enumerated below.
Figure 18 illustrates an electrical intergrated circuit which may be a portion of a VLSI circuit.
Figure 19 is the equivalent electrical schematic of the structure of Figure 18.
Description of the preferred embodiments First preferred embodiment
The following description of the first preferred embodiment provides the chronological sequence of process steps performed in accordance with the present invention. Each of these process steps has been given a numerical designation for ease of identification.
Step 1. The process starts with a semiconductor water having a monocrystalline device quality layer of P-type silicon. The wafer can be either of monolithic configuration or may be a composite wafer having a silicon layer 1 on top of a substrate of different material (e.g. silicon-on-sapphire composite). In addition, while the process has been illustrated as beginning with P-type substrate it is of course understood that the process is amenable to N-type substrates as well. The dopant materials used
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GB 2 104 285 A
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in such a case would be different from those indicated below. The wafer is first cleaned by conventional means to remove the normal surface impurities. Figure 2 illustrates a partial cross-5 sectional view of a monolithic silicon wafer 1.
Step 2. The now cleaned wafer is subjected to a conventional oxidation process (e.g., thermal oxidation) which serves to form a silicon dioxide layer 5 on top of the silicon layer 1. Atypical thickness for 10 the silicon dioxide layer 5 would be somewhere on the order of 600 A. Figure 3 illustrates a partial cross-sectional view of the water after having been processed in accordance with this step.
Step 3a. A first nitride layer 6 is deposited on top 15 of the silicon dioxide layer 5 using conventional nitride deposition techniques. The nitride layer 6 deposited may typically be on the order of 575 A thick.
Step 3b. The wafer is then optionally subjected 20 to a short steam cycle to form a thin silicon oxynitride layer 400 on top of the silicon nitride layer 6. This oxynitride layer 400 allows for greater adherence of the photoresist regions 100 and 101 applied in step 4a below. However, it has been found 25 that this oxynitride layer is not absolutely necessary. Figure 4 illustrates the wafer after being processed in accordance with step 3b.
Step 4a. A photoresist layer is then deposited on top of the silicon nitride and oxynitride layers and 30 this photoresist layer is exposed to actinic radiation through a N-mask. The N-mask is substantially transparent to actinic radiation except for a plurality of protective regions (i.e.-100 and 101 as illustrated in Figure 1) which are opaque to the actinic radiation. 35 The photoresist regions 100 and 101 which have been shielded by the opaque protective regions of the N-mask are nonsoluble in an appropriate photoresist developer while the remainder of the photoresist which had been exposed to the actinic radiation 40 becomes soluble in the same appropriate photoresist developer. Thus, by placing the wafer in an appropriate developer solution, the photoresist layer is selectively removed in accordance with the configuration of the protective regions 100 and 101 of 45 the N-mask.
Step 4b. The wafer is then subjected to sequential selective oxynitride and nitride removal processes using removal processes that attack the oxynitride layer 400 and the nitride layer 6 but do not attack 50 the photoresist layer. Thus, the oxynitride layer 400 and the nitride layer 6 are selectively removed from the entire surface of the silicon dioxide layer at all regions except where protected by the remaining regions 100 and 101 of the photoresist layer. A 55 plasma etching process is but one example of such a selective nitride removal process. The remaining oxynitride and nitride regions cover those areas of the wafer in which the FET devices will be located (i.e. - region 100) and further cover the areas of the 60 chip in which N+ diffused interconnecting lines will eventually be formed (i.e. - region 101).
Figures 1,5 and 6 illustrate the two photoresist layer regions 100 and 101 which the N mask has protected.
65 Step 5. The wafer is then subjected to a depant implant step in which dopant ions (e.g. - boron ions) are implanted into the surface of the entire silicon layer except for those areas directly underneath the remaining photoresist regions 100 and 101. The 70 photoresist layer is a shield against the dopant ions. The arrows 150, in Figure 6, indicate the path of the dopant ions. Afterthe ion implantation step, the photoresist regions 100 and 101 are removed by conventional techniques (e.g., sulphuric/persulfate 75 acid bath). The ion implantation serves to dope the silicon substrate 1 in those regions which will ultimately be used for isolating the active devices and the N+ interconnecting lines.
Step 6. The wafer is then subjected to an anneal-80 ing process which serves to stabilize and equalize the above noted ion implantation step. This annealing step may be combined with the field oxidation step (step 7) described below.
Step 7. The wafer is then subjected to a thermal 85 field oxidation process which thermally oxidizes the surface of the field portions of the silicon layer 1 except underthe remaining portions of the silicon oxynitride and nitride layers 400 and 6. The silicon nitride layer portions 6 serve to protect the under-90 lying silicon from thermal oxidation. Typically, the thermal oxidation process can be used to form dioxide layers 2,3, and 4 having a thickness of the order 15,500 A. In addition, such a thermal oxidation process of sufficient duration to produce a 15,500 A 95 silicon dioxide thickness will produce an oxynitride layer 7 having a 200 A thickness. The oxynitride layer 7 combines with the optional oxynitride layer 400 to form a single oxynitride layer. This single combined layer will subsequently be referred to as oxynitride 100 layer 400 for convenience. The thermally grown silicon dioxide field oxide layers 2,3 and 4 will ultimately serve to electrically isolate the FET devices and N+ diffused interconnections. Figure 7 illustrates a cross-sectional view of the semiconduc-105 tor wafer illustrated in Figure 1 after having undergone processing steps 1 to 7. Note that the thick field oxide regions 2,3 and 4 have been grown everywhere but in regions 8 and 10. Region 8 illustrates the cross-section taken along section line A-A of 110 Figure 1 while area 9 illustrates a cross-section taken along section line B-B of Figure 1. Area 10 is a cross-sectional view taken along section line C-C of Figure 1. In areas 8 and 10, the silicon substrate 1 is covered by the gate oxide layer 5, the silicon nitride 115 layer 6, and the oxynitride layer 400. Present but not shown in Figure 7 are in regions of silicon layer 1 underneath the field oxide layer 2,3 and 4 which have dopant ions which have been implanted by step 5. While the process indicates the use of a 120 nitride layer, it is understood that other materials having characteristics similar to silicon nitride may be substituted.
Step 8. A layer of polycrystalline silicon (polysilicon) 11 is then deposited on top of the surface of the 125 water. Typically, a phosphorus or arsenic doped polysilicon is used and a polysilicon layer 11 having a thickness on the order of 8,000 A is deposited. The polysilicon layer 11 will eventually be selectively removed so as to form the gate electrodes and 130 remote gate interconnect lines.
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Step 9. The polysilicon layer 11 is then oxidized using conventional oxidation techniques (e.g. steam treatment to form a layer of silicon dioxide 12 on top of the polysilicon layer 11. Typically, a silicon dioxide 5 layer 12 of between 600 to 1,200 A is formed.
Step 10. The water is then subjected to a second nitride deposition process which deposits a layer of silicon nitride 13 on top of the silicon dioxide layer 12. Typically, this second nitride layer 13 is on the 10 order of 400 A thick. Figure 8 illustrates the wafer after being processed in accordance with step 10.
Step 11. A photoresist layer 401 is then applied on top of the second nitride layer 13 and exposed to actinic radiation through a PC-mask. This mask has 15 its opaque protective regions 103, illustrated in Figure 1, configured so as to render the photoresist layer in soluble at that region on the wafer wherein the polysilicon contact to a subsequently formed metalized interconnect line is to be located. The 20 photoresist layer is then developed with the appropriate photoresist developer solution to remove the unwanted photoresist layer.
Step 12a. The wafer is then subjected to a selective nitride layer removal process (e.g., plasma 25 etching) to selectively remove all of the second nitride layer 13 except those portions protected by the remaining photoresist layer 401.
Figure 9 illustrates a cross-sectional view of a semiconductor wafer 1 of Figure 1 after having 30 undergone processing up to and including step 12a in accordance with the present invention. The polysilicon layer 11 is covered at the PC contact site by a silicon dioxide layer 12, the second silicon nitride layer 13, and the photoresist region 401 which 35 covers the illustrated polysilicon contact.
Step 12b. The remaining photoresist layer 401 is then removed. Thus, the PC contact area is protected by the second nitride layer 13, while the remainder of the wafer has a surface layer of silicon dioxide 12. 40 Step 13. Apply a layer 402 of material such as boron doped chemically vapor deposited silicon dioxide (Silox) which has a lower etch rate than oxynitride layers when exposed to the same etchants. Other substitute materials may be used. 45 Step 14a. Apply a layer of photoresist to the silicon wafer and expose same to actinic radiation through a G-mask and then remove the unwanted photoresist layer using the appropriate developer solution. This leaves regions 403 and 404 of photore-50 sist 14 atop the exposed Silox layer 402 stop the second nitride layer 13 and silicon dioxide layer 12 at those locations where the polysilicon interconnect and polysilicon gate lines are located (illustrated as area 102 Figure 1). Figure 10 illustrates a partial 55 cross-sectional view of the wafer after being processed in accordance with step 14. Note that the G-mask resist areas 403 and 404 are juxtaposed directly above the gate and polysilicon line regions. Also note that as illustrated in Figure 1, because of the 60 fact that the PC mask and N mask regions 103 and 100 are largerthan the polysilicon line and gate mask 102, the alignment tolerance of the G mask is not stringent.
Step 15a. Using a selective oxide removal pro-65 cess, selectively remove those portions of the silox layer 402 not protected by the G-mask resist regions 403 and 404.
Step 15b. Using a selective nitride removal process (e.g., plasma etch), selectively remove those 70 portions of the second silicon nitride layer 13 not protected by the photoresist regions 403 and 404.
Step 15c. Using a selective oxide removal process, selectively remove those portions of the silicon dioxide layer 12 not protected by the G-mask resist 75 regions 403 and 404.
Step 15d. Using a selective polysilicon removal process, selectively remove those portions of the polysilicon layer 11 not protected by the photoresist regions 403 and 404. Figure 11 illustrates a partial 80 cross-section view of the wafer after having undergone processing in accordance with step 15d. Note that the G-mask region in area 8 (i.e.-the gate region) comprises the silicon 1, covered by silicon dioxide 5, silicon nitride 6, and silicon oxynitride 400, 85 covered in turn by polysilicon 11, silicon dioxide 12, Silox 402, and finally covered by the G-mask resist region 403. The G-mask region in area 9 (i.e. - the PC polysilicon contact region) consists of the silicon 1 covered by the field oxide 3, covered by polysilicon 90 11, silicon dioxide 12, covered in turn by the second nitride layer 13, the Silox 402, and finally covered by the G-mask resist region 404. The source, drain, and N+ diffused line areas consist of the silicon 1 covered by silicon dioxide 5, silicon nitride 6, and 95 silicon oxynitride 400.
Step 15e Remove the remaining portions of the photoresist layer using conventional techniques.
Step 16. Apply a layer of photoresist to the silicon wafer and expose same to actinic radiation 100 through a C-mask and then remove the unwanted photoresist layer using the appropriate developer solution. This leaves a layer of photoresist atop the wafer at those regions shown in crosshatch lines as regions 405 and 406 of Figure 12. Areas 501 - 506 105 respectively illustrate the polysilicon line 501, source 502, gate 503, and drain 504 of an FET device, N+ diffused line 505 and N+ contact 506. These regions are over areas which will ultimately be the contact interface between the source and drain lines, (i.e. -110 region 405) the diffused N+ lines (i.e. - region 406) and the subsequently formed metalized interconnection lines. As illustrated in Figure 1, the C mask areas 405 and 406 do not require stringent placement alignment tolerances, since they are larger than the 115 areas to be protected.
Step 17a. Using a selective oxynitride removal process, selectively remove those portions of the oxynitride layer not protected by the photoresist regions 405 and 406.
120 Step17b1. Using a selective nitride removal process, selectively remove those portions of the nitride layer not protected by the photoresist regions 405 and 406.
Step 17b2. Remove the underlying oxide ex-125 posed by the nitride removal process in step 17b1.
Step 17b3. Deposit a phosphorus or arsenic dopant on the surface of the wafer and perform a dopant drive process to dope the N+ line.
Step 17c. Remove the photoresist region 405 and 130 406 using conventional techniques.
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Step 17d1. Oxidize the exposed polysilicon interconnect line and N+ interconnect line using conventional oxidization techniques (e.g., steam processing) to fabricate a thick silicon dioxide layer 15 5 thereon. Typically, a 4000 to 5000 A thick layer may be produced. It is important to note that in region 8 and in the region 10 protected in the earlier steps by photoresist regions 405 and 406, the oxynitride layer 400 and underlying nitride layer 6 protect the 10 underlying source, drain and N+ contact areas from oxidation. Note that the sides of the polysilicon gate and line, since they are not protected by a silicon nitride or oxynitride layer, are oxidized simultaneously with the formation of oxide layer 15. 15 These additional oxidized side areas 475 are extremely important since their presence prevents the subsequently applied metalized interconnection to the source, drain, and N+ contacts, from shorting to the sides of the polysilicon gate and line if misalign-20 ment should occur. The oxidation process also partially oxidizes the top of polysilicon layer 11 not protected by the second silicon nitride layer. Figure 13 illustrates dopant ions present in the Silox layer 402. Figure 13 illustrates the wafer cross-section 25 after being processed in accordance with step 17.
Step 18. Subject the wafer to a dip etch process to remove all of the exposed Silox layer 402. Alternatively, (see Alternate step 18 below) the wafer can be subjected to a C2-mask step to leave a Silox 30 layer covering the poly line except at the PC poly line contact site. Figure 14 illustrates such a C2-mask. The use of the C2 mask step, as described below in Alternate step 18, leaves the Silox layer 402 covering the polysilicon line except at the PC contact site. 35 Because of the presence of the Silox layer, the polysilicon line would not be doped by step 20. However, additional doping of the already doped polysilicon may not be required. For the remaining discussion, it will be assumed that step 18 has been 40 performed instead of Alternate step 18.
Alternate Step 18. A photoresist layer is applied to the surface of the wafer and exposed to actinic radiation through a C2-mask and the unwanted portions of the photoresist layer are then removed 45 using an appropriate developer solution. The C2 mask contains opaque protective regions so as to leave a photoresist layer over the entire surface except at those areas in which polysilicon line contacts are to be formed. The exposed Silox layer 50 402 is then removed and the C2 - mask photoresist layer removed, leaving a N+ contact area protected by a nitride/oxynitride button.
Step 19a. Subject the wafer to a selective oxynitride removal process (e.g., wet or plasma etching) to 55 selectively remove the exposed oxynitride layer off of the source, drain, and N+ line contacts located underthe oxynitride layer.
Step 19b. Subject the wafer to a nitride removal process (e.g., plasma or wet etching) to selectively 60 remove those portions of the first and second nitride layers covering the source, drain, N + line contacts and polysilicon line contact sites. Figure 15 illustrates a cross-sectional view of the silicon wafer 1 after having undergone the nitride removal process 65 of step 19b. Note that the source, drain, polysilicon contact and N+ contact now all have just a thin oxide layer cover. Dip etch the wafer to remove the oxide layer covering the regions to be doped.
Step 20. Deposit a layer of phosphorus using, for 70 example, conventional POC13techniques or deposit arsenic using a layer of arsenic doped Silox or polysilicon. Using conventional techniques, the wafer is then subjected to a doping process which drives the phosphorus or arsenic ions simultaneously into 75 the source, drain, N+ contact and polysilicon contact regions.
Step 21. Deglaze if a conventional POC13 doping procedure is performed, by a dip (batch) etching procedure. This dip etching serves also to remove 80 any thin oxide layer covering the contact sites formed in step 20. Fgure 16 is a partial cross-sectional view of the wafer after having been processed in accordance with step 21.
Step 22. Apply a Silox layer 410 to the surface of 85 the wafer and densify by normal densification techniques. Then apply a layer of photoresist and expose same to actinic radiation through a second C-mask and then remove the unwanted photoresist layer using the appropriate developer solution. The 90 second C-mask has opaque portions arranged so as to leave unprotected the previously formed contact sites. The wafer is then subjected to a selective oxide removal process (e.g., etching) so as to provide windows into the contact sites. Note that the oxide 95 removal process may be used to etch a window through both the Silox layer 410 and any remaining portions of the silicon dioxide layer 5. The second C-mask does not require stringent alignment tolerances since all the contact regions have already been 100 formed and are separated by insulating materials, and since all of the edges 475 of the polysilicon line 11 are protected by an insulating oxide.
Step 23. Apply a metallization layer 20 and a photoresist layer and expose same to actinic radia-105 tion through a M-mask and the remove the unwanted photoresist layer using standard removal techniques. The M-mask is arranged to leave protective portions of photoresist layer on those areas of the conductive metalization layer wherein intercon-110 nections to the contacts are to be formed. The wafer is then subjected to a standard metalization layer removal process (e.g., etching) to remove the unwanted metalization layer and the wafer is then subjected to a photoresist removal process. Other 115 materials (e.g., - polysilicon) could be substituted for the metalization layer 20.
Step 24. The wafer is then exposed to a hydrogen annealing process to anneal the previously formed metalization layer. Figure 17 illustrates the 120 silicon wafer of Figure 1 after this step.
Step 25. The wafer is then subjected to the usual finishing procedures (e.g. sandblasting, cleaning, passivating) in accordance with conventional procedures.
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Alternate embodiment I
This embodiment is essentially a modification of the first embodiment described above with the distinction being that the boron doped Silox deposi-130 tion step (Step 13) is replaced by the boron doping of
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an oxynitride layer (greater than 80 A thick) formed over the second silicon nitride film. In other words, after Step 10 of the first embodiment, we would add:
Step 10a. Steam nitride layer to form an oxynit-5 ride layer thereon.
Step 10b. Subject the wafer to a boron deposition process (e.g., boron deposition at 1030° with BBr3) to deposit boron ions on the just formed oxynitride layer.
10 Step 13 of course would be deleted and in Steps 15a and 18 we would of course selectively etch the boron doped oxynitride layer rather than a Silox layer. The remaining processing steps would be identical to those of the first embodiment.
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Alternate embodiment II
This embodiment is an improvement over the embodiments described above in that a layer of silicon nitride is used instead of the boron doped 20 Silox or boron doped oxynitride layers. Since the silicon nitride layer (designed silicon nitride III) may be as thin as 400A, one can more accurately etch the polysilicon lines than, for example, when using the Silox or nitride II layer which must be thicker 25 typically than the silicon nitride layer. Since the processes of this embodiment are quite similar to those of the first embodiment, the different processes described below with regard to this embodiment will not be stated in such comprehensive detail as 30 that provided for the first embodiment.
Step 1. Perform the steps of the first embodiment up to and including Step 10 (deposit nitride layer II).
Step 2. Steam silicon nitride II layer to form a 35 layer of silicon oxynitride (e.g., - greater than 80A thick).
Step 3. PC mask
Step 3a. Remove unwanted resist so as to leave resist on the PC mask as in first embodiment. 40 Step 3b. Etch the unprotected oxynitride layer.
Step 3c. Remove the exposed field nitride layer using, for example, a plasma etch process.
Step 4. Deposit a silicon nitride layer III (e.g., 400 A thick), and steam the nitride layer to form a silicon 45 oxynitride layer.
Step 5. G mask.
Step 5a. Remove unwanted photoresist layer so as to leave resist overthe PC stripe and overthe polysilicon interconnection lines.
50 Step 5b. Etch the exposed oxynitride off of the field areas.
Step 5c. Etch the nitride off of the field using, for example, a plasma etch process so as to leave nitride covering the oxynitride strip on the PC pad and over 55 the oxidized polysilicon interconnection lines.
Step 5d. Remove the remaining photoresist and etch the exposed oxide and polysilicon lines using, for example, wet or dry plasma etching techniques.
Step 6. C mask (as in first embodiment). 60 Step 6a. Remove unwanted photoresist so as to leave resist areas on the N+ diffused line contact region and the source and drain regions.
Step 6b. Using a selective removal procedure, (e.g. - selective etch) etch the oxynitride layer off of 65 the N+ lines.
Step 6c. Remove the remaining photoresist layer using conventional methods.
Step 6d. Plasma etch the silicon nitride off of the N+ lines and the polysilicon lines and then dip etch the entire wafer to remove the underlying silicon dioxide layer so as to expose the bare silicon, thus exposing the N+ and polysilicon lines.
Step 7. Deposit arsenic or phosphorus using conventional techniques or alternatively implant arsenic or phosphorus ions using ion implant techniques. Delgaze the wafer if necessary.
Step 8. Drive the junctions in the N+ lines and oxidize the N+ lines and polysilicon lines to any desired oxide thickness. For example, if a 5,000A thick oxide layer is desired, a 90-120 minute steam process would be desirable for phosphorus type doping. A different cycle would be necessary for arsenic doping to achieve a similar result.
Step 9. Dip etch the oxynitride layer off of the contact sites.
Step 10. Plasma etch the exposed nitride layer off of the contact sites.
Step 11. Phosphorus or arsenic dope the source, drain, N+ contacts and PC contacts as in the first embodiment. Note that in this embodiment, the N+ and polysilicon lines are doped in a separate step.
Step 12. Continue with Step 21 of the first embodiment and complete the processing of the wafer.
Alternate embodiment III
As an extension of alternate embodiment II, the following improved variation is offered:
At Step 4 of alternate embodiment II, a photoresist layer can be substituted for the third silicon nitride layer and left in place after the G masking steps (Steps 5 and 5a of alternate embodiment II). After Step 5b of alternate embodiment II is completed, the oxynitride layer is removed, and the polysilicon layer plasma etched to delineate the polysilicon lines. The plasma etching method usually improves the resist adherence through perhaps an additional polymerization. This is a highly desirable feature, since in this alternate embodiment, the G mask resist is left in place as a protective covering for the polysilicon contact stripe PC of oxynitride coated nitride during the C layer etching step of the oxynitride layer over the N+ lines (i.e., the resist for the C layer is next applied overthe resist remaining from the G layer masking steps. The processing then continues to Step 6b of alternate embodiment II and the oxynitride layer is etched off the N+ lines. Subsequently, in Step 6c the resist from both the C and the G masking operations is removed. Step 6d is then performed to plasma etch the first silicon nitride layer from the N+ lines. The wafer is then dip etched to remove the underlying oxide layer and the processing proceeds to Step 7 of alternate embodiment II and continues to completion of the wafer.
Alternate embodiment IV
In order to reduce the deleterious effect of the first silicon nitride regions edge lifting and cracking after Step 7, (i.e., the field oxidation step of all the various embodiments) the first silicon nitride layer can be
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stripped by a plasma etching technique after the field oxidation, and then the wafer can be subjected to a wet etching to remove the underlying oxide layer. A new gate oxide and gate silicon nitride layer 5 are then regrown. For example, the wafer is first processed in accordance with Steps 1 through 7 of the first embodiment. The wafer is then processed as follows:
Step 2a. Remove the oxynitride layer off the N 10 mask regions by conventional etching techniques (e.g., wet acid etching).
Step 2b. Remove the exposed silicon nitride layer by conventional plasma etching techniques.
Step 2c. Remove the exposed underlying oxide 15 layer if desired.
Step 2d. Subject the wafer to a reoxidation process to regrow the gate oxide to a thickness of about 600A. It is noted that the removal of the underlying oxide (Step c) will preferentially attack 20 the "bird beak" formed during the original field oxidation step and reduce its height and stress contributing factors. This preferential attacking of the "bird beak" oxide occurs because the "bird beak" oxide is more highly stressed. By reoxidizing 25 the intended gate region and redepositing a silicon nitride layer, the resultant oxide/nitride sandwich layer has a better integrity and fewer defects. Furthermore, by regrowing the oxide and the depositing with silicon nitride, the field oxide regions 30 are covered with an additional silicon nitride layer to provide additional isolation of the polysilicon lines and the field oxide. Furthermore, the silicon nitride layer atop the field oxide provides a different type of surface for nucleating the polysilicon layer to be 35 applied later and usually produces a finer grained polysilicon texture.
Step 2e. Subject the wafer to a steam treatment to convert the exposed nitride film to an oxynitride. An added advantage of this newly formed silicon 40 nitride layer is that it will prevent later oxide growth of the field regions during subsequent diffusion steps and act as an etch stop during later oxide etch steps. The wafer is then processed in accordance with the remaining steps of the various embodi-45 ments (i.e., deposit a layer of polysilicon as in Step 8).
Alternate embodiment V
An improvement can be made in the above noted 50 embodiments by the use of a doped chemically vapor deposited silicon dioxide layer (Silox). The Silox layer (doped either with phosphorus or arsenic for example) is used as a diffusion source for all of the N+ areas and enables the simultaneous diffu-55 sion of the source, drain, N+ lines, polysilicon lines, and polysilicon contacts. The doped Silox is left in place after the dopant diffusion process to serve as an electrical insulating layer. Particularly, it serves as an electrical insulator between the polysilicon lines 60 and the metalized interconnection lines overlying the polysilicon lines. Another feature of this embodiment is the elimination of the first C masking step since a later C mask over the doped Silox layer will be used to open contacts to all of the desired contact 65 regions. This C mask will have enlarged contact geometries, (for example, larger than the width of of polysilicon lines or N+ lines), to enable a non-stringent C mask positional alignment tolerance. Additionally, the polysilicon lines are oxidized to 70 form for example 5,000A of silicon dioxide afterthe G masking step used to delineate the polysilicon lines but before the nitride layer is selectively removed from the N+ lines, source, drain, and polysilicon contacts. The basic sequence of masks 75 used in this embodiment are: N. PC, G, C, and M. A short description of the sequence of steps in this embodiment is noted below:
Proceed to process the wafer in accordance with alternate embodiment IV as noted above up to an 80 including the G mask process. After the photoresist layer has been exposed to the G layer mask to delineate the polysilicon lines, the wafer is dip etched to remove the oxynitride layer on the PC nitrided surface pad and the wafer is then subjected 85 to a plasma etching process to remove the nitride extensions beyond the PC mask stripe.
The wafer is then subjected to a wet etching process to remove the field oxide layer on top of the poly layer and the wafer is then plasma etched to 90 remove the polysilicon field. As an alternative to the plasma etching process, the remaining photoresist layer can be removed and the wafer subjected to a wet etching process to remove the polysilicon field.
The polysilicon lines are now delineated and after 95 removing the remaining photoresist layer (if necessary) the polysilicon lines are oxidized to form a silicon dioxide layer thereon of typically between 3,000 and 5,000A thick.
The wafer is then subjected to a dip etching 100 process to remove all of the oxynitride layer overthe N+ lines. The oxynitride is also removed by the same process from the source and drain regions and the polysilicon contact sites.
The wafer is then subjected to a plasma etching 105 process to remove the protective nitride I layer from the N+ lines, source, drain, and polysilicon contacts. Accordingly, the underlying oxide layer is dip etched. A layer of doped Silox (for example phosphorus doped) is then deposited and the wafer 110 subjected to a drive process to simultaneously dope the source, drain, N+ lines, N+ contacts and polysilicon contacts.
A photoresist layer is then applied and exposed to actinic radiation through a C mask having typically 115 enlarged contact geometries (perhaps with the exception of the PC stripe) on each side beyond the respective lines to be contacted. This allows for less stringent alignment tolerances.
After conventional photolithographic processing 120 steps, the windows in the Silox are etched using conventional etching techniques.
An optical Silox reflow step may be performed here to smooth the Silox layer and aid in the subsequent metalization steps and it further causes 125 a beneficial additional dopant diffusion into the contact sites. However, this step is not absolutely necessary and in fact may not be preferable in some cases.
The wafer is then subjected to an acid dip etch and 130 then metalized as in the case of the previous
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embodiments.
Figure 18 is a partial plan view of a portion of a semiconductor substrate containing elements fabricated in accordance with the present invention.
5 Illustrated are field effect transistor devices ^ and
2 each having a source, gate and drain. Connected to the respective sources of transistors ■[ and 2 are diffused N+ lines 801 and 803 which have been inter-connected by means of diffused N+ line 806. 10 Similarly, the drains of transistors ^ and 2are interconnected to each other by means of diffused N+ lines 802,805, and 807. All of these diffused lines may be delineated simultaneously by means of the N-mask step. As illustrated in Figure 18, diffused N + 15 lines 806 and 807 can extend in various directions on the substrate so as to interconnect with a plurality of additional devices. It is of course also possible to provide one or more contact regions to directly interconnect the N+ diffused lines 806 and 807 to the 20 subsequent metalized interconnections delineated in the M-mask step.
The gates of transistors 1 and 2 are illustrated as being connected to polysilicon lines 800 and 804, respectively. These remote polysilicon lines could be 25 connected to other portions of the circuitry contained on the substrate. In many cases, however, a direct contact ratherthan a remote contact would be provided so as to directly connect the gates of the transistors to the metalized interconnections deline-30 ated by the M-mask step.
Figure 19 schematically illustrates the portion of the substrate circuitry illustrated in Figure 18. Like designators of the elements in Figure 19 correspond to like elements in Figure 18.
35 An important usage for tbe circuitry shown in Figures 18 and 19 would be in the fabrication of monolithic random access memories or read only memories having a large number of memory elements. As indicated in the Summary of the Inven-40 tion, the disclosed fabrication process lends itself to the fabrication of circuits having active devices and associated interconnects having substantially reduced surface area in comparison to circuitry fabricated by prior art methods. Since there are inherent 45 size limitations in the surface area of the silicon substrates contained in integrated circuit chips, the advantageous reduction of the overall surface area of the elements fabricated in accordance with the present invention allows for the production of 50 integrated circuit chips having greater numbers of memory elements. For example, the invention renders it feasible to produce random access memory chips in accordance with the present invention having 256 kilobits of memory storage capability 55 whereas present day prior art fabrication techniques have only been able to produce commercially feasible random access memory chips having 32 kilobits of memory storage capability.
Numerous modifications and variations of the 60 process and device structures and configurations and of integrated circuit designs incorporating such devices will be apparent to those of skill in the art. Whereas N channel devices have been disclosed, it will be apparent that P channel devices instead can 65 be made by this process. The processes have been illustrated as employing bulk silicon, but silicon layers on other substrates, such a silicon-on-sapphire, may be employed in the alternative.

Claims (3)

1. A process for fabricating on a layer of monoc-rystalline silicon a very large scale integrated circuit device, containing field effect transistors, polysilicon interconnect lines, and diffused interconnect lines, comprising the steps of:
defining selected areas of said monocrystalline silicon layer on which the field effect transistors and diffused interconnect lines are to be formed, on the remaining areas of which field oxide is to be formed;
forming a field oxide on said remaining areas and forming a first silicon dioxide layer of a thickness suitable for the gate insulator of a gate for a field effect transistor at least on said selected areas and forming a first layer of silicon nitride over at least said first silicon dioxide layer on said selected areas;
depositing a layer of polysilicon having dopant ions therein over said surface of the device;
oxidizing the surface of said polysilicon layer to form a second layer of silicon dioxide thereon;
applying a second layer of silicon nitride on the surface of said second silicon dioxide layer;
oxidizing said second nitride layerto form an oxynitride layer thereon;
removing, by a selective removal process, all of said oxynitride layer of said second silicon nitride layer and all of said second silicon nitride layer except for the respective portions thereof juxtaposed overthe area in which a polysilicon interconnect line contact is to be formed;
forming a third silicon nitride layer overthe entire surface and oxidizing the third silicon nitride layerto form a silicon oxynitride layer on the surface thereof;
selectively removing all of the oxynitride layer of said third silicon nitride layer except at those regions juxtaposed over areas in which gate electrodes of the field effect transistors and the polysilicon interconnect lines are to be formed;
sequentially removing exposed portions of the oxynitride layer of said second silicon nitride layer exposed by removal of the said third nitride layer portions, of the corresponding, exposed portions of said second nitride layer exposed by removal of those portions of said oxynitride formed from said second nitride layer, and of those portions of said polysilicon layer exposed by removal of portions of said second nitride layer, for defining the gate electrodes of the field effect transistors and the polysilicon interconnect lines;
selectively removing any remaining oxynitride of the first silicon nitride layer from the surfaces of said diffused lines while retaining same over the contact areas of said diffused lines and overthe source and drain regions of the field effect transistors;
removing the portions of the first silicon nitride layer exposed by the removal of the aforesaid portions of the silicon oxynitride layer formed from said first silicon nitride layer;
batch etching the device for removing the first
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silicon dioxide layer exposed by removal of said portions of said first silicon nitride layer thereby to expose the surfaces of the diffused conducting lines and of the polysilicon interconnect lines, except at 5 the areas of the contacts thereto;
doping the diffused conducting lines and the polysilicon lines through their exposed surfaces;
batch etching the device for removing, in sequence, the remaining oxynitride layer portions and 10 the corresponding, thereby exposed nitride layer portions from the contact areas of said diffused lines and said polysilicon conductor lines and from the source and drain regions of the field effect devices; simultaneously doping the aforesaid, exposed 15 source and drain regions and said contact areas of said diffused and said polysilicon interconnect lines;
removing any silicon dioxide layers remaining on the aforesaid contact areas; and selectively applying conducting interconnection 20 lines to said exposed contact areas.
2. A process for fabricating on a layer of monoc-rystalline silicon a very large scale integrated circuit device, containing field effect transistors, polysilicon interconnect lines, and diffused interconnect lines, 25 comprising the steps of:
defining selected areas of said monocrystalline silicon layer on which the field effect transistors and diffused interconnect lines are to be formed, on the remaining areas of which field oxide is to be formed; 30 forming a first silicon dioxide layer of a thickness suitable for the gate insulator of a gate for a field effect transistor on said layer of monocrystalline silicon and forming a first layer of silicon nitride over said first silicon dioxide layer;
35 selectively removing portions of said first silicon nitride layer, leaving portions of said first silicon nitride layer juxtaposed only over said selected areas wherein field effect transistors and diffused interconnect lines are to be formed;
40 oxidizing said monocrystalline silicon layerto produce field oxide overthe surface of said layer of mono-crystalline silicon except at those selected areas juxtaposed beneath the remaining portions of said first silicon nitride layer;
45 depositing a layer of polysilicon having dopant ions therein over said surface of the device;
oxidizing the surface of said polysilicon layerto form a second layer of silicon dioxide thereon; applying a second layer of silicon nitride on the 50 surface of said silicon dioxide layer;
oxidizing said second nitride layer to form an oxynitride layer thereon;
removing, by a selective removal process, all of said oxynitride layer of said second silicon nitride 55 layer and all of said second silicon nitride layer except for the respective portions thereof juxtaposed overthe area in which a polysilicon interconnect line contact is to be formed;
forming a third silicon nitride layer over the entire 60 surface and oxidizing the third silicon nitride layer to form a silicon oxynitride layer on the surface thereof;
selectively removing all of the oxynitride layer of said third silicon nitride layer except at those regions 65 juxtaposed over areas in which gate electrodes of the field effect transistors and the polysilicon interconnect lines are to be formed;
sequentially removing exposed portions of the oxynitride layer of said second silicon nitride layer 70 exposed by removal of said third nitride layer portions of the corresponding, exposed portions of said second nitride layer exposed by removal of those portions of said oxynitride formed from said second nitride layer, and of those portions of said 75 polysilicon layer exposed by removal of portions of said second nitride layer, for defining the gate electrodes of the field effect transistors and the polysilicon interconnect lines;
selectively removing any remaining oxynitride of 80 the first silicon nitride layer from the surfaces of said diffused lines while retaining same overthe contact areas of said diffused lines and overthe source and drain regions of the field effect transistors;
removing the portions of the first silicon nitride 85 layer exposed by the removal of the aforesaid portions of the silicon oxynitride layer formed from said first silicon nitride layer;
batch etching the device for removing the first silicon dioxide layer exposed by removal of said 90 portions of said first silicon nitride layer thereby to expose the surfaces of the diffused conducting lines and of the polysilicon interconnect lines, except at the areas of the contacts thereto;
doping the diffused conducting lines and the 95 polysilicon lines through their exposed surfaces; batch etching the device for removing, in sequence, the remaining oxynitride layer portions and the corresponding, thereby exposed nitride layer portions from the contact areas of said diffused lines 100 and said polysilicon conductor lines and from the source and drain regions of the field effect devices;
simultaneously doping the aforesaid, exposed source and drain regions and said contact areas of said diffused and said polysilicon interconnect lines; 105 removing any silicon dioxide layers remaining on the aforesaid contact areas; and selectively applying conducting interconnection lines to said exposed contact areas.
3. A process for fabricating on a layer of monocrystalline silicon a very large scale integrated circuit 110 device, containing field effect transistors, poiysilicon interconnect lines, and diffused interconnect lines, comprising the steps of:
defining selected areas of said monocrystalline silicon layer on which the field effect transistors and 115 diffused interconnect lines are to be formed, on the remaining areas of which field oxide is to be formed;
forming a field oxide on said remaining areas and forming a first silicon dioxide layer of a thickness suitable for the gate insulator of a gate for a field 120 effect transistor at least on said selected areas and forming a first layer of silicon nitride over at least said first silicon dioxide layer on said selected areas;
depositing a layer of polysilicon having dopant ions therein over said surface of the device; 125 oxidizing the surface of said polysilicon layerto form a second layer of silicon dioxide thereon;
applying a second layer of silicon nitride on the surface of said second silicon dioxide layer;
oxidizing said second nitride layer to form an 130 oxynitride layer thereon;
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removing, by a selective removal process, all of said oxynitride layer of said second silicon nitride layer and all of said second silicon nitride layer exceptforthe respective portions thereof juxtaposed 5 overthe area in which a polysilicon interconnect line contact is to be formed;
selectively forming a protective layer over said device covering those regions juxtaposed over areas in which gate electrodes of the field effect transistors 10 and the polysilicon interconnect lines are to be formed;
sequentially removing exposed portions of the oxynitride layer of said second silicon nitride layer not covered by said protective layer, of the corres-15 ponding, exposed portions of said second nitride layer exposed by removal of those portions of said oxynitride formed from said second nitride layer, and of those portions of said second layer of silicon dioxide and of said polysilicon layer exposed by 20 removal of portions of said second nitride layer, for defining the gate electrodes of the field effect transistors and the polysilicon interconnect lines;
selectively removing any remaining oxynitride of the first silicon nitride layer from the surfaces of said 25 diffused lines while retaining same overthe contact areas of said diffused lines overthe source and drain regions of the field effect transistors;
removing the remaining portions of the protective layer;
30 removing the portions of the first silicon nitride layer exposed by the removal of the aforesaid portions of the silicon oxynitride layerformed from said first silicon nitride layer;
batch etching the device for removing the first 35 silicon dioxide layer exposed by removal of said portions of said first silicon nitride layer thereby to expose the surfaces of the diffused conducting lines and of the polysilicon interconnect lines, except at the areas of the contacts thereto;
40 doping the diffused conducting lines and the polysilicon lines through their exposed surfaces;
batch etching the device for removing, in sequence, the remaining oxynitride layer portions and the corresponding, thereby exposed nitride layer 45 portions from the contact lines of said diffused lines and said polysilicon conductor lines and from the source and drain regions of the field effect devices;
simultaneously doping the aforesaid, exposed source and drain regions and said contact areas of 50 said diffused and said polysilicon interconnect lines; removing any silicon dioxide layers remaining on the aforesaid contact areas; and selectively applying conducting interconnection lines to said exposed contact areas.
Printed for Her Majesty's Stationery Office, by Croydon Printing Company Limited, Croydon, Surrey, 1983.
Published by The Patent Office, 25 Southampton Buildings, London,
WC2A1 AY, from which copies may be obtained.
3. A process for fabricating on a layer of monoc-110 rystalline silicon a very large scale integrated circuit device, containing field effect transistors, polysilicon interconnect lines, and diffused interconnect lines, comprising the steps of:
defining selected areas of said monocrystalline 115 silicon layer on which the field effect transistors and diffused interconnect lines are to be formed, on the remaining areas of which field oxide is to be formed;
forming a field oxide on said remaining areas and forming a first silicon dioxide layer of a thickness 120 suitable for the gate insulator of a gate for a field effect transistor at least on said selected areas and forming a first layer of silicon nitride over at least said first silicon dioxide layer on said selected areas; depositing a layer of polysilicon having dopant 125 ions therein over said surface of the device;
oxidizing the surface of said polysilicon layerto form a second layer of silicon dioxide thereon;
applying a second layer of silicon nitride on the surface of said second silicon dioxide layer; 130 oxidizing said second nitride layer to form an
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GB 2 104 285 A
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oxynitride layer thereon;
removing, by a selective removal process, all of said oxynitride layer of said second silicon nitride layer and all of said second silicon nitride layer 5 exceptforthe respective portions thereof juxtaposed overthe area in which a polysilicon interconnect line contact is to be formed;
selectively forming a protective layer over said device covering those regions juxtaposed over areas 10 in which gate electrodes of the field effect transistors and the polysilicon interconnect lines are to be formed;
sequentially removing exposed portions of the oxynitride layer of said second silicon nitride layer 15 not covered by said protective layer, of the corresponding, exposed portions of said second nitride layer exposed by removal of those portions of said oxynitride formed from said second nitride layer, and of those portions of said polysilicon layer 20 exposed by removal of portions of said second nitride layer, for defining the gate electrodes of the field effect transistors and the polysilicon interconnect lines;
selectively removing any remaining oxynitride of 25 the first silicon nitride layer from the surfaces of said diffused lines while retaining same over the contact areas of said diffused lines overthe source and drain regions of the field effect transistors;
removing the remaining portions of the protective 30 layer;
removing the portions of the first silicon nitride layer exposed by the removal of the aforesaid portions of the silicon oxynitride layerformed from said first silicon nitride layer;
35 batch etching the device for removing the first silicon dioxide layer exposed by removal of said portions of said first silicon nitride layer thereby to expose the surfaces of the diffused conducting lines and of the polysilicon interconnect lines, except at 40 the areas of the contacts thereto;
doping the diffused conducting lines and the polysilicon lines through their exposed surfaces;
batch etching the device for removing, in sequence, the remaining oxynitride layer portions and 45 the corresponding, thereby exposed nitride layer portions from the contact lines of said diffused lines and said polysilicon conductor lines and from the source and drain regions of the field effect devices; simultaneously doping the aforesaid, exposed 50 source and drain regions and said contact areas of said diffused and said polysilicon interconnect lines;
removing any silicon dioxide layers remaining on the aforesaid contact areas; and selectively applying conducting interconnection 55 lines to said exposed contact areas.
4. The process of claim 3 wherein said protective layer comprises a photoresist layer.
5. The process of claim 3 wherein said protective layer comprises a third silicon nitride layer and an
60 associated silicon oxynitride layer formed thereon.
New claims or amendments to claims filed on 13 Sep 1982
Superseded claims 1 to 3 65 New or amended claims:-
1. A process for fabricating on a layer of monocrystalline silicon a very large scale integrated circuit device, containing field effect transistors, polysilicon interconnect lines, and diffused interconnect lines, comprising the steps of:
defining selected areas of said monocrystalline silicon layer on which the field effect transistors and diffused interconnect lines are to be formed, on the remaining areas of which field oxide is to be formed;
forming a field oxide on said remaining areas and forming a first silicon dioxide layer of a thickness suitable for the gate insulator of a gate for a field effect transistor at least on said selected areas and forming a first layer of silicon nitride over at least said first silicon dioxide layer on said selected areas;
depositing a layer of polysilicon having dopant ions therein over said surface of the device;
oxidizing the surface of said polysilicon layerto form a second layer of silicon dioxide thereon;
applying a second layer of silicon nitride on the surface of said second silicon dioxide layer;
oxidizing said second nitride layerto form an oxynitride layer thereon;
removing, by a selective removal process, all of said oxynitride layer of said second silicon nitride layer and all of said second silicon nitride layer exceptforthe respective portions thereof juxtaposed overthe area in which a polysilicon interconnect line contact is to be formed;
forming a third silicon nitride layer over the entire surface and oxidizing the third silicon nitride layerto form a silicon oxynitride layer on the surface thereof;
selectively removing all of the oxynitride layer of said third silicon nitride layer and all of said third silicon nitride layer except at those regions juxtaposed over areas in which gate electrodes of the field effect transistors and the polysilicon interconnect lines are to be formed;
sequentially removing exposed portions of the oxynitride layer of said second silicon nitride layer exposed by removal of the said third nitride layer portions, of the corresponding, exposed portions of said second nitride layer exposed by removal of those portions of said oxynitride formed from said second nitride layer, and of those portions of said second layer of silicon dioxide and of said polysilicon layer exposed by removal of portions of said second nitride layer, for defining the gate electrodes of the field effect transistors and the polysilicon interconnect lines;
selectively removing any remaining oxynitride of the first silicon nitride layer from the surfaces of said diffused lines while retaining same overthe contact areas of said diffused lines and overthe source and drain regions of the field effect transistors;
removing the portions of the first silicon nitride layer exposed by the removal of the aforesaid portions of the silicon oxynitride layerformed from said first silicon nitride layer;
batch etching the device for removing the first silicon dioxide layer exposed by removal of said portions of said first silicon nitride layer thereby to expose the surfaces of the diffused conducting lines
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GB 2 104 285 A
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and of the polysilicon interconnect lines, except at the areas of the contacts thereto;
doping the diffused conducting lines and the polysilicon lines through their exposed surfaces; 5 batch etching the device for removing, in sequence, the remaining oxynitride layer portions and the corresponding, thereby exposed nitride layer portions from the contact areas of said diffused lines and said polysilicon conductor lines and from the 10 source and drain regions of the field effect devices; simultaneously doping the aforesaid, exposed source and drain regions and said contact areas of said diffused of said polysilicon interconnect lines; removing any silicon dioxide layers remaining on 15 the aforesaid contact areas; and selectively applying conducting interconnection lines to said exposed contact areas.
2. A process for fabricating on a layer of monocrystalline silicon a very large scale integrated circuit 20 device, containing field effect transistors, polysilicon interconnect lines, and diffused interconnect lines, comprising the steps of:
defining selected areas of said monocrystalline silicon layer on which the field effect transistors and 25 diffused interconnect lines are to be formed, on the remaining areas of which field oxide is to be formed;
forming a first silicon dioxide layer of a thickness suitable for the gate insulator of a gate for a field effect transistor on said layer of monocrystalline 30 silicon and forming a first layer of silicon nitride over said first silicon dioxide layer;
selectively removing portions of said first silicon nitride layer, leaving portions of said first silicon nitride layer juxtaposed only over said selected 35 areas wherein field effect transistors and diffused interconnect lines are to be formed;
oxidizing said monocrystalline silicon layerto produce field oxide over the surface of said layer of monocrystalline silicon except at those selected 40 areas juxtaposed beneath the remaining portions of said first silicon nitride layer;
depositing a layer of polysilicon having dopant ions therein over said surface of the device;
oxidizing the surface of said polysilicon layerto 45 form a second layer of silicon dioxide thereon; applying a second layer of silicon nitride on the surface of said silicon dioxide layer;
oxidizing said second nitride layerto form an oxynitride layer thereon;
50 removing, by a selective removal process, all of said oxynitride layer of said second silicon nitride layerand all of said second silicon nitride layer except for the respective portions thereof juxtaposed overthe area in which a polysilicon interconnect line 55 contact is to be formed;
forming a third silicon nitride layer over the entire surface and oxidizing the third silicon nitride layerto form a silicon oxynitride layer on the surface thereof;
60 selectively removing all of the oxynitride layer of said third silicon nitride layer and all of said third silicon nitride layer except at those regions juxtaposed over areas in which gate electrodes of the field effect transistors and the polysilicon intercon-65 nect lines are to be formed;
sequentially removing exposed portions of the oxynitride layer of said second silicon nitride layer exposed by removal of said third nitride layer portions, of the corresponding, exposed portions of 70 said second nitride layer exposed by removal of those portions of said oxynitride formed from said second nitride layer, and of those portions of said second layer of silicon dioxide and of said polysilicon layer exposed by removal of portions of said 75 second nitride layer, for defining the gate electrodes of the field effect transistors and the polysilicon interconnect lines; selectively removing any remaining oxynitride of the first silicon nitride layer from the surfaces of said diffused lines while retaining 80 same overthe contact areas of said diffused lines and overthe source and drain regions of the field effect transistors;
removing the portions of the first silicon nitride layer exposed by the removal of the aforesaid 85 portions of the silicon oxynitride layerformed from said first silicon nitride layer;
batch etching the device for removing the first silicon dioxide layer exposed by removal of said portions of said first silicon nitride layer thereby to 90 expose the surfaces of the diffused conducting lines and of the polysilicon interconnect lines, except at the areas of the contacts thereto;
doping the diffused conducting lines and the polysilicon lines through their exposed surfaces; 95 batch etching the device for removing, in sequence, the remaining oxynitride layer portions and the corresponding, thereby exposed nitride layer portions from the contact areas of said diffused lines and said polysilicon conductor lines and from the 100 source and drain regions of the field effect devices; simultaneously doping the aforesaid, exposed source and drain regions and said contact areas of said diffused and said polysilicon interconnect lines; removing any silicon dioxide layers remaining on 105 the aforesaid contact areas; and selectively applying conducting interconnection lines to said exposed contact areas.
GB08220289A 1978-05-26 1982-07-13 Manufacture of integrated circuits Expired GB2104285B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/909,886 US4277881A (en) 1978-05-26 1978-05-26 Process for fabrication of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US05/913,182 US4221044A (en) 1978-06-06 1978-06-06 Self-alignment of gate contacts at local or remote sites

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GB2104285B GB2104285B (en) 1983-07-06

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GB08220264A Expired GB2106315B (en) 1978-05-26 1982-07-13 Manufacture of integrated circuits

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0660393A1 (en) * 1993-12-23 1995-06-28 STMicroelectronics, Inc. Method and dielectric structure for facilitating overetching of metal without damage to inter-level dielectric

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503601A (en) * 1983-04-18 1985-03-12 Ncr Corporation Oxide trench structure for polysilicon gates and interconnects
CA1258320A (en) * 1985-04-01 1989-08-08 Madhukar B. Vora Small contactless ram cell
US5439846A (en) * 1993-12-17 1995-08-08 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6284584B1 (en) * 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0660393A1 (en) * 1993-12-23 1995-06-28 STMicroelectronics, Inc. Method and dielectric structure for facilitating overetching of metal without damage to inter-level dielectric
US5766974A (en) * 1993-12-23 1998-06-16 Sgs-Thomson Microelectronics, Inc. Method of making a dielectric structure for facilitating overetching of metal without damage to inter-level dielectric

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GB2024505A (en) 1980-01-09

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