JPS60207363A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce warpage generated during an element manufacturing process by minimizing the occupying rate, in which the area of a semiconductor layer electrically isolated by a dielectric from semiconductor substrate occupies in total chip area, in a semiconductor device containing dielectric isolating structure. CONSTITUTION:One parts of the surface of a P type silicon substrate 1 are oxidized selectively to form SiO2 films 2, 2 as dielectric isolating regions, and one parts of the SiO2 films 2, 2 are removed selectively through etching to shape insular single crystl silicon 5, 5 isolated by dielectrics. Active elements containing CMOSs are formed in single crystal silicon isolated by dielectrics by the SiO2 films 2, 2 and an active element such as a MOS transistor on other surface of the substrate 1 respectively according to a normal manufacturing process. Consequently, when the areas of single crystal silicon isolated nt dielectrics occupy 30% or less of total chip area, warpage generated during the manufacturing process is reduced, and yield is improved remarkably.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device including a dielectric isolation structure.

[Technical background of the invention and its problems]

Generally, in a semiconductor integrated circuit, a single chip includes many various integrated circuit elements (transistors, diodes, etc.).
(resistance, capacitance, etc.) are formed, and these elements are isolated from each other. A dielectric isolation method is used as one method of element isolation. This dielectric isolation method completely isolates the periphery of a semiconductor layer in which active elements are formed using a dielectric.

This method has the advantage that the latch-up in the 0MO8 structure is suppressed and the occurrence of soft errors due to α rays can be reduced, so that the malfunction rate of the element can be extremely reduced. Furthermore, the presence of the insulator tends to reduce the ground capacitance and increase the operating speed of the device.

The method for achieving this dielectric separation is as follows: (I> Form an amorphous insulating layer on a silicon substrate, deposit amorphous silicon on top of it, and then form single crystal silicon by melting or in-phase growth. (so-called 5ol). ゛(II) A method of directly forming a single crystal silicon layer by vapor phase growth on an insulating substrate (for example, a sapphire substrate) (so-called 5O8).

(I [[) A method in which an insulator is formed around a predetermined portion of a single crystal silicon substrate, and single crystal silicon is formed only in the predetermined portion.

etc. are known.

There have already been many reports regarding the method (1) above (for example, Applied Physics vol. 1.53, ρp, 27-32), such as burying an insulator, implanting oxygen ions in high concentration, and anodizing. A method of oxidizing porous silicon is known. There are also examples of experimentally forming integrated circuits.

Incidentally, in recent years, as the miniaturization and large-scale integration of elements have progressed from an economic standpoint, requirements for wafer flatness during pattern exposure have become considerably stricter. For example, in the case of an exposure device using an ideal lens, the wavelength is 5000.
In order to irradiate IIl light and form a pattern with a line width of 1.5 to 1 um, the wafer surface must be misaligned with the focal plane by 1
．． It is said that it must be within 4-0.7p (
Nikkei Electronics, special issue “Micro Devices”
ρ, 91° (1983)).

However, in dielectric isolation structures, even if we screen and use those with warpage of 2 or less before forming the element structure, many of them warp more than 10 or more in the actual device manufacturing process. This is a major obstacle to forming a pattern.

This is because high-temperature processes reaching temperatures of 900 to 1000 degrees Celsius are normally used to manufacture integrated circuits, but the coefficient of thermal expansion of the single crystal silicon and the insulator used for separation is This is because it is difficult to perfectly match the temperature. In particular, in the conventional dielectric isolation method, the area of the semiconductor layer separated by the dielectric and in which the active elements are formed occupies most of the total chip area, so the mismatch in the thermal expansion coefficients has a large effect. Therefore, due to repeated high-temperature processes, wafers with a dielectric isolation structure are significantly warped during the manufacturing process, causing a decrease in yield.

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned drawbacks, and aims to provide a semiconductor device that has a dielectric isolation structure, has less warpage during the device manufacturing process, has a high yield, and is high-speed and highly reliable. That is.

[Summary of the invention]

The semiconductor device of the present invention includes an active element formed on the surface of a semiconductor substrate in a semiconductor layer electrically insulated from the substrate by a dielectric, and an active element formed on the surface of the semiconductor substrate in electrical continuity with the substrate. The semiconductor device having an active element is characterized in that the area of the semiconductor layer electrically insulated from the semiconductor substrate by a dielectric is 30% or less of the total chip area.

According to such a semiconductor device, since the area of the semiconductor layer electrically insulated from the semiconductor substrate by the dielectric occupies a small proportion of the total chip area, the coefficient of thermal expansion between the semiconductor layer and the dielectric is small. The difference does not have much influence,
Warpage during the manufacturing process is reduced and yields are significantly improved compared to conventional methods. Furthermore, if an active element having, for example, an 0MO8 structure is formed in a semiconductor layer that is electrically insulated from the semiconductor substrate by a dielectric, latch-up can be prevented.
Reliability can be improved. In addition, a logical operation section,
The dielectric isolation structure of the present invention can be applied to a so-called one-chip microcomputer having other storage parts, etc., and active elements constituting a logic operation part can be formed in a semiconductor layer electrically insulated from a semiconductor substrate by a dielectric. For example, the malfunction rate caused by soft errors caused by alpha rays can be significantly reduced.

[Embodiments of the invention]

Examples of the present invention will be described below along with the manufacturing method shown in FIGS. 1(a) to (d).

First, a portion of the surface of a P-type silicon substrate 1 having a diameter of 3 inches was selectively oxidized to form a 5i02 film 2.2 that would serve as a dielectric isolation region. Next, SiO2 film 2.
A portion of 2 was selectively etched away to form 3.3 (as shown in FIG. 1(a)). Next, a mask material (not shown) was formed on the surface of the substrate 1, and then a polycrystalline silicon film was deposited on the entire surface. Subsequently, the entire surface was etched back, and after burying polycrystalline silicon 4.4 only in the groove 3.3, the mask material was removed (as shown in FIG. 3B). Next, an oxide film and a nitride film (not shown) were sequentially deposited on the entire surface, and then annealing was performed using a laser until the polycrystalline silicon 4.4 began to melt. During this laser annealing,
No change occurs on the surface of the bulk substrate 1 on which the s + 02 film 2.2 is not formed.

This is s + 02 surrounding polycrystalline silicon 4.4
Film 2.2 has low thermal conductivity, so polycrystalline silicon 4.4
Although the temperature of the silicon substrate 1 increases, it is presumed that because the silicon substrate 1 has high thermal conductivity, the temperature does not increase much. Next, after removing the nitride film and the oxide film, the substrate 1
Island-shaped single crystal silicon 5.5 with dielectric separation is formed on a part of the surface (as shown in FIG. 2C). In addition, the size of the chip formed in the above process is 8IIllll + square,
The size of the island-shaped single crystal silicon 5.5 was set to 15-square. Further, wafers were formed in which the ratio of the area S of the island-shaped single crystal silicon 5 to the chip area S was 50%, 40%, and 20%, respectively.

Next, 25 wafers with a warpage of 5 or less when using a vacuum chuck are selected from each of the above wafers, and the n-type element region 6 is formed according to the normal manufacturing process as shown below.
Formation of n-type element region 7, formation of gate oxidation PIA 8, formation of gate electrode 9 by patterning after depositing impurity-doped polycrystalline silicon, formation of gate electrode 9...
・n+ by ion implantation using resist i・ as a mask
Formation of type source and drain regions 10.11.12.13 and n+ diffusion layer 14 for bias, goo 1-electrode 9...
・And p+ type source and drain regions 15 and 16 and p+ for bias by ion implantation using resist as a mask
A diffusion layer 17 was formed, a contact hole was formed after the interlayer insulating film 18 was deposited, and a wiring 19 was formed by patterning after the wiring metal was deposited. Through the above steps, 5i
An active element including 0MO8 in single crystal silicon dielectrically isolated by 02112.2, and an active element such as a MOS l-transistor were formed on the surface of the other substrate 1 (as shown in FIG. 3(d)). Note that the typical pattern width in this example was 3 capes.

At this time, the photo-etching process (PEP) of the above-mentioned integrated circuit manufacturing process is used.
In the process), those with warpage of 10IIJn or more were difficult to pattern match, so they were successively excluded from the process. As a result, the number N of wafers remaining until the final process among the 25 wafers for each condition is shown in the table below.

As is clear from the above table, if the area of single crystal silicon that is dielectrically isolated is less than 30% of the total chip area, there will be less warping during the manufacturing process, and the next PEP process can be performed. The number of wafers that can be processed has increased significantly, and the yield has significantly improved. Moreover, by forming elements on the surface of the substrate 1 which is not dielectrically separated and making them coexist, it was possible to manufacture an integrated circuit without reducing the degree of integration of the integrated circuit. In addition, 0MO8 formed in single crystal silicon dielectrically separated from the substrate 1
No latch-up phenomenon was observed.

Furthermore, as shown in FIG. 2, one chip 21 includes a CPU.
22, memory controller 23, memory 24, input/output port (IOP) 2 connected to external peripheral device 31
5 and a clock 26 that sends clock signals to these.
The present invention is applied to a one-chip microcomputer in which .
7, and the other parts were formed on the silicon substrate surface.

When this integrated circuit was operated under a radiation source, the CPU
The malfunction rate due to soft errors in 21 is CP
This was reduced to 5% or less compared to the case where LI was formed on the silicon surface. In the case of microcomputers, it goes without saying that the malfunction rate of the CPU has a large correlation with the malfunction rate of the entire system.

Note that in the above example, a dielectric separation method was used in which polycrystalline silicon was embedded in the 8102 film and then single crystal silicon was formed using laser aninyl, but the method is not limited to this. The method is to anodize a part of the silicon substrate to make porous silicon,
A dielectric isolation structure obtained by a method such as oxidizing porous silicon can also provide the same effect as in the above embodiment.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a semiconductor device having a high yield, high speed, and high reliability dielectric isolation structure.

[Brief explanation of drawings]

1(a) to (d) are cross-sectional views showing the observation process for obtaining a semiconductor device with a dielectric isolation structure in an embodiment of the present invention, and FIG. 2 is a sectional view showing a dielectric structure in another embodiment of the present invention. FIG. 1 is a configuration diagram of a microcomputer having a separate structure. 1...p-type silicon substrate, 2...SiO2 film, 3...
... Groove, 4... Polycrystalline silicon, 5... Single crystal silicon, 6... N-type element region, 7... N-type element region,
8... Gate oxide film, 9... Gate electrode, 10.1
1.12.13...n++ source, drain region, 1
4...n+ type scattered layer 15.16...p++ source, drain region, 17...p+ type scattered layer 18...
Interlayer insulating film, 19... Wiring, 21... Chip, 22
...CPU, 23...Memory controller, 24.
...Memory, 25...Input/output capo-I~, 26...
Clock, 27... Dielectric (Si02), 31...
Peripheral equipment. Applicant's agent Patent attorney Takehiko Suzue

Claims (3)

[Claims] (1) An active element formed on the surface of a semiconductor substrate in a semiconductor layer electrically insulated from the substrate by a dielectric, and an active element formed on the surface of the semiconductor substrate in electrical continuity with the substrate. 1. A semiconductor device comprising: a semiconductor layer electrically insulated from the semiconductor substrate by a dielectric; an area of the semiconductor layer being 30% or less of the total chip area; (2) The semiconductor device according to claim 1, wherein the active element formed in the semiconductor layer electrically insulated from the semiconductor substrate by a dielectric has an 0MO8 structure. (3) An active element formed in a semiconductor layer electrically insulated from a semiconductor substrate by a dielectric material is an element that constitutes a logical operation section, and an element that is electrically connected to the substrate is an element that constitutes a storage section. A semiconductor device according to claim 1.