JPS60195798A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form a power supply terminal with one pin so as to enlarge the capacity of a memory and reduce the number of wiring, by providing a circuit which reads out the power supply for a writing voltage and converts the power supply into the power supply for a reading voltage. CONSTITUTION:At the time of readout, a reading voltage VCC of a low voltage is applied to a power supply terminal 12 and also to the output terminal OUT of a regulated power supply circuit 13, and then, the reading out operation is performed. On the other hand, at the time of writing, a writing voltage VPP of a high voltage is applied to the power supply terminal 12 and the low voltage VCC is outputted to the output terminal OUT. Therefore, the high voltage VPP is directly supplied to X- and Y-address decoders 2 and 3 and the low voltage VCC is supplied to a peripheral circuit 15, and then, a program control circuit 6 is operated by a program signal P from a control terminal 11. Thus the writing operation is performed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a write voltage power supply v
An EF ROM (E
rasable and prograa+able
This is related to Read OnlyMe*ory).

(Conventional technology) FIG. 1 shows a block diagram of an example of a conventional EPROM.

In the figure, l is the address buffer, 2゜3 is X and Y
Address decoder, 4 is a memory array group, 5 is a data input/output circuit, 6 is a program control circuit, 7 is a read voltage power supply terminal, 8 is a write voltage power supply terminal, 9 is an address input terminal, 10 is a data input/output terminal, 11 is the program control terminal.

The address buffer 1, the X and Y address decoders 2.3, the data input/output circuit 5, and the program control circuit 6 are connected via a terminal 7 to the voltage type? IJvcc is supplied, and a write voltage power supply vPP is supplied via a terminal 8 to the X and Y address decoders 2.3.

Next, the operation will be explained.

In a conventional EFROM, when reading, the voltage at terminal 7 is continuously input to a low voltage (usually 5V), which is the voltage vCC.
), the voltage at terminal 8 is similarly set to a low voltage, and address signal A is input from address input terminal 9 to address decoders 2 and 3 via address buffer l. Then, the contents of the address of the memory array group 4 selected by the address decoder 2.3 go through the Y address decoder 3 to the input/output buffer circuit 5, and are output from the data input/output terminal 10, thus reading out the data D. .

On the other hand, when writing, the voltage at terminal 8 is set to a high voltage (usually 21 to 25 V), which is the write voltage VPP, while the voltage at terminal 7 is maintained at a low voltage, and the program signal P is sent to program control terminal 11. Enter. Then, the program control circuit 6 operates and the X and Y address decoders 2
, 3 to the program mode, and the Y address decoder 3 applies a high voltage to the selected memory address at this time.
In this way, data D is written.

The conventional EFROM is configured as described above, and has a drawback in that two power supply terminals are required because the read voltage type @VCC terminal and the write voltage power supply vPP terminal are provided separately.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by providing a transformer circuit that sequentially outputs a write voltage power source and transforms it into a voltage power source, the power terminal can be changed to one power source.
The purpose of the present invention is to provide a semiconductor device with improved performance.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a block diagram of a semiconductor device according to an embodiment of the present invention, in which 1 is an address buffer;
are X and Y address decoders, 4 is a memory array group, 5 is
1 is a data input/output circuit, 6 is a program control circuit, 9 is an address input terminal, IO is a data input/output terminal, and 11 is a program control terminal. 12 is a power supply terminal, and 13 is a stabilized power supply circuit. Address buffer 1. X and Y address decoders 2, 3. Data input/output circuit 5. A power supply voltage is directly supplied to the Y address decoders 2 and 3 from the power supply terminal 12.

Here, the power supply terminal 1z is one terminal that shares the conventional write voltage power supply terminal and read voltage power supply terminal, and the continuous voltage (usually 5 V) is applied during reading, and the write voltage (usually 21 to 25 V) is used during writing. It is applied.

Further, the stabilized power supply circuit 13 connected to the power supply terminal 12 is
When the continuous voltage VCC (usually 5V) is applied to the power supply terminal 12, the read voltage VCC is output as is to the output terminal OUT, and when the write voltage VPP (usually 21 to 25V) is applied, the voltage is dropped. Then the voltage V, C continues
C<normally 5V).

An example of the configuration of the stabilized power supply circuit 13 is shown in FIG. 3, and its electrical characteristics are shown in FIG. 4. In FIG. 3, Trl and Tr2 are depressing type N-channel MO3) transistors. In this stabilized power supply circuit 13, the 41st!
As can be seen from 1, when the voltage at the input terminal IN exceeds a certain level, the voltage at the output terminal OUT becomes constant.

In the above configuration, the X and Y address decoders 2 and 3 write data into the memory circuit when high voltage power is applied, and write successive write circuit 14 reads data from the memory circuit when low voltage power is applied. The address buffer 1, the data input/output circuit 5, and the program control circuit 6 constitute a peripheral circuit 15 of the write/read circuit which is activated by application of a low voltage power supply, and the stabilized power supply circuit 13 transforms the power into a low voltage power and supplies it to the peripheral circuit 15 when a high voltage power is applied, and supplies the power as it is to the peripheral circuit 15 when a low voltage power is applied.
This is a transformer circuit that supplies power to the

Next, the operation of this device will be explained. First, during continuous reading, a low-voltage read voltage vCC is applied to the power supply terminal 12, and the continuous reading voltage VCC is also output to the output terminal OUT of the stabilized power supply circuit 13, so that reading can be performed in the same way as in the conventional case. .

Also, during writing, a high voltage write voltage VPP is applied to the power supply terminal 12, and the output terminal OUT of the stabilized power supply circuit 13 is applied to the power supply terminal 12.
A low voltage vCC is output to the X and Y address decoders 2.3, a high voltage vPP is applied directly to the The program control circuit 6 is activated by the signal P, and writing is executed.

In the device of this embodiment as described above, the write voltage power supply terminal and the read voltage power supply terminal are shared, and when a high voltage write voltage is applied, the voltage is divided into the write voltage system and the read voltage system by the stabilizing power supply circuit. Since the power supply terminal is divided into 1 bin, the remaining bin can be used as an address input terminal etc. to expand the memory capacity and reduce the number of wiring such as printed circuit boards.

In the above embodiment, the stabilized power supply circuit shown in FIG. 3 was used as the transformer circuit, but any of the various stabilized power supply circuits may be used as long as it achieves the same function. Needless to say.

〔Effect of the invention〕

As described above, according to the present invention, the write voltage power supply terminal and the read voltage power supply terminal are shared, and when high voltage power is applied, it is transformed to a low voltage by the transformer circuit and supplied to the peripheral circuit. , the number of power supply terminals can be reduced to one bin, and as a result, excellent effects such as an increase in memory capacity and a reduction in wiring can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional EFROM, Fig. 2 is a block diagram of a BFROM according to an embodiment of the present invention, Fig. 3 is a diagram showing an example of the configuration of a stabilizing power supply circuit in the above-mentioned EFROM, and Fig. 4 is a block diagram of the above-mentioned EFROM. FIG. 3 is a diagram showing input/output characteristics of a stabilized power supply circuit. 4...Memory array group (memory circuit), 12...Power supply terminal, 13...Stabilized power supply circuit (transformer circuit), 14.
...Writing/reading circuit, 15... Peripheral circuit. In the drawings, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 2 Figure 3 Figure 4 Input voltage → Procedural amendment (voluntary) 5-2, Name of the invention Cattle conductor device 3, Person making the amendment, Details of the invention in the specification to be amended. Explanation column, content of correction (1) “Y address decoder 3” on page 3, line 17 of the specification
” is corrected to “X and Y address decoder 2.3”. that's all

Claims (1)

[Claims] (1) A memory circuit that stores data, a write/read circuit that writes data in the memory circuit when a high voltage power supply is applied and reads data from the memory circuit when a low voltage power supply is applied, and is activated by the application of a low voltage power supply. and a peripheral circuit that controls the write/read of the write/read circuit, and when a high voltage power supply is applied, the power supply is transformed into a low voltage power supply and supplied to the above peripheral circuit, and when a low voltage power supply is applied, the power supply is directly connected to the above. A semiconductor device W1゜ characterized by comprising a transformer circuit that supplies peripheral circuits, and one power supply terminal that is connected to the write/read circuit and the transformer circuit and to which a high voltage power supply or a low voltage power supply is applied from the outside.