JPH03283093A - Writing circuit to e2prom - Google Patents

Abstract

PURPOSE:To reduce the number of times for writing data to the E<2>PROM by providing a circuit which inhibits the writing automatically when writing the data of the same contents while comparing the holding data of the E<2>PROM with input data. CONSTITUTION:A data bit and a write enable signal are inputted from an external part to a buffer circuit 1, and the data bit is outputted as the writing data when the write enable signal is turned on. The E<2>PROM 2 writes the data bit to an internal memory when the write enable signal is turned on, reads out and outputs the holding data bit of the internal memory when the write enable signal is turned off. A comparator 3 compares the data bit with the holding data bit to be outputted from the E<2>PROM 2, and when they are coincident, the write inhibit signal is turned on and outputted. In a gate 4, the write instruction signal to be inputted from the external part is outputted as the write enable signal only when the write inhibit signal is turned off. Thus, the number of times for writing data to the E<2>PROM can be reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a write circuit for E2 PROM, which is an electrically erasable PROM, and in particular, a write circuit for E2 FROM that can reduce the number of times of writing to E2 PROM. Regarding.

[Conventional technology]

The conventional write circuit to E” FROM is E2PROM.
It is now possible to write the same contents as those already written in the E2 PROM, but in order to avoid writing the same contents, it is necessary to read the contents of the E2 PROM with a CPU etc. and write it. The software was prohibited from writing if the content was the same.

[Problem to be solved by the invention]

The conventional writing circuit to the E2 PROM described above uses software that prohibits writing of the same content that has already been written to the E2 FROM, and therefore has the disadvantage that the software processing becomes complicated.

[Means to solve the problem]

A write circuit for an E2 PROM of the present invention receives data bits and a write enable signal from the outside, and includes a buffer circuit that outputs the data bits as write data when the write enable signal is on, and a buffer circuit that outputs the data bits as write data when the write enable signal is on. an E2 FROM that writes the previous data bit to the internal memory when the write enable signal is on, and reads and outputs the data bit held in the internal memory when the write enable signal is off; and the data bit and the held data output from the E2 FROM. A comparator that outputs a write inhibit signal as ON when the bits are compared and match, and outputs the write instruction signal as a write enable signal only when the write inhibit signal input from the outside is OFF. It has a gate.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a signal timing chart of this embodiment.

In FIG. 1, when the buffer circuit 1 receives n-bi soto input data (FIG. 2(a)) through terminals 5A to 5N, a write enable signal (
Only when FIG. 2(e)) is on, n-bit data input is output to the terminals 7A to 7N (FIG. 2(b)). On the other hand, E
2 When the write enable signal input from terminal 6 is on, the PROM writes n bits of data input via terminals 7A to 7N to the internal memory, and when it is off, it writes n bits of data held in the internal memory to terminal 7A. ~7N
Output to. Also, the comparator 3 outputs the n cut data from the terminals 5A to 5N and the E2 output from the terminals 7A to 7N4.
Input and compare data held in the internal memory of FROM.

If the data contents match as a result, a write inhibit signal is output to the terminal 8 (FIG. 2(d)). Gate 4 inputs the write inhibit signal from terminal 8 and a write instruction (see FIG. 2 (C)) input from the outside via terminal 9, and sends the write instruction signal to terminal 6 only when the write inhibit signal is off. It is output as a write enable signal (FIG. 2(e)).

〔Effect of the invention〕

As explained above, the present invention prevents redundant writing by providing a circuit that automatically disables writing when attempting to write data with the same content using a comparator between data held in the E2 PROM and input data. It can be reduced. Therefore, the number of times the E2PROM is written can be reduced, which has the effect of extending the life of the E2PROM.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing chart of this embodiment. 1...Buffer circuit, 2...E2 PROM, 3.
...Comparator, 4...Gate, 5A~5N, 6.7A~
7N. 8.9−°゛Terminal°; human speech? : Shidohara
Shinsaku 1 Diagram 2

Claims (1)

[Claims] A buffer circuit receives data bits and a write enable signal from the outside, outputs the data bits as write data when the write enable signal is on, and writes the data bits into an internal memory when the write enable signal is on. , when the E^2PROM reads and outputs the data bits held in the internal memory when the write enable signal is off, and the data bits and the data bits outputted from the E^2PROM are compared and match, The device is characterized by comprising a comparator that outputs a write inhibit signal as ON, and a gate that outputs the write instruction signal as a write enable signal only when the write instruction signal inputted from the outside is OFF. E^2P
Write circuit to ROM.