JPH04311228A - Terminal function setting circuit - Google Patents

Abstract

PURPOSE:To prevent the setting of a holding state by the output data of a microcomputer itself even when the value of a direction register is rewritten by the runaway of a CPU, erroneous programming, etc., at the time of selecting a stopping mode. CONSTITUTION:An assertion inhibiting means 10 which is provided with a terminal used as a input-output port or for stopping a control input (hold request input or ready input) and closes so as to inhibit the assertion from a direction register 4 to a gate (output buffer 4) contained in a data outputting route 20 in modes other than a normal mode (mainly, stopping mode) which uses the terminal 5 as the input-output port is provided.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention prevents a terminal function setting circuit, particularly a microcomputer (hereinafter referred to as a microcomputer), from being held by its own output when it goes out of control or due to a programming error. It is about things.

0002

2. Description of the Related Art FIG. 3 is an example of a block diagram of a terminal function setting circuit in which a conventional microcomputer input/output port and a stop control input such as a hold request input or a ready input are shared. In the figure, reference numeral 1 indicates a data bus (hereinafter referred to as internal data bus) inside the microcomputer, which is connected to the CPU. 2 is an output data latch that latches output data; 3 is a direction register that controls the input/output direction of the port; 4 is an output buffer as a gate that is active while the output buffer active signal from the direction register 3 is asserted; 5 is an input/output terminal, 6 is a data line 6a
A data input path 7 is composed of a buffer 6b inserted in the data line 7a and transmits input data to the internal data bus 1. A direction register 3 is composed of a buffer 7b inserted in the data line 7a.
8 is a hold control means that holds the microcontroller when there is a hold request input, and 9 is a hold control means when the hold request input or ready input function is selected (hereinafter referred to as stop mode). This is an AND gate that is opened and held only at the point (described as ). 20 is a data output path that outputs data in the CPU to terminal 5, and the data line 20
It consists of an output data latch 2 and an output buffer 4 interposed in a. It is activated and deactivated by turning on and off the buffer 4 or the buffer 6b.

Next, the operation will be explained. When using the terminal 5 as a normal input/output port (hereinafter referred to as normal mode), the input/output direction is determined by first writing a value to the direction register 3. In this figure, "H" is an output, and "L" is an input. In the case of output, the output data is sent to the output data latch 2 through the internal data bus 1 and output to the input/output terminal 5 via the output buffer 4.

In the case of input, the input data input to the input/output terminal 5 passes through the data input path 6 to the internal data bus 1.
sent to.

[0005] When the stop mode is selected, the port is fixed to input. If there is a hold request input here, the AND gate 9 performs a logical product of the "H" active hold request input and the stop mode selection signal B, and inputs the result to the hold control means 8, where a hold is applied to the microcomputer. That is, the gate 9 is opened in the stop mode, and the C
PU is stopped.

[0006]

[Problem to be solved by the invention] With conventional microcontrollers, if the value of the direction register is changed due to a CPU runaway or a programming error when the stop mode is selected, the hold is applied by the output data of the microcontroller itself. There was a problem.

The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a microcomputer that inhibits the assertion of the output buffer active signal from the direction register when the stop mode is selected.

[0008]

[Means for Solving the Problems] The present invention enables and deactivates the data output path 20 and the data input path 6 to use the terminal 5 as an input/output port in a mode other than the normal mode (mainly in the stop mode). The device is equipped with an assertion inhibiting means 10 that closes the gate (output buffer 4) and inhibits the direction register 3 from asserting the gate (output buffer 4).

[0009]

[Operation] In the present invention, in the normal mode, the output of the direction register 3 is asserted to the gate (output buffer 4) of the data output path 20;
0 and data input path 6 are activated and deactivated, and the terminal (
The input/output terminal 5) is used as an input/output port, but when the mode is other than the normal mode, mainly the stop mode, the assertion inhibiting means 10 closes and the output gate of the direction register 3 (
Assertion to output buffer 4) is prohibited.

0010

[Embodiments] Hereinafter, embodiments of the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, the same or equivalent parts as in FIG. 3 are given the same reference numerals. 10 is opened by the normal mode selection signal A,
This means is closed when the selection signal A is not supplied, that is, prohibits assertion of the output buffer active signal to the output buffer 4 when the mode is not normal (hereinafter referred to as output buffer active signal assertion prohibition means). Further, FIG. 2 shows an example of the configuration of the output buffer active signal assertion inhibiting means. Next, the operation will be explained. In this embodiment, 1 to 9 operate in the same way as a conventional microcomputer. By providing the output buffer active signal assertion inhibiting means 10 that takes the logical product of the output buffer active signal from the direction register 3 and the normal mode selection signal A and the "H" active state, the output buffer 4 is activated only when the normal mode is selected. It can be done. When in stop mode (other than normal mode), normal mode selection signal A
is "L", the assertion inhibiting means 10 is closed, and the output buffer 4 does not operate, so there is no possibility that a hold will be applied when the CPU runs out of control.

[0011]

As described above, according to the present invention, since an assertion inhibiting means is provided that inhibits assertion to the gate in the data output path when the mode is other than the normal mode, it is possible to prevent CPU runaway and program errors when the stop mode is selected. Even if the value of the direction register is rewritten due to a change in the value of the direction register, it is possible to prevent the output data from being held by the microcomputer itself.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a terminal function setting circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of an assertion inhibiting means according to an embodiment of the present invention.

FIG. 3 is a block diagram of a conventional terminal function setting circuit.

[Explanation of symbols]

1 Internal data bus 3 Direction register 4 Output buffer 5 Input/output terminal 6 Data input path 8 Hold control means 9 AND gate 10 Output buffer active signal assertion prohibition means 20 Data output path

Claims (1)

[Claims] 1. A data output path that is inserted between an internal data bus connected to a CPU and one terminal, and that outputs output data of the internal data bus to the terminal, and that outputs input data from the terminal. A data input path input to the internal data bus, a direction register having data for activating or inactivating the data output path and the data input path and setting the terminal as an input/output port, and a stop mode from the outside. In a terminal function setting circuit equipped with a gate that is opened and closed based on a selection signal to receive a stop control input such as a hold request input or a ready input from the above terminal, when the above terminal is used as an input/output port in a mode other than the normal mode. A terminal function setting circuit comprising an assertion inhibiting means for inhibiting assertion from the direction register to a gate that activates a data output path when the direction register is closed.