JPH03283181A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce a consumption current and the area of a chip and to stabilize a substrate voltage by providing a control means controlling a substrate potential generation circuit in accordance with the change of an external address input signal. CONSTITUTION:The substrate voltage generation circuits 20, 21-2n waveform- shape internal address signals a0, a1-an in invertors INV1 and INV2 and they are inputted to a voltage doubler generation circuit VV. The voltage doubler generation circuit VV is activated once by a change that the internal signals a0, a1-an return from a low level to a high level or from the high level to the low level. Then, capacity adjusted to a substrate current which flows at two changes (from the high level to the low level, and from the low level to the high level) of the internal address signals is given. Thus, a circuit scale and the consumption current can be reduced and the substrate voltage can be stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device incorporating a substrate voltage generation circuit.

[Conventional technology]

FIG. 4 is a block diagram showing a substrate voltage generation circuit used in a conventional semiconductor memory device, FIG. 5 is a circuit diagram showing a dynamic random access memory which is a conventional example of a semiconductor memory device, and FIG. FIG. 3 is a diagram showing the amount of current flowing into a substrate in a conventional example.

In a semiconductor memory device (particularly a dynamic random access memory DRAM) in which the substrate voltage is set to a voltage other than GND or Vcc, an ionization current is generated during circuit operation due to the characteristics of the MOS transistor, and a portion of it flows to the substrate 30.
It appears that the substrate voltage is rising. In order to prevent such substrate voltage fluctuations and ensure stable operation of the circuit, DRAM
In general, substrate voltage generation circuits 41 and 42 are provided on the chip (FIG. 4). This substrate voltage generation circuit has a substrate voltage generation circuit 41 with a relatively small ion absorption capacity in order to cope with the leakage current (several μA to several tens of μA) during standby caused by the PN junction, and a substrate voltage generation circuit 41 that has a relatively small ion absorption capacity due to the large current consumption during active operation. Ionized substrate current (several hundred μA
The boat fishing is comprised of a substrate voltage generating circuit 42 corresponding to the degree of Ionization current is normally generated in proportion to ICC (power consumption current).

The parts that depend on external addresses will be explained below with reference to FIGS. 5 and 6.

External address signal A. , A1. ~． Due to changes in Ao,
The internal address generation circuit operates and generates the internal address signal aO+.
aI+~, ao, and the partial decoder 61 and column decoder 62 change. Accordingly, current flows into the substrate. Also, the data of the memory cell array 63 selected by the column decoder 62 is l10967
After being amplified by the data amplifier 64, the data is output to the output buffer 6.
5, but the operation of each circuit also causes substrate current to flow. On the other hand, during writing as well, current flows into the substrate due to the operation of the input buffer 68 and the like. Of the circuits that flow these currents into the board,
Non-address dependent circuits include output buffers and human input buffers, which depend on the values of input and output data.

The current flowing into the substrate of a circuit activated by a signal dependent on an external address, such as the data amplifier 64, depends on both the external address and output data.

In addition, as circuits that do not depend on external address signals and human output data, the word line drive circuit 71 and the sense amplifier 72
There is something like that.

[Problem to be solved by the invention]

In the conventional semiconductor memory device described above, the current capacity of the substrate voltage generation circuit 42 for active use must be sufficient for the maximum value of the current flowing into the substrate during active operation. On the other hand, as the capacity of current semiconductor memory devices increases, the circuits related to address signals occupy a larger proportion of the overall circuitry, and there are operating modes in which internal signals also change according to changes in external addresses. (Static column operation, etc.) has also been incorporated.

Therefore, the value of the current flowing into the board changes greatly depending on whether the external address changes in a short period or when it does not change, but the board voltage generation circuit must be designed to have the ability to handle the maximum value. In this case, there are disadvantages in that the circuit becomes larger and the current consumption in the substrate potential generation circuit also increases.

[Means to solve the problem]

The semiconductor memory device of the present invention has control means for controlling a built-in substrate potential generation circuit according to changes in an external address input signal.

[For production]

The control means controls the substrate voltage generation circuit so that only the required amount of current flows into the substrate according to changes in the external address input signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor memory device of the present invention.

°The internal address generation circuit 10 generates an external address signal Ao.
, A + , ~, An are input, and the internal address signal a. , al, to, ao are output. Internal address signal a
. , al, -, an are respectively the substrate voltage generation circuits 20,
21. ~． It is supplied to internal circuits such as 2n. Each substrate voltage generation circuit 20, 21° to 2n receives an internal address signal a.
Inverter INV inputting O+alg~an
, an inverter INV2 connected in series with the inverter INV, and a voltage doubler generation circuit vv.

The voltage doubler generating circuit VV is diode-connected, and the substrate 30
Transistors Q+ and Q2 inserted in series between
, the connection point of transistors Ql and Q2, and the inverter IN
It consists of a capacitor C connected to the output terminal of V2.

Next, the operation of this embodiment will be explained.

Substrate voltage generation circuits 20, 21. . . . , 2n are internal address signals a. ,al,~,an as inverter INV+,
The waveform is shaped by INV2 and input to the voltage doubler generation circuit VV. The voltage doubler generating circuit VV receives internal signals ao, a, .
, an is activated once when changing from low level to high level or from high level back to low level. It is provided with the ability to match the substrate current that flows due to two changes in the internal address signal (from high level to low level and from low level to high level). This embodiment is particularly effective for stabilizing the substrate voltage when the internal address has a characteristic that a larger substrate current flows when changing from a high level to a low level or from a low level to a high level. In that case, it is necessary to increase or decrease the number of inverter stages and match the polarity of the inverter output applied to the capacitor C.

FIG. 2 is a circuit diagram showing a substrate voltage generation circuit used in a second embodiment of the present invention, and FIG. 3 is a waveform diagram showing the operation of the circuit of FIG. 2.

Internal address signal a. is delay circuit DL and inverter IN
The signal is inverted and delayed by V, and the exclusive OR circuit EX outputs the delayed signal. and the internal address signal an.

The output C1 outputs a one-shot signal waveform every time the internal address signal an changes, and the voltage doubler generating circuit 2n receives the internal address signal a. It is activated every time there is a change in , and can compensate for the current flowing into the substrate, which has the advantage of further stabilizing the substrate voltage.

〔Effect of the invention〕

As explained above, the present invention has the effect of reducing current consumption and chip area and stabilizing the voltage compared to the base voltage by providing a substrate voltage generation circuit activated by an internal address signal synchronized with an external address. .

Further, it is not necessary to provide a substrate voltage generation circuit that is activated by all internal address signals, and it is sufficient to provide the substrate voltage generation circuit according to the present invention only for addresses where a large amount of current flows into the substrate due to a change in the external address. It is clear that the effects can be obtained. For example, the activation signal a of the data amplifier 64 shown in FIG.
If the current flowing into the substrate when the voltage changes is particularly large, a sufficient effect can be obtained by simply providing a substrate voltage generation circuit activated by the activation signal a1.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor memory device of the present invention, FIG. 2 is a circuit diagram showing a substrate voltage generation circuit used in a second embodiment of the present invention, and FIG. Figure 2 is a waveform diagram showing the operation of the circuit, Figure 4 is a block diagram showing a substrate voltage generation circuit used in a conventional semiconductor memory device, and Figure 5 is a dynamic random access memory that is a conventional example of a semiconductor memory device. The circuit diagram, FIG. 6, is a diagram showing the amount of current flowing into the substrate in the conventional example of FIG. 4. 10... Internal address generation circuit, 20.21. ~2n...Substrate voltage generation circuit, 30...
・Board, INV+, INV2, INV... Inva ';'
, C... Capacitor, Ql, Q2... Transistor, DL... Delay circuit, EX... Exclusive OR circuit.

Claims (1)

[Scope of Claims] 1. A semiconductor memory device incorporating a substrate potential generation circuit, characterized by comprising: control means for controlling the substrate potential generation circuit according to changes in an external address input signal.