JPS60187996A - Access control system - Google Patents

Abstract

PURPOSE:To access easily a dynamic RAM (DRAM) having no output registers with an optional independent timing clock, by holding and repeating access requests due to the independent clock which does not accord with the clock of the DRAM. CONSTITUTION:When the single clock mode indication due to the independent clock is set from a maintenance control part 6 to a register 8 for the purpose of accessing a DRAM2 from a service processor 5, a clock control part 7 stops clock supply to each control part. The control part 7 supplies the clock to a bus control part 3 at the timing synchronized with a non-control clock for refresh, and set contents of the register 8 are repeated, and a bus use permission signal is supplied from the control part 3 to the processor 5. Consequently, the DRAM having no output registers is accessed easily in accordance with the independent clock due to the service processor or the like without paying attention to the refresh clock or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a dynamic random access memory (DRA).
M) relates to data processing/systems using 10,000 access systems, particularly in DRAMKs without read data registers.

(b) Background of the technology In recent years, with the development of semiconductor technology and especially integration technology, a large number of circuit elements have been mounted in one package.
For example, microprocessors (11PU) and large-capacity storage devices based on LSI (LSI) have been realized at low cost, and have become widely used in many fields including data processing systems. On the other hand, devices using these devices are increasingly expected to have higher speeds and lower costs. Normal data processing f! 1! The main data record 1- in the 7-stem is cost-effective as a means.
RAM is used, but the function described in 1.1 in DRAM is to determine the magnitude of the charge accumulated in the capacitor in one transistor j16 memory cell at the logic level "tM□."

, it is necessary to perform a refresh operation to read and write the same data again before this charge is lost, and unless there is a special interruption, it is internationally standardized to perform a refresh at 2m510 to 70℃. ing. Therefore, the DRAM is always refreshed according to the continuous non-control clock (NCLK), and the normal line clock is used as a reference clock in accessing the DRAM. Further, in order to facilitate read access to the DRAM, the output data registers are separated, and the setting/resetting of the registers is also performed in accordance with NCLK.

(C) Prior art and problems In recent years, in order to increase the speed of data processing, the output data register in the above-mentioned DRAM is omitted, the one clock required for the input/output operation of the register is shortened, and the read data is stored in the DRAM. A method has come to be used in which data is read from registers built into other control units that are directly accessed via a data bus. This means that the register for storing read data in the control section on the read side is also operated in dependence on NCLK in the storage means. Although this method is unlikely to cause any additional problems during normal system operation, the control functions that control the other independent clocks connected via the data bus automatically control the data read from the storage means. The data bus &
C cannot be connected and operated. For example, the DRA
A test device or a maintenance processor (SV
There is a problem in that it is not easy to perform operations such as Pi connection and access via a data bus using a single clock or the like at an arbitrary timing.

(d) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned problems by using a DRAM.
As before, only the memory section using the continuous uncontrolled clock (
NCLK), and the control section on the read side uses the NCLK.
The system is configured to operate according to another control clock with a timing that guarantees memory access, and when access to the storage means is made with independent timing such as a single clock signal, the occurrence of the access is temporarily held, and access to the storage means is guaranteed. The present invention attempts to provide an access control method for a DRAM that does not have an output data register that handles asynchronous access by controlling the held access requests to be executed in synchronization with the subtooth 1 clock with the shortest waiting time. (e) Structure of the Invention This object is to provide a storage means using a dynamic random access memory without an output data register, and a plurality of control means having a function of directly accessing the storage means connected by a data bus. In the data processing system, the clock control means detects an access request from each control means to the storage means, and notifies the storage means of the timing when the storage means can be accessed according to the clock of the storage means. Single by arbitrary timing from other additional control means with no independent clock!
l! Alternatively, it is equipped with an access relay means that holds access requests from a plurality of separate pukus, and when an access using a different clock occurs from the access control means, the clock control means executes the access request each time the access relay means is set. This can be achieved by providing an access control method characterized in that a control clock is sent to both of the additional control means at the shortest possible timing, and the accesses by the additional control means using different clocks are relayed.

(f+ Embodiment of the invention Hereinafter, an embodiment of the invention will be described with reference to the drawings.

FIG. 1 is a configuration example diagram of a data processing device to which an access control method according to an embodiment of the present invention is applied, and FIG.
FIG. 3 shows a time chart for clock synchronous access executed during stem operation, and FIG. 3 shows a time chart for asynchronous access executed from independent synchronous system means.
INΔ1@(Co.

2 is a storage unit (MEM) consisting of a DRAM without a buffer register; 3 is a bus control unit (BC) that controls the common bus; and 4 is an interface control unit 10c that controls the interface with other devices. ), 51ri"j - Hisp o Seno? (SVP), 6id Maintenance control unit (SIC) that manages maintenance control under control from SVP5, 7 is a clock control unit (CLC), and 8 is asynchronous to MEM2 from USIC6. A register that holds access information (
RQR).

The procedure for accessing MEM2 via the CCI chip or l0C4 output common bus synchronized with the normal clock is as shown in Figure 2.
Explain the access case.

CC1 first sends a common bus use request signal (R
EQ)e Issue. REQv9-digit BC3U REQ from the other system E1 section is given priority control, and as soon as the other decoration section is no longer in use and the common bus becomes usable, a use permission signal (ACK) is responded to the CCI.

Upon receiving the ACK, the CCI sends a memory read request signal (MEMRD> and its address (AD)) onto the bus.IV (9M2 turns on the memory read start signal (GORD) when MEMRD is detected.

Immediately after GORD is turned on, a signal (RDCY) indicating a memory read cycle is turned on, memory reading is started, and the read data is sent to Ccl via the entire bus. After that, the timing signal (END) that can guarantee vagina data is C.
The read operation in MEM2 by access from the sending CCI to CI and BC3 is completed. When the BC receives the END, it turns off the ACK' and waits for the next REQ.

The CCI takes in the data on the bus into an internal register at the END timing. Note that the clock start OK signal (C8TOK) in FIG.
The difference is that it is output and controlled at the same timing as ND. The above is ME using CLK in conventional system operation.
This is common to the access operation of M2. Next, the procedure for access from a different independent clock system, for example, in the single clock mode from 5VP5, will be explained with reference to FIG.

Single clock mode instruction from 5VP5 to MEM 2
When set to RQR8 from 5IC6 for access to, CLC7 stops the CLK supplied to each control section 11. Thereafter, each time a 1-clock output instruction is set from 5VP5 to RQR8, the CLK'el clock is sent and reset to RQR8. That is, although not shown in the drawings, the non-control clock (NCLK) is continuously applied to the MEM2 from the clock signal generating means as before.
Memory operations synchronized with NCLK are ready for execution. Therefore, when CLK is sent from CLC7 at a timing synchronized with the NCLK, from then on, REQeBC3 is sent from 5vP5 via 5IC6, similar to the time chart in FIG.
ACK is received by SVP as soon as the bus becomes available.
5, and after receiving the ACK, 5VP5 sends M on the bus.
Sends ERRD and AD. MEM2 at this time
is activated by C3TOK', which is turned on at a timing when access operation can be guaranteed in response to asynchronous access such as SVP5. In FIG. 3, it is turned on at a timing when read data can be guaranteed for a read operation. In addition, C3TOK is N
Controlled by CLK. Therefore, 5VP5 is not in memory access mode as shown in the leftmost value cut in Figure 3.
CLK transmission by CLC7 is executed unconditionally for CLKGO, but after MEMRD by 5VP5 is turned on, it is controlled by NCLK.
Since C3TOK is turned on for only one cycle in each cycle, CLC7 waits until the next timing when C3TOK turns on every time CLKC is set in RQR8.
11161 and resets CLKC of RQR8. In this way, the procedure is executed according to the CLK sent from CLC7, and END is sent to guarantee the data for GORD, RDCY, and rescue hfL, so at the timing of CLK when END is output, similar to CCI in Fig. 2. 5VP5 can be taken into the read data gold register. By doing the above, the CLC7 selects and sends the timing that can guarantee the access for the access by the independent clock, and the access to MEM2 can be executed, so everything except MEM2 operates according to the CLK of the CLC7, and the With the timing-based clock, access of the MEM2 to the single clock of the SVP 5 can be easily realized, and testing and maintenance can be made more efficient. Note that since the MEM section operates with NCLK, it is not possible to directly check the operation with a single clock signal, but as mentioned above, the CLK is always sent out with the timing C3TOK, which guarantees memory access, turned on. Since the operation limited to the same conditions is repeated, it is possible to easily confirm the MEM2 access control timing.

(g) Effects of the Invention As has been clearly demonstrated, according to the present invention, the uncontrolled clock applied to the storage means when accessing from the common bus to the storage means 19 constituted by a DRAM without an output data register. This is useful because it provides an access control system that easily realizes access to the storage means even with a clock based on any other timing from another control means having an independent timing, without having to be familiar with the above.

[Brief explanation of the drawing]

FIG. 1 shows a configuration side of a data processing apparatus 1 to which an access control system according to an embodiment of the present invention is applied, FIG. 2 shows a time chart for clock synchronous access, and FIG. 3 shows a time chart for asynchronous access. In the figure, 1 is the main control unit (CC), 2 is the memorized sound [1 (
MEM), 3P′i bus Kozuki 9η) sweat 1 evening (o(゛),
4 is the interface system (11 parts (IOC), 5171 service processor f (SVP), 6 is the maintenance side fil n
(S I C), 7 is a clock fli control unit (CLC)
and 8 Hashi/Resta (RQR). Kaya 1 Chicha 2 Cause

Claims (1)

[Claims] In a data processing system, each i A clock control means that detects an access request from the control means to the means mentioned above and notifies the timing of access to the storage means according to the clock of the storage means, and another additional control means that uses an independent clock t that does not follow the clock. It is equipped with an access relay means that holds all the access requests by one or more different clocks according to the above 1+ meaning timing, and when an access to another clock occurs from the additional tlfll fal1 means, the clock control/J first stage is an access relay means. An access control method characterized by relaying the access by another clock of the means in the previous section at the shortest executable timing every time an access request is set.