JPS60182729A - 半導体パッケージ組立工程でのバリ除去兼外装処理方法 - Google Patents

半導体パッケージ組立工程でのバリ除去兼外装処理方法

Info

Publication number
JPS60182729A
JPS60182729A JP59039450A JP3945084A JPS60182729A JP S60182729 A JPS60182729 A JP S60182729A JP 59039450 A JP59039450 A JP 59039450A JP 3945084 A JP3945084 A JP 3945084A JP S60182729 A JPS60182729 A JP S60182729A
Authority
JP
Japan
Prior art keywords
exterior
molding
lead frame
lead
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59039450A
Other languages
English (en)
Japanese (ja)
Other versions
JPH021368B2 (enExample
Inventor
Tetsuya Hojo
徹也 北城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP59039450A priority Critical patent/JPS60182729A/ja
Publication of JPS60182729A publication Critical patent/JPS60182729A/ja
Publication of JPH021368B2 publication Critical patent/JPH021368B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Processing And Handling Of Plastics And Other Materials For Molding In General (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP59039450A 1984-02-29 1984-02-29 半導体パッケージ組立工程でのバリ除去兼外装処理方法 Granted JPS60182729A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59039450A JPS60182729A (ja) 1984-02-29 1984-02-29 半導体パッケージ組立工程でのバリ除去兼外装処理方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59039450A JPS60182729A (ja) 1984-02-29 1984-02-29 半導体パッケージ組立工程でのバリ除去兼外装処理方法

Publications (2)

Publication Number Publication Date
JPS60182729A true JPS60182729A (ja) 1985-09-18
JPH021368B2 JPH021368B2 (enExample) 1990-01-11

Family

ID=12553364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59039450A Granted JPS60182729A (ja) 1984-02-29 1984-02-29 半導体パッケージ組立工程でのバリ除去兼外装処理方法

Country Status (1)

Country Link
JP (1) JPS60182729A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862586A (en) * 1985-02-28 1989-09-05 Michio Osada Lead frame for enclosing semiconductor chips with resin
US5589402A (en) * 1993-11-23 1996-12-31 Motorola, Inc. Process for manufacturing a package for mating with a bare semiconductor die
JP2013026550A (ja) * 2011-07-25 2013-02-04 Apic Yamada Corp 半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862586A (en) * 1985-02-28 1989-09-05 Michio Osada Lead frame for enclosing semiconductor chips with resin
US5589402A (en) * 1993-11-23 1996-12-31 Motorola, Inc. Process for manufacturing a package for mating with a bare semiconductor die
JP2013026550A (ja) * 2011-07-25 2013-02-04 Apic Yamada Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JPH021368B2 (enExample) 1990-01-11

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