JPS60182729A - Sheathing treatment functioning as deburring in combination in assembly process for semiconductor package - Google Patents

Sheathing treatment functioning as deburring in combination in assembly process for semiconductor package

Info

Publication number
JPS60182729A
JPS60182729A JP59039450A JP3945084A JPS60182729A JP S60182729 A JPS60182729 A JP S60182729A JP 59039450 A JP59039450 A JP 59039450A JP 3945084 A JP3945084 A JP 3945084A JP S60182729 A JPS60182729 A JP S60182729A
Authority
JP
Japan
Prior art keywords
exterior
molding
lead frame
lead
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59039450A
Other languages
Japanese (ja)
Other versions
JPH021368B2 (en
Inventor
Tetsuya Hojo
徹也 北城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP59039450A priority Critical patent/JPS60182729A/en
Publication of JPS60182729A publication Critical patent/JPS60182729A/en
Publication of JPH021368B2 publication Critical patent/JPH021368B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Processing And Handling Of Plastics And Other Materials For Molding In General (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To execute deburring and sheathing treatment at a time by a method wherein a semiconductor chip is bonded with a lead frame, a film material for laminating is stuck to a molding unnecessary section, a resin is molded to a molding necessary section, and the film material for laminating is peeled off as a thin-film as a sheathing material is left as it is. CONSTITUTION:IC chips 4 are fixed to island sections 2 in a lead frame 1 with the island sections 2, inner leads 3 and outer leads 7 and 8, and films 5 and films 6 in Al, etc. on which thin-films 6 as sheathing materials are laminated are stuck on both surfaces of molding unnecessary sections in the frame 1 while being inward directed. The films 6 are fast stuck mutually among the leads 8 through pressing by a section with projecting sections corresponding to sections among the leads 8, and the lead frame is molded centering around the chips 4. The burrs 10 of a resin flowing out of a molding section 9 are removed together with the Al films 5, and deburring and sheathing treatment are executed at a stroke.

Description

【発明の詳細な説明】 本発明は半辱俸パッケージ組立工程でのパリ除去兼外装
処仰方法、詳しくはパリ除去と外装処理を、−挙にかつ
尚精度で自制的に行ない得る方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for removing deburrs and treating the exterior in a package assembly process, and more particularly, to a method that can perform the deburring and exterior treatment simultaneously, with precision, and self-control. It is.

近1植の半ノη体の1.“イ要の増大と高性11? f
とに伴ない、生得し入パッケージの製jft W 1析
も自制化と高精度化か図られ、その進歩は著しいもので
ある。その製造手段で現仕広く行われているものは、部
分メッキされたリードフレームに半専俸チップtホンテ
ィジグし、気密封止のためエポキシ横側等でモールディ
ジグし、その際にモールド不要部分に乗数・流入した樹
1指υIJちパリ(flash) を除去し、次いで半
11」・錫等によるメッキオたVJ′、浸設てリードに
外装処理し、その後マーキング等を施こすものである。
1. of semi-η body of near one plant. “Increase in energy and high quality 11?
Along with this, efforts have been made to control and improve the accuracy of the JFT W1 analysis of the original package, and the progress has been remarkable. The currently widely used manufacturing method is to mount a semi-specialized chip on a partially plated lead frame, mold it with epoxy on the side for airtight sealing, and then apply a multiplier to the part that does not need to be molded.・Remove the inflowing wood υIJ flash, then plate it with tin or the like and immerse it to give the lead an exterior treatment, and then apply markings, etc.

半、部体に、今後も一層の微細化・高性能化が図られる
とともに、品質の安定性と生産性・経済性の向上が要求
される。そこで上記の如く、その組立工程も高精度化と
自動化が図られ、ポンディング工程までは今後の要旨に
も応えられる技術水r$に達しつつある。しかし、モー
ルディングに伴なうパリの除去、およびその後の外装処
−18!に闇しては、未だ不充分な技術水準にあり、こ
れか半導体パッケージの組立工程を全自動の1ライン化
を進める上で重大な障壁となっている。
In the future, further miniaturization and higher performance will be sought for semi-finished parts and parts, as well as improvements in quality stability, productivity, and economic efficiency. Therefore, as mentioned above, the assembly process is becoming more precise and automated, and the process up to the bonding process is reaching a technological level that can meet future requirements. However, the removal of the Paris along with the molding and the subsequent exterior treatment-18! Unfortunately, the level of technology is still inadequate, and this is a serious barrier to moving the semiconductor package assembly process to a fully automated single line.

すなわち、パリ除去に関してはこれがリードフレームに
残留していると、次の外装処理を行なってもその部分が
絶縁状態となっているので、半導体はその性能を損ない
、不良品となってし捷う。
In other words, when it comes to removing paris, if this remains on the lead frame, that part will remain insulated even after the next exterior treatment, which will impair the performance of the semiconductor and result in it being rejected. .

それゆえ、フレームにパリの付着のないことか100%
の完全さで要求されている。そこでパリ除去手段として
現在まで種々なものが提案され、リードフレームを楽品
に浸漬させる化学的方法、’tに。
Therefore, it is 100% sure that there is no dust on the frame.
required with completeness. To date, various methods have been proposed to remove paris, including a chemical method in which the lead frame is immersed in the product.

解剥陰による電気的方法、高圧エアーまたeユ粒体を吹
付ける機械的(物理的)方法等がある。しかしこれらは
、パリ剥離が不充分であったり、リードフレームや半導
体チップを損傷させるおそれがある等の問題点を有して
いる。他面でパリの発生を無くすことも考えられたが、
リードフレームが簡単で定型的なものなら1能となって
も、複雑で多岐にわたる品種を扱かう場合には、パリの
発生を皆2+1?にすることは不可能である。そのため
現在は、リードフレームに付着したパリを除去するのに
、上記手段を幾つか併用したり、人手によりブラシで除
去している状況にある。
There are electrical methods using demolition shadows, and mechanical (physical) methods such as blowing high-pressure air or e-granules. However, these methods have problems such as insufficient separation of paris and the risk of damaging lead frames and semiconductor chips. On the other hand, it was possible to eliminate the outbreak of Paris, but
If the lead frame is simple and standard, it may be 1 function, but if you are dealing with a complex and wide variety of products, do you think it's 2+1? It is impossible to do so. Therefore, at present, in order to remove the particles attached to the lead frame, some of the above-mentioned methods are used in combination, or the particles are removed manually with a brush.

しかしこのような手段である限りは、萌・後の工程が尚
精度化・自制化していても、組立工程の全ラインを完全
自動化することはできない。しかも、今後−韻半等体が
微細化しリードフレームも細割化すると、モールド川樹
脂はより流動性のあるものが用いられる。従って、モー
ルディング時の樹脂の流れ込み・もれ・飛散が多くなり
一層パリが増えるから、パリ除去は今後一層大きな問題
となることが予想される。
However, as long as such means are used, it is not possible to completely automate the entire assembly process line, even if the initial and subsequent processes are more precise and self-controlled. Moreover, in the future, as semimetals become finer and lead frames become finer, mold resins with more fluidity will be used. Therefore, resin flows, leaks, and scatters more frequently during molding, which increases the amount of debris, so removing debris is expected to become an even bigger problem in the future.

他方性装置1に関しては、上記の如〈従来から半田(錫
Σメッキ法と半白(錫)浴浸漬法とが行われている。し
かしiff者td 助: <均一なメッキ膜が得ら、れ
るものの、メッキ処理Kt/−1半部体バックージ製造
とVi異質な特有の作業検鏡があるため、それを組立ラ
イン中に入れられず、外部のメッキ専業者に発注するか
、別棟のメッキ工場で行なう必要がある。これでは製品
lぎ理・品質管理も不完全になる。また後者の半田(錫
)浴浸漬法は、ライン化を可能とするため考えられたも
のであるが、1模厚の調節に難しい[釦があり、必要以
上に厚い被膜となりがちである。そのため被1模がリー
ド間にブリッジ状に付着したり、プリント基板へマクシ
ト時に装入用孔へリードが入らなくなる。さらに浴の高
熱雰囲気は、半キメ体回路に伺の影響も与えないとは断
言できず、回路損傷の原因にもなり得るものである。
Regarding the one-sided device 1, as described above, the solder (tin Σ plating method and the half-white (tin) bath immersion method have been conventionally used. However, if a uniform plating film is obtained, However, due to the plating process Kt/-1 half-body backge manufacturing and the special work speculum that is different from Vi, it cannot be put into the assembly line, so it must be ordered to an outside plating specialist or plated in a separate building. This must be done at the factory.This would result in incomplete product processing and quality control.Also, the latter solder (tin) bath immersion method was designed to enable production lines, but 1. Difficult to adjust the thickness of the pattern [There is a button, so the film tends to be thicker than necessary.As a result, the pattern may stick to the bridge between the leads, or the leads may not enter the charging hole when machining the printed circuit board. Furthermore, it cannot be guaranteed that the high-temperature atmosphere of the bath will not have a negative effect on the semi-solid circuit, and may even cause damage to the circuit.

上記の如く、半導体パッケージ組立工程においてパリ除
去と外装処理工程は、他の工程よりも技術的に未熟であ
り、またこれらが半導体パッケージ組立工程全体の高精
度化と、全ラインの完全自動化を妨げている2大要因で
ある。
As mentioned above, in the semiconductor package assembly process, the parity removal and exterior treatment processes are technically less mature than other processes, and these also hinder the high precision of the entire semiconductor package assembly process and the complete automation of the entire line. There are two major factors contributing to this.

本発明は半導体パッケージ組立工程でのパリ除去と外装
処理に関し、従来手段が有する上記問題点を解決しよう
とするものである。1111ちその目的とするところは
、第1に、モールティング時に生ずるパリのリードへの
付着やリード間への流込みをなくシ、パリの除去を確実
に行えるようにすることである。第2には、次工程の半
田(錫)によるリードへの外装処理を、均一なYJい被
膜がjヒ成できるとともに、それを半導体パッケージの
組立工程内で行えるようにすることである。第3には、
上記2つの工程(i−筒精度で完全自動化を図りながら
、できるだけシンプルな手段で行えるようにすることで
ある。そしてその結果として、半導体パッケージ製造の
全組立工程を、高精度で完全口切の1ラインとし、品質
の安定性と生産性(歩留り)・経lΔ性のII−II 
J二を図ることにある。
The present invention is directed to solving the above-mentioned problems of conventional means regarding parity removal and exterior treatment in the semiconductor package assembly process. 1111. The purpose of this is, first, to eliminate the attachment of paris to the leads or to flow between the leads, which occurs during molding, and to ensure the removal of paris. Second, it is possible to form a uniform YJ coating in the next process of coating the leads with solder (tin), and to perform this process during the assembly process of the semiconductor package. Thirdly,
The goal is to make the above two processes (i-tube precision and complete automation) as simple as possible.As a result, the entire assembly process of semiconductor package manufacturing can be performed with high precision and complete cut-off. 1 line, quality stability, productivity (yield), and lΔ characteristics II-II
The aim is to achieve J2.

以下に本発明を説明するが、本発明の要部である工程を
実施例で概説すると第1図のようになる。
The present invention will be described below, and the steps which are the main parts of the present invention are summarized in Examples as shown in FIG.

即ち、リードフレームに半導体チップをボンティングし
た後、該リードフレームのモールド不要Lq所に、片面
に外装材の薄膜を形成したラミネート川膜材を、その湧
暎で接するようにフレームの両面から貼付する。次に、
そのリードフレームの各リード間を両側から加圧して、
モールド必要箇所に樹脂でモールディングする。その後
、外装材薄膜をフレームに残したままで、ラミネート用
膜材を剥離する。続いてリフローラ、外装材’is膜の
濡れ性・光沢性を増して、各アククーリードKtm<て
均一な外装材被膜を形成させる。後はマーキングやカッ
ティング等の処理を施せばよい。
That is, after bonding a semiconductor chip to a lead frame, a laminated membrane material with a thin film of an exterior material formed on one side is attached to the Lq location of the lead frame where molding is not required, from both sides of the frame so that the thin film of the exterior material is in contact with the lead frame. do. next,
Pressure is applied between each lead of the lead frame from both sides,
Molding with resin in the required areas. Thereafter, the laminate film material is peeled off while leaving the exterior material thin film on the frame. Subsequently, a reroller is used to increase the wettability and gloss of the exterior material's film, and form a uniform exterior material coating using each Accooled Ktm. All that is left to do is to perform processing such as marking and cutting.

」1記の如く本発明は、パリ除去工程と外装処理工程と
を密接に関連させ、併せて一挙に行なうものである。そ
の実施例を図tl+j K基いて説明する。
1, in the present invention, the paris removal process and the exterior treatment process are closely related and are carried out all at once. An example thereof will be explained based on FIG. tl+jK.

[+1はリードフレームで、第3図の如く、中火にアイ
ランド部(2)を有し、その筒部に多数のインナーリー
ド(3)をイ]する。そのアイランド部(2)に、回路
を形成された半導休チップとしてのICチップ(4)を
ポンディング、即ちチップボンディングとワイヤポンデ
ィングしである。上記工程は現在広く行われている手段
により行なえばよい。
[+1 is a lead frame, as shown in Fig. 3, which has an island part (2) for medium heat, and a large number of inner leads (3) in its cylindrical part]. An IC chip (4) as a semiconducting chip on which a circuit is formed is bonded to the island portion (2), that is, chip bonding and wire bonding are performed. The above steps may be performed by means that are currently widely used.

(5)はラミネート用膜材で、第2図の如く裏囲に外装
材の′%II膜(6)を形成しである。ラミネート用膜
材(6)には、例えばアルミニウム箔の如き金属箔、あ
るいfd 1lit =性プラスチックフィルムを用い
るが、後で膜材剥till峙に薄膜(6)がフレームi
t)側に密着して、この+m材(5)側から剥れるもの
を採用する。外装材としては半田や錫を用いるが、その
縛膜(6)の形成手段は、例えば半田メッキ法や半田ク
ラッド法によってもよいか、ペースト状の半田をローラ
式のコークで塗布すれば、装置がシンプルで#膜もい、
1ノ<均一に形成できる。この場合に、フレーム(1)
か銅製ならば外装材の付着性・濡れ性も充分であること
は(#+i :忍l斉である。しかし近時多く用いられ
るようになった合金製のフレーム、例えばFe−N1合
金(4・210イ)に対しては+J[’性・諦れ性に不
充分さが認められるので、フレーム(1)の外装処理の
必要置所に、その合金に逸するフラックス剤でgfJ処
理を施しておけばよい。なおラミネート用膜材(6)は
、予じめ所要寸法に切断しであるものでもよいが、ライ
ンの自助化のためにはラミネート後に切断することにし
て、コイル状にしたものを利用することが望しい。
(5) is a film material for lamination, and as shown in FIG. 2, a % II film (6) of an exterior material is formed on the back side. For example, a metal foil such as aluminum foil or a fd 1lit plastic film is used as the laminating film material (6).
Use a material that adheres closely to the t) side and can be peeled off from the +m material (5) side. Solder or tin is used as the exterior material, but the method for forming the binding film (6) may be, for example, a solder plating method or a solder cladding method, or if paste-like solder is applied with a roller type caulk, the device can be easily formed. is simple and has #membrane,
1 can be formed uniformly. In this case, frame (1)
However, if the frame is made of copper, the adhesion and wettability of the exterior material is sufficient (#+i).・For 210a), +J['] was found to be insufficient in terms of strength and wearability, so gfJ treatment was applied to the necessary areas of frame (1) for exterior treatment using a fluxing agent that is compatible with the alloy. The laminating membrane material (6) may be cut into the required dimensions in advance, but in order to make the line self-supporting, it was decided to cut it after lamination and make it into a coil shape. It is desirable to use things.

そして第4図の如く、リードフレーム+11のモールド
不要部所に、両面からラミネート用膜材(5)を外装材
薄膜(6)が接するように貼付する。その後、各リード
i¥J(8+に対応する凸部をもつ型材にて、第5図・
第6図で示すようにフレーム+1)の両面から加圧し、
各アクタ−リード間(8)で外装材′tID tlQ 
+61同士を密着させる。これにより、谷アクターリー
ド(7)はラミネート用1模材(5)と内向の外装材勤
1換(6)とで密着状に囲続されるとともに、各リード
向(8)もその1挨材(5)と汽91模(6)とで否閉
される。この状1息で次に半導休チップ(4)を中心に
モールティングすると、その除にモールド部(9)から
流れl:l’、17’fiり乗数した樹脂即ち71月1
01は、リード(7)付着したりリード1MJt8+に
流れ込まず、第7図・第8図の如く全て両面のラミネー
ト用1換材(5)表向にイ・」石することになる。
Then, as shown in FIG. 4, the laminating film material (5) is attached to the parts of the lead frame +11 where molding is not required from both sides so that the thin film of the exterior material (6) comes into contact with the parts. After that, each lead i¥J (see Fig. 5.
As shown in Figure 6, pressurize from both sides of the frame +1),
Exterior material 'tID tlQ between each actor and lead (8)
+61s are in close contact with each other. As a result, the valley actor lead (7) is closely surrounded by the first laminate material (5) and the inward facing exterior material shift (6), and each lead direction (8) is It is closed by the material (5) and the steam 91 model (6). In this state, when molding is performed centering around the semi-conducting chip (4), the resin that is multiplied by l:l', 17'fi, flows from the mold part (9), i.e., 71/1.
01 does not adhere to the lead (7) or flow into the lead 1MJt8+, but instead splatters on the surface of the laminating substitute material (5) on both sides, as shown in FIGS. 7 and 8.

このモールディング時において、その作業の雰囲気は通
常170°Cの加熱を2分間続けるものであるため、ラ
ミネート用膜材(5)内側の外装材薄膜(6)は溶融状
癌になる。そしてその外装材は、ラミネート用膜材(5
)よりも付層しやすい材質であるフレーム(1)のリー
ド(7)面に転写(転移)される。この際に補助的にリ
フロ一工程を曲せば、耐融・転写が一層容易となる。
During this molding, the working atmosphere is usually one in which heating is continued at 170° C. for 2 minutes, so the thin sheathing material film (6) inside the laminating film material (5) becomes a molten cancer. The exterior material is a laminating film material (5
) is transferred (transferred) onto the lead (7) surface of the frame (1), which is a material that is easier to layer. At this time, if the reflow step is assisted, the melting resistance and transfer will be made easier.

次に第9図の如く、ラミネート用1戻材(5)をリード
フレームil+から剥離することにより、全てその表O
nに付着しているパリ叫はその膜材(5)と共に佃実に
除去されることになる。またその剥1lj1..時に、
外装材薄膜(6)は、目「1記の如く既にフレーム(1
)のリード(7)に転写されているので11匁材(6)
に伺いて剥れず、第10図で示すように各リード(7)
の局面に付着したをまである。続いてそのリードフレー
ム(1)をリフローすることにより、各リード(7)の
周m1に付aされている外装4;A薄膜(6)は、第1
1図の如く濡れ性を増して各リード(7)の同曲に薄く
均一化された被膜(6a)を形成するとともに、光沢性
も増すことになる。その後は洗浄・カッティング・ベン
ディング・バッキング等の工程を経ればよい。
Next, as shown in Fig. 9, by peeling the laminating material 1 (5) from the lead frame il+,
The particles adhering to n are effectively removed together with the film material (5). Also, the peeling 1lj1. .. Sometimes,
The exterior material thin film (6) has already been applied to the frame (1) as shown in item 1.
) is transferred to the reed (7), so it is 11 momme material (6)
As shown in Figure 10, each lead (7)
There is even a surface that is attached to the surface. Subsequently, by reflowing the lead frame (1), the outer sheath 4; A thin film (6) attached to the circumference m1 of each lead (7) is
As shown in Figure 1, the wettability is increased and a thin and uniform coating (6a) is formed on the same track of each reed (7), and the gloss is also increased. After that, processes such as cleaning, cutting, bending, and backing may be performed.

なお上記実施例はICパッケージ組立工程でのパリ除去
と外装処理について述べたが、その龍広く半41体パッ
ケージの組立工程でも利用できる。
Although the above embodiments have been described in terms of pars removal and exterior treatment in the IC package assembly process, they can also be widely used in the assembly process of half-41 packages.

才だパッケージの形状に関係なく、テユアル・イン・ラ
インパッケージやフラットパッケージ、その他のものも
処理できる。上記実施例では、フレーム+11両曲の)
漢材)5)を密着させるのに卆相で加圧したか、それに
限らす例えば尚匝エアーでl+bJ側から加圧したり、
捷だ肋材(5)間の突気を吸引して密着させる等の手段
によってもよい。
Regardless of the shape of the package, we can process both individual-in-line packages, flat packages, and more. In the above example, frame + 11 songs)
For example, pressurize from the l+bJ side with Shosan air, or
It is also possible to use means such as suctioning air between the twisted ribs (5) to bring them into close contact.

以」二で明かな如く本発明の特徴は、ラミネート用膜材
の表面に外装月のlυ/膜を形成してお・き、それをボ
ンティング後のリードフレームでモールド不要簡n1に
両面から貼イ」シ、ラミネート用肋材r両側から加圧し
てリード間で密着状とする。そしてボンディング時に生
ずるパリを、リードにイ\Jかす全てう三ネート用膜材
」二に付和させるとともに、その際の熱で外装材を溶融
状として各リード間に転写させる。次いでラミネート用
膜材の剥1帷により、パリを該膜材と共に全て除去する
か、外装祠薄膜は各リードに行右させておき、リードフ
レームを次Vこリフローすることで外装材の17/ff
れ性を増形成されるものである。
As is clear from the following, the feature of the present invention is to form an exterior lυ/film on the surface of the laminating film material, and then apply it to the lead frame after bonding from both sides without the need for molding. Apply pressure from both sides of the laminating ribs to create a tight seal between the leads. Then, the dust produced during bonding is attached to the leads and the coating material is melted by the heat and transferred between the leads. Next, remove all the particles together with the laminating film material by stripping the film material for lamination, or leave the exterior abrasion thin film on each lead and reflow the lead frame to remove 17% of the exterior material. ff
This increases the resistance to formation.

したかって本発明によれば、第1に、モールディング時
に生ずるパリは、リード面への行右やリード間に2互れ
込むことがなく、ラミネート用膜材の剥離により全ての
パリは(#f実に述去できる。第2に、ラミネート用膜
材に予じめ形成しである外装材を、モールティジグ時と
りフローによりリード間に転写し幅れ性を増すので、均
一で薄い鼓膜か1し1戊できるとともに、その工程は半
導体パッケージ組立工程において特に異質なものでない
から、そのライン中に組入rすることかてきる。第3に
、パリ除去と外装処理を関連させて、並行的に行なうも
のであるから、高精度で完全自動化を図りながらもシン
プルな手段にできる。しかもその結果、半導体パッケー
ジ製造の全組立工程を、高精度で完全自動の1ラインに
できて、品質の安定性と生N(性・歩留りおよび経済性
の向上を図ることができる、等の優れた効果を奏する。
Therefore, according to the present invention, firstly, the flashes generated during molding do not cross over to the lead surface or between the leads, and all the flashes are removed by peeling off the laminating film material (#f). Second, the sheathing material, which is pre-formed on the membrane material for lamination, is transferred between the leads using the flow of the molding jig, increasing the width of the tympanic membrane, resulting in a uniform and thin eardrum. In addition, since the process is not particularly different from the semiconductor package assembly process, it can be incorporated into the line.Thirdly, parity removal and exterior processing are related and performed in parallel. As a result, it is possible to achieve high precision and complete automation with a simple method.Moreover, as a result, the entire assembly process of semiconductor package manufacturing can be completed on one highly precise and fully automated line, resulting in stable quality and It has excellent effects such as improving raw N (productivity, yield, and economic efficiency).

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の実施例を示すもので、第1図はその工程図
、第2図は釉)模付ラミネート膜材の一部の拡大斜視図
、第3図はボンティング後の平面図、第4図は腺祠旧付
後の一部拡大縦断側聞図、第5図は1模材を加圧後の平
lin図、第6図は第5図の八−A部分の一部拡大縦断
側面図、第7図はモールディング後の斜視図、第8図は
第7図のB−B部分の一部拡大縦断側面図、第9図は)
模桐剥篩゛1時の斜視図、第10図は膜材剥削、後の一
部拡大縦断側聞図i図、第11図はりフロー後の一部拡
大縦断側面図である。 図山[符り(1)・・・リードフレーム、(5)・・・
ラミネート用膜材、(6)・・・外装材の薄膜、(6a
)・・・鼓膜、(7)・・・リード、(8)・・・リー
ドrL f+01−・・パリ出願人 北域徹也
The figures show an example of the present invention, in which Fig. 1 is a process diagram, Fig. 2 is an enlarged perspective view of a part of the glazed (glazed) laminate film material, and Fig. 3 is a plan view after bonding. Figure 4 is a partially enlarged longitudinal cross-sectional view after the gland shrine was installed, Figure 5 is a flat line view after pressing one piece of material, and Figure 6 is a partially enlarged view of section 8-A in Figure 5. (Figure 7 is a perspective view after molding, Figure 8 is a partially enlarged vertical side view of the section B-B in Figure 7, and Figure 9 is a vertical side view.)
Fig. 10 is a partially enlarged longitudinal sectional side view after the film material is removed; Fig. 11 is a partially enlarged longitudinal sectional side view after the beam is flowed. Figure mountain [mark (1)...lead frame, (5)...
Membrane material for lamination, (6)...Thin film of exterior material, (6a
)...Eardrum, (7)...Reed, (8)...Reed rL f+01-...Paris applicant Tetsuya Kitaen

Claims (1)

【特許請求の範囲】[Claims] ■生得体チップをホンティングしたリードフレームに、
横月旨でモールディングし、そのi?六に生じる/くり
を除去してリードに外装処理ケ施こす工程をもつ半ン(
メ体パッケージ組立工桿において、リードフレームfi
lのモールド不要薗所の両1n]に、予しめ外装材の薄
U*+6+を片面に形成したラミネート用jr、;、!
材(5)を、その薄膜(6)面で貼付し、その両1川の
1像日(5)を各リート′(7)を&H続する如くリー
ド間(8)で密着させ、次にモールティングしその際の
パリ(1o)を全て膜材(5)上に付着させるとともに
、外装(シ薄膜+61を各リード(7) 1.fTlに
帖写し、次いでン専膜(6)全フレーム(1)に残して
パリ(+0+の付右した映桐(5)全判1離し、その後
に外装材の濡れ性を増すリフロー処理をして、谷リード
(7)周面に均一て鰭い外装材被111バ6a)を形成
させるようにした、半棒体パッケージ組立工程でのパリ
除去兼外装処理方法。
■The lead frame has an innate chip,
Molding with Yokozukiji, that i? This is a semi-finished product with a process of removing the hollows that occur on the reed and applying exterior treatment to the reed.
In the metal package assembly process, the lead frame fi
Laminating jr with a thin U*+6+ exterior material formed on one side in advance on both 1n of the mold-free slots of l, ;,!
Paste the material (5) with its thin film (6) side, and place the image (5) of both of the two parts in close contact between the leads (8) so that each lead' (7) is connected by &H. At the same time as molding, attach all of the Paris (1o) on the membrane material (5), copy the exterior (thin film +61) onto each lead (7) 1.fTl, and then apply the special film (6) to the entire frame. Leave it on (1) and release the Eigiri (5) with +0+ on it, then apply reflow treatment to increase the wettability of the exterior material, and apply a uniform fin exterior on the circumference of the valley reed (7). A method for removing pars and treating the exterior in a half-bar package assembly process in which a material cover 111 bar 6a) is formed.
JP59039450A 1984-02-29 1984-02-29 Sheathing treatment functioning as deburring in combination in assembly process for semiconductor package Granted JPS60182729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59039450A JPS60182729A (en) 1984-02-29 1984-02-29 Sheathing treatment functioning as deburring in combination in assembly process for semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59039450A JPS60182729A (en) 1984-02-29 1984-02-29 Sheathing treatment functioning as deburring in combination in assembly process for semiconductor package

Publications (2)

Publication Number Publication Date
JPS60182729A true JPS60182729A (en) 1985-09-18
JPH021368B2 JPH021368B2 (en) 1990-01-11

Family

ID=12553364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59039450A Granted JPS60182729A (en) 1984-02-29 1984-02-29 Sheathing treatment functioning as deburring in combination in assembly process for semiconductor package

Country Status (1)

Country Link
JP (1) JPS60182729A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862586A (en) * 1985-02-28 1989-09-05 Michio Osada Lead frame for enclosing semiconductor chips with resin
US5589402A (en) * 1993-11-23 1996-12-31 Motorola, Inc. Process for manufacturing a package for mating with a bare semiconductor die
JP2013026550A (en) * 2011-07-25 2013-02-04 Apic Yamada Corp Method of manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862586A (en) * 1985-02-28 1989-09-05 Michio Osada Lead frame for enclosing semiconductor chips with resin
US5589402A (en) * 1993-11-23 1996-12-31 Motorola, Inc. Process for manufacturing a package for mating with a bare semiconductor die
JP2013026550A (en) * 2011-07-25 2013-02-04 Apic Yamada Corp Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
JPH021368B2 (en) 1990-01-11

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