JP4701842B2 - Manufacturing method of semiconductor device substrate - Google Patents

Description

  The present invention relates to a semiconductor device mounting substrate used in a BGA (Ball Grid Array) type semiconductor device, a manufacturing method thereof, and a semiconductor device substrate forming base material suitable for the same. More specifically, the present invention relates to a semiconductor device BGA package, and more particularly to a semiconductor mounting substrate and a method for manufacturing the same for improving reliability and economy.

  In recent years, in the electronics industry, the development of multifunction devices with high reliability has been rapidly progressing, and with the advent of high functionality and high density elements, high reliability and multifunction have been achieved. There is an increasing demand for lightweight, thin and small devices. Accordingly, the development of new element mounting technology is becoming increasingly important, and development is progressing as an important issue especially in miniaturization and diversification of semiconductor packages.

Accordingly, a BGA package for a CSP (chip size package) semiconductor using a multi-layer build-up structure has been proposed in order to improve the mounting density. However, along with the demand for higher density by further multilayering, it is inevitable that the cost of the semiconductor BGA package itself is increased. For high-density mounting, vias are installed (fan-in) directly under the semiconductor chip, and the wiring circuit pattern of the BGA package for semiconductors is made finer, the space between copper wirings is narrowed, and the via diameter is reduced. A study of narrower pitch and single layer is underway.
In addition, a resin film or a metal plate is used as a support for the single-layer substrate as described above, and when this support is processed into a roll shape and a semiconductor package is manufactured with multiple faces by a roll-to-roll method, Cost can be reduced.

Furthermore, the difference between the miniaturization pace of the semiconductor chip itself and the miniaturization pace of the semiconductor BGA package tends to increase year by year, and the high density and low cost of the semiconductor BGA package corresponding to the fine pitch can be dealt with. It is strongly desired. Further, as a material for the core material of the semiconductor device substrate, a tape BGA package using a flexible polyimide having a thickness of about 50 μm as the core material is put on the market. For example, Patent Document 1 is cited as a typical single-layer semiconductor BGA substrate having a fan-in structure. Such a single-layer semiconductor BGA substrate can be multi-faceted in a matrix by a reel-to-reel method using an insulating film or the like, and can be mass-produced at low cost.

  By the way, generally, laser processing is used for forming a via of a semiconductor BGA substrate. However, in laser processing, since vias are individually formed, it is not possible to form vias all over the surface, which is an obstacle to cost / process reduction and workability improvement. Photo via formation methods, die punching methods, and the like are known as methods for forming vias at once, but photosensitive insulating films used for photo via formation methods are expensive, and die punching cannot make the via diameter fine. There was a problem. For these reasons, with the conventional method, it is difficult to collectively form vias on a large-area substrate, thereby reducing processes and costs.

In addition, when solder is filled in a via formed by a conventional method such as laser processing, a photo via method, or a die punching method, air or moisture mixed in the via may expand due to heat and generate a crack. Further, when the via is formed by the conventional method, the stress due to the expansion and contraction of the base material in the heat cycle test is concentrated on the via opening, which causes a problem that the via opening is cracked. For this reason, in the conventional via forming method, there is a problem of reliability of the semiconductor device substrate, and it is necessary to cope with this problem.
Japanese Patent No. 3352804

  The present invention has been made to solve the above-mentioned problems, and the problem is to simplify the manufacturing process and to mass-produce highly reliable BGA package products for semiconductors in a multifaceted manner at a low price. Is to provide a good product.

In order to solve the above problems, the present inventors have conducted the following studies.
First, a substrate composed of three layers of wiring layer / insulating support layer / metal layer so that the adhesion strength between the wiring layer and the insulating support layer is equal to or higher than the adhesion strength between the metal layer and the insulating support layer. Formed.
Next, a photoresist was applied to both surfaces of the metal layer and the wiring layer of the substrate. The substrate was subjected to double-sided exposure, and a wiring pattern was formed on the wiring layer, and a pattern identical to the via pattern was formed on the metal layer.
Subsequently, using the metal layer as a mask for forming a via pattern, the insulating support layer was chemically etched to form a via. Thereafter, when the metal layer used as a mask was peeled off, the metal layer was cleanly separated from the insulating support layer, and the entire metal layer could be recovered.
Also, if the adhesion strength between the wiring layer and the insulating support layer is less than the adhesion strength between the metal layer and the insulating support layer, the amount of undercut when the insulating support is chemically etched increases, and the insulating support It has been found that the effect that the opening formed in the film has a preferable tapered shape can be obtained at the same time. Then, wet blasting is performed from the metal layer side, and when the insulating support layer forming the via opening and the portion exposed by the via of the wiring layer are roughened, the solder adhesion can be improved. did it. The present inventors have been able to manufacture a semiconductor device substrate through the steps as described above.

The present invention has been made based on such knowledge, and the invention according to claim 1 includes at least a wiring layer provided on one side of a substrate,
In a method of manufacturing a semiconductor device substrate having an insulating support layer and a via pattern that penetrates the insulating support layer and reaches the wiring layer, at least,
(A) providing a wiring layer on one side of the insulating support layer;
(B) providing a metal layer on the opposite surface of the insulating support layer to the wiring layer;
(C) laminating a photoresist on the wiring layer and the metal layer;
(D) exposing and developing a photoresist on the wiring layer and the metal layer to form a photoresist wiring pattern on the wiring layer, and forming a photoresist via pattern on the metal layer;
(E) etching the wiring layer and the metal layer using the photoresist wiring pattern and the photoresist via pattern as an etching mask, and peeling the photoresist wiring pattern and the photoresist via pattern;
(F) attaching a protective sheet on the wiring layer and forming a forward tapered via in the insulating support layer using the metal layer as a mask;
(G) mechanically peeling the metal layer;
A method for manufacturing a semiconductor device substrate.
Further, in addition to the above configuration, (f) a step of attaching a protective sheet on the wiring layer and forming a tapered via in the insulating support layer using the metal layer as a mask is a wet etching method or a wet etching method. A method of manufacturing a semiconductor device substrate, characterized in that one of the blasting methods or a combination of both methods is used.
Further, in addition to the above-described configuration, (d) a photoresist on the wiring layer and the metal layer is exposed and developed to form a photoresist wiring pattern on the wiring layer, and a photoresist via on the metal layer. The process for forming a pattern is a method for manufacturing a semiconductor device substrate, characterized in that double-sided batch exposure is performed.

In the invention according to claim 4 , the step (a) of providing a wiring layer on one side surface of the insulating support layer includes:
(A1) a step of depositing a wiring seed material on one side of the insulating support layer by sputtering to provide a wiring seed layer;
(A2) laminating a wiring material on the wiring seed layer by plating,
(B) providing a metal layer on the opposite surface of the insulating support layer to the wiring layer,
(B1) providing a metal layer seed layer by sputtering a metal layer seed material on one side of the insulating support layer;
(B2) laminating a metal layer material on the metal layer seed layer by plating,
The wiring seed material and the metal layer seed material are different metal materials, and
Adhesion strength between the wiring layer and the insulating support layer, a semiconductor device substrate according to claim 1, wherein greater than the adhesion strength between the insulating support layer and the metal layer It is a manufacturing method.

The invention according to claim 5 is characterized in that the difference between the adhesion strength between the wiring layer and the insulating support layer and the adhesion strength between the metal layer and the insulating support layer is 5% or more. A method for manufacturing a semiconductor device substrate according to claim 1 .

In the invention according to claim 6 , the adhesion strength between the wiring layer and the insulating support layer is
6. The method of manufacturing a semiconductor device substrate according to claim 1 , wherein the method is in a range of 0.4 kgf / cm to 0.7 kgf / cm.

The invention of claim 7 is a method for manufacturing a semiconductor device substrate according to any one of claims 1 to 6, wherein the insulating support layer is a polyimide.

The invention according to claim 8 is the method for manufacturing a semiconductor device substrate according to any one of claims 1 to 7 , wherein copper is used as a plating material for the wiring layer or the metal layer.

A tenth aspect of the present invention is a semiconductor device substrate manufactured using the manufacturing method according to any of the second to ninth aspects.

According to the present invention, since the via opening provided in the insulating support of the semiconductor device substrate having a fine wiring pattern can be collectively formed in a large area, the number of processes is reduced, and the semiconductor device The manufacturing cost of the substrate could be reduced.
In addition, according to the present invention, the exposure process of the photoresist that forms the wiring layer of the semiconductor device substrate and the via pattern of the metal layer formed on the opposite surface performs batch exposure. The effect that does not occur was obtained. For this reason, the alignment accuracy of the wiring pattern and the via pattern of the semiconductor device substrate has been dramatically improved as compared with the conventional case, and the defect rate has been reduced.
In addition, according to the present invention, the metal layer used as a mask can be peeled and recovered when forming the via opening of the insulating support layer of the semiconductor device substrate. For this reason, since the collected metal layer can be recycled and reused, an environment-friendly and inexpensive semiconductor device substrate could be manufactured.
Furthermore, according to the present invention, since the via opening of the semiconductor device substrate has a tapered shape, the fluidity of the filled solder is improved, and the water vapor and bubbles of the flux are easily removed. In addition, solder with a via opening filled in a tapered shape is more resistant to concentration of thermal stress in the via opening compared to solder formed in a straight via that is not tapered, so the solder ball connection is stable, The reliability of the semiconductor device substrate could be improved.
According to the present invention, after the via formation of the semiconductor device substrate, wet blasting is performed, so that the exposed surface of the wiring layer corresponding to the via bottom and the surface roughness of the insulating support layer forming the via opening are reduced. Rz = 0.5 μm to 1.0 μm. For this reason, by improving the wettability in the solder reflow process and improving the adhesion due to the anchor effect, the connection of the solder balls is stabilized, and the reliability of the semiconductor device substrate can be improved.

An example of the manufacturing process of the substrate for forming a semiconductor device substrate, the semiconductor device substrate, the BGA package for semiconductor, and the BGA package product for semiconductor of the present invention will be described below with reference to FIGS.
Hereinafter, the insulating support layer 10 of the present invention is used as a starting point and will be described in detail using examples. The insulating support layer of the present invention may be a resin having a glass transition point of 150 ° C. or higher, and is not limited to this example. For example, a polyimide film can be used.

(A) A polyimide film 10 is used as an insulating support layer serving as a base, and metal materials having different adhesion properties are formed on the front and back surfaces of this surface by a sputtering deposition method. As an example of such a configuration, Ni—Cr alloy 21 is sputter-deposited on the front surface and copper alloy 31 is sputter-deposited on the back surface. (Figure 2)
(B) Copper plating is performed on the Ni—Cr alloy 21 and the copper alloy 31 sputter-deposited on the polyimide film 10 to form copper plating layers 22 and 32 of about 10 μm, respectively, and copper foil layers 20 and 30 are formed. . (FIG. 3) The copper foil layer 20 corresponds to the “wiring layer” of the present invention, and the copper foil layer 30 corresponds to the “metal layer” of the present invention. In this way, the substrate for forming a semiconductor device substrate of the present invention (hereinafter referred to as a three-layer structure substrate) is manufactured.
(C) Photoresist 40 is coated to a thickness of about 10 μm on both surfaces of the three-layer structure substrate of copper foil layer 20 / insulating support layer 10 / copper foil layer 30. (Fig. 4)
(D) Both surfaces of the three-layer structure base material coated with the photoresist 40 on both sides are exposed. At this time, a photomask having a wiring pattern is used on the surface on which the Ni—Cr alloy 20 is sputter-deposited, and a photomask having a via pattern is used on the surface on which the copper alloy 30 is sputter-deposited. Then, double-sided exposure is performed on the work. Thereafter, alkali development is performed to form a wiring pattern in the photoresist on the copper foil 20 side, and a via pattern is formed in the photoresist on the copper foil 30 side. (Fig. 5)
At this time, it is preferable that the photomask is aligned at the same time for batch exposure. Then, since it is possible to perform alignment once that has conventionally been performed twice for each side, the number of steps can be reduced, and the number of alignments is halved. This is because the effect of doubling the alignment accuracy of the pattern can be obtained.
(E) Using the wiring pattern and via pattern of the photoresist as an etching mask, the double-sided copper foil layers 20 and 30 of the three-layer structure base material were subjected to pattern etching, and the photoresist was stripped with a 5% NaOH solution. A copper foil wiring pattern 20 and a via pattern were formed on the polyimide film surface. (Fig. 6)
(F) A protective sheet 50 was pasted on the copper foil layer 20. Furthermore, using the via pattern of the copper foil layer 30 as an etching mask for the polyimide film, vias were formed on the insulating support layer of the polyimide film 10 exposed from the via pattern by the via processing method of the present invention. (Fig. 7)
(G) The copper foil layer 30 was mechanically peeled and recovered. Further, the protective sheet 50 provided on the copper foil layer 20 was also mechanically peeled. (FIG. 8).
(H) The insulating film 60 was coated so that the bonding portion with the semiconductor chip was exposed in the copper foil layer 20 (wiring layer) region. (Fig. 9)
(I) Nickel / gold plating was applied to the joint portion with the exposed semiconductor chip. (Fig. 10)
The semiconductor BGA package of the present invention is produced by the steps (a) to (i).

  If the above-mentioned semiconductor BGA package is arranged in multiple faces in a matrix, the semiconductor BGA package product of the present invention can be produced. With such an arrangement, the semiconductor package can be mass-produced at a lower cost. As an example of the multi-sided arrangement, FIG. 1 shows an example in which 7 × 7 BGA packages for semiconductor are arranged in a matrix. In the conventional tape BGA package product, the tape BGA package is arranged in series on a polyimide tape having a width of about 50 mm, and sprocket regions used for alignment and transport are provided on both sides of the tape BGA package. In semiconductor BGA package products, it is possible to reduce the material cost of useless sprocket regions.

  The insulating support layer serving as a base is a support for a package substrate for a semiconductor device, and a film-like engineering plastic (hereinafter referred to as engineering plastic) having a glass transition point of 150 ° C. or higher can be used. Generally, polyimide is used for such engineering plastics. Other examples of engineering plastic materials that can be used in the present invention include polyamide, polyacetal, polycarbonate, polyphenylene ether, polybutylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyetherimide, polyarylate, polysulfone, and polyethersulfone. , Polyether ether ketone, liquid crystal polymer and the like. Among them, polyimide, liquid crystal polymer and the like can be mentioned as suitable for the alkali etching step. In recent years, it has been desired that the semiconductor device substrate further support high frequency, and it is preferable to use an insulating resin material having a dielectric constant of 3.0 or less for the BGA package for semiconductors. Also, if the high temperature condition continues, such as during solder reflow, the moisture absorbed in the insulator material sandwiched between the metal layers will evaporate and cracks will occur. An insulating material with a low is preferred.

  The thickness of the insulating support layer is preferably about 30 μm to 100 μm from the viewpoint of strength during conveyance in the roll-to-roll process, and more preferably 50 μm from the viewpoint of cost. If the thickness is less than 30 μm, the flexibility is very good, but the problem of cutting during transportation and the problem that the pattern of the wiring copper foil shows through and the flatness cannot be maintained occur, which is not good for the base. Is appropriate. On the other hand, when the plate thickness is thicker than 100 μm, it is rigid and the workability is lowered in the manufacturing process, and the material cost is increased.

  In the present invention, for example, as shown in FIG. 1, in order to supply an inexpensive semiconductor BGA package, semiconductor BGA package products are arranged in a multi-sided arrangement in a matrix form on a wide roll having a width of 500 mm or more. With such an arrangement, it is possible to mass-produce semiconductor packages, and it is possible to supply cheaper BGA package products for semiconductors.

  Furthermore, a metal layer and a wiring layer are formed on both surfaces of the insulating support layer to obtain a three-layer structure base material for a semiconductor device substrate of the present invention. As a method of forming the metal layer and the wiring layer on both surfaces of the insulating support layer, seed sputter films are formed on both surfaces of the insulating support layer. Further, electroplating is performed on the seed sputtered film using a conductive metal such as copper to form a metal layer on one side and a wiring layer on the opposite side of the metal layer. The wiring layer appropriately performs electrical connection between the semiconductor element mounted on the semiconductor element mounting board and the motherboard. The metal layer is used as a mask for forming a via pattern on the insulating support. The metal layer and the wiring layer can be formed on both surfaces by 5 to 12 μm. When the film thickness is thicker than 12 μm for forming a fine pattern by the substruct method, it is inappropriate, and the copper foil by metallizing increases the cost. For the metal layer formed by electrolytic plating up, a conductive metal such as copper can be used.

In the present invention, the adhesion strength between the wiring layer and the insulating support is increased with respect to the adhesion strength between the metal layer and the insulating support. This is because only the metal layer used as a mask can be peeled cleanly in the (g) peeling step. Furthermore, it is more preferable that the adhesion strength between the wiring layer and the insulating support is increased by 5% or more with respect to the adhesion strength between the metal layer and the insulating support.
The adhesion strength between the insulating support layer and the metal layer is preferably in the range of 0.4 to 0.7 kgf / cm. When the adhesion strength between the insulating support layer and the metal layer is less than 0.4 kgf / cm, the metal layer (copper foil layer 30) floats as shown in FIG. 11 during the (f) via processing step. There is a risk of peeling off (an example in which no floating or peeling occurs is shown in FIG. 12). On the other hand, if it is larger than 0.7 kgf / cm, there is a possibility that the metal layer is cut or the semiconductor device substrate is deformed when the metal layer is peeled off.
Furthermore, when the adhesion strength between the insulating support layer and the metal layer is in the range of 0.4 to 0.5 kgf / cm, in the (e) via formation step, the via shape is more ideally tapered. be able to.

  The seed sputtered film is preferably formed with a thickness of about 2000 mm. In order to make a difference in the adhesion strength between the metal layer and the wiring layer with respect to the insulating support layer, for example, a Cr-Ni alloy or the like is used as a seed sputtering target on the wiring layer surface side with a high adhesion strength, and the metal with a low adhesion strength. On the layer surface side, a Cu alloy can be used as a target for seed sputtering.

  In addition to the three-layer structure base material using polyimide as an insulating support layer, a base material made by bonding non-thermoplastic polyimide and copper foil using thermoplastic polyimide as an adhesive by the casting method or laminating method is marketed. Has been. In the base material, thermoplastic polyimide is used as an adhesive. However, when the alkali etching rate of the thermoplastic polyimide is slower than the etching rate of the non-thermoplastic polyimide, the thermoplastic polyimide is completely alkali-etched while being non-thermoplastic. There is a problem that the amount of undercut of polyimide becomes large and the dimensional accuracy deteriorates. For this reason, when a three-layer structure substrate formed of such an adhesive is used in the present invention, it is necessary to select an adhesive whose etching rate is not too slow relative to the etching rate of the insulating support layer. is there.

  As the photoresist used for forming the via pattern of the metal layer and the wiring pattern of the wiring layer of the present invention, for example, when using a negative resist, an aqueous casein solution to which ammonium dichromate is added as a photosensitive assistant can be exemplified. It is not limited to.

  In the present invention, the photoresist formed on both surfaces of the three-layer structure substrate is simultaneously exposed to the wiring layer pattern and the metal layer via pattern. At this time, the wiring pattern mask and the via pattern mask are aligned at a time. The work is roll-to-roll and passed between aligned photomasks. For this reason, the alignment accuracy between the photomask of the wiring layer and the photomask of the via pattern of the metal layer is very important, but the alignment accuracy between the workpiece and the photomask is not so important. As described above, the alignment may be performed once with the photomask of the wiring layer and the photomask of the via pattern of the metal layer, and only the workpiece is movable. Therefore, improvement in accuracy can be expected. For this reason, the yield reduction due to the alignment failure is eliminated, and an inexpensive product can be supplied.

  In the present invention, vias are formed on the insulating support on the wide-roll three-layer structure substrate using the wet etching method or the wet blasting method using the metal layer on which the via pattern is formed as a mask. . According to this method, it is possible to form a large-area via at once with high accuracy, and thus the cost for forming a via opening can be reduced.

  A wet etching method is used to form a via in the insulating support layer. The wet etching method is a method of forming a via pattern by etching an insulating support layer with a hot alkaline solution. The wet etching method is superior in cost and process compared to the laser method because a via can be formed at a time for a large-area substrate at once. In addition, as the via diameter decreases, the problem of air bubbles falling into the via during solder filling has become a problem, and for this measure, the insulating support layer is made thinner or the wiring layer foil exposed in the via is removed. Although it was necessary to devise measures such as plating up, the former method of thinning the insulating support layer has a problem of insufficient mechanical strength, and the latter method of plating up the via bottom However, there was a problem that the cost was increased.

  However, when the via formation method of the present invention is performed using the three-layer structure substrate of the present invention, the via shape becomes a forward taper shape, so that bubbles are eliminated during filling with solder, and the conventional problem described above Could be solved. Further, the feature of this method is that the etching proceeds isotropically, so that the side etching proceeds directly under the mask in which the via pattern is formed (undercut). For this reason, the via diameter on the mask needs to be set smaller than the originally required via pattern dimension.

In addition, the layer structure of the insulating support is desirably a single material in order to make the progress of etching uniform. For example, specifically, the copper foil is metalized on the non-thermoplastic polyimide film without using thermoplastic polyimide as an adhesive between the insulating support layer made of non-thermoplastic polyimide and the copper foil layer. It is preferable not to make the insulating support layer a composite of thermoplastic polyimide and non-thermoplastic polyimide. Thermoplastic engineering plastics such as liquid crystal polymers can be used without any particular problem.

  The wet blasting method is a method of discharging a turbid liquid containing water-insoluble fine particles and grinding a hard engineering plastic material layer using a soft copper foil as a mask. Here, the water-insoluble fine particles are generally used for wet blasting such as silica, alumina and titania, and there is no problem as long as they are classified to 1 to 10 μm. If wet blasting is performed using fine particles of this particle size, the exposed surface of the wiring copper layer corresponding to the bottom of the via can be roughened in the range of Rz = 0.5 μm to 1.0 μm. Since the surface of the vias of the wiring copper foil and the insulating support layer is moderately roughened, the soldering material is improved in paintability and adhesion strength, and the connection reliability is improved.

In order to make the most of the advantages of wet etching and wet blasting,
First, after the wet etching method with a high processing speed, the removal of residues by the wet blasting method and the processed surface can be made into a satin finish to improve the connection reliability.

  The present invention provides an inexpensive semiconductor substrate by the above method. Hereinafter, specific examples will be described.

Example 1
(A) As an insulating support layer (10), a surface of a 50 μm-thick polyimide film (Kapton 200H, manufactured by Toray DuPont) is sputter-deposited (about 21 mm) using a Ni—Cr alloy as a target (21), and a Cu film is formed on the back Similarly, sputtering was performed (31) by using an alloy as a target. (Figure 2)
(B) Further, a sputtered film (21, 22) is used as a seed layer to form a film of about 8 μm by copper plating, and a three-layer structure of copper foil layer (20) / insulating support layer (10) / copper foil layer (30) A substrate was created. (Figure 3)
(C) After surface-treating the surface of the three-layer structure substrate, an aqueous casein solution (40) to which ammonium dichromate is added as a photosensitizer is used as a negative photoresist on both surfaces of the three-layer structure substrate. Applied. (Fig. 4)
(D) After drying the photoresist, using a photomask in which a desired pattern is arranged in a multifaceted manner in a matrix, wiring is made on a copper foil surface (20) using a Ni—Cr alloy of a three-layer structure base material as a seed layer. A pattern photomask is attached to a copper foil surface (30) with a Cu alloy seed layer, and a via pattern photomask is brought into close contact with each other while aligning the photomasks, and ultraviolet rays are simultaneously irradiated from both sides. The photoresist was exposed and photocured in a region other than the predetermined pattern portion. Subsequently, hot water spray development was performed to remove the uncured photoresist, and then the remaining photoresist was hardened. (Fig. 5)
(E) Further, ferric chloride solution is sprayed on both surfaces of the three-layer structure substrate, the copper plate and the wiring copper foil layer are etched using the photoresist as a mask, and the wiring pattern and the via pattern are formed into the three-layer structure substrate. The copper foil was formed. The casein was peeled off by dipping in a sodium hydroxide solution. (Fig. 6)
(F) A protective film made of polypropylene (50) was attached to the copper foil layer surface of the wiring pattern, immersed in an 80 ° C. amine-based alkaline aqueous solution on the copper foil layer surface of the via pattern, and sprayed in the liquid. A via pattern was formed on an insulating support layer made of polyimide. (Fig. 7)
(G) After mechanically peeling off the protective film (50) on the copper foil layer surface of the wiring pattern, a solder resist (manufactured by Asahi Chemical Research Laboratories) was screen-printed so that the wire bonding pad portion was exposed, and at 150 ° C. for 1 hour Baking was performed to form a pattern in which the copper wiring portion of the wire bonding pad was exposed. (Not shown)
(H) After a plating-resistant protective film was applied to the via pattern copper foil layer, nickel / gold plating was applied to the exposed copper wiring portion of the wire bonding pad. After stripping of the plating-resistant protective film, the copper foil layer of the via pattern on the back surface was then mechanically peeled off. (Not shown)
(I) A semiconductor chip is mounted, the wire bonding pad portion plated on the wiring copper foil layer and the semiconductor chip are connected by wire bonding, molded with an epoxy-based sealing resin, and the via is filled with solder. BGA package product for semiconductor. When the cross section of this semiconductor device substrate was observed, there were no bubbles or gaps in the solder. Also in the heat cycle test, the rate of change in resistance between the solder material and the wire bonding pad was within 8%.

(Example 2)
In Example 2, instead of polyimide film, heat resistance is 150 ° C. or more, and polyethylene naphthalate (manufactured by Teijin DuPont) is used as an inexpensive material, and steps (a) to (e) are carried out. 1 was performed. Thereafter, the following steps were performed.
(F) A suspension in which alumina having a particle size of 10 μm or less is dispersed in water is wet blasted to the copper foil layer surface side of the via pattern with a spray pressure of 5 kgf / cm 2, and the via pattern is formed on the insulating support layer made of polyimide. Formed. (Fig. 8)
(G) After thoroughly washing with water and drying so that no alumina particles remain, solder resist (manufactured by Asahi Chemical Laboratories) is screen-printed so that the wire bonding pad portion is exposed, baked, and copper wiring of the wire bonding pad A pattern in which a portion was exposed was formed. (Fig. 9)
Further, steps (h) to (i) were performed in the same manner as in Example 1 to fabricate a semiconductor device substrate and a semiconductor BGA package product. When the cross section of the semiconductor device substrate was observed, there were no bubbles or gaps in the solder. Also in the heat cycle test, the rate of change in resistance between the solder material and the wire bonding pad was within 8%.

(Example 3)
In Example 3, steps (a) to (f) were performed in the same manner as in Example 1. Thereafter, the following steps were performed.
(G) After completion of the step (e), a suspension in which alumina having a particle size of 10 μm or less is further dispersed in water is wet-blasted to the copper foil layer surface side of the via pattern with a spray pressure of 5 kgf / cm 2, and from the via pattern The exposed copper foil and the surface of the insulating support layer in the via are roughened, and in this step, the residue of the insulating support layer remaining on the wiring copper foil in the via is completely removed. (Fig. 9)
Further, steps (g) to (i) of Example 1 were performed to manufacture a semiconductor device substrate and a semiconductor BGA package product. When this semiconductor device substrate was observed on the cross section of the semiconductor element, there were no bubbles or gaps in the solder. Also in the heat cycle test, the rate of change in resistance between the solder material and the wire bonding pad was within 8%.

(Comparative Example 1)
(A) Except that the insulating support layer (10) was formed by sputtering (21) on both sides of a polyimide film (Kapton 200H, manufactured by Toray DuPont) with a thickness of 50 μm using a Ni—Cr alloy as a target. An attempt was made to manufacture a semiconductor device substrate in the same process as in Example 1.
However, (h) In the step of peeling the copper foil layer on the via surface, the strip-shaped film was cut. Even when the peeling stress was applied evenly, the cut pits formed at the edges of the film were cut.

(Comparative Example 2)
In this comparative example, a via was formed by punching using a mold, and then a semiconductor BGA package product was created by a method of bonding a copper foil with an epoxy adhesive.
(A) A via pattern was formed by punching at a predetermined position of a polyimide film (Kapton 200H, manufactured by Toray DuPont) having a thickness of 50 μm as an insulating support. However, the width of 150 mm and the length of 300 mm are the limits due to the cost of the mold and the punching device, so that it cannot be arranged in a matrix.
(B) Furthermore, the polyimide film which formed the rolled copper foil and the via | veer was bonded together using the epoxy-type adhesive agent, and was hardened.
(C) A negative photoresist was applied on the rolled copper foil of the two-layer base material. (Fig. 4)
(D) After drying the photoresist, the vias of the insulating support layer and the photomask of the wiring pattern are brought into close contact with each other while being aligned, exposed by irradiating with ultraviolet rays, and exposed to the photoresist in a region other than the predetermined pattern portion. Photocuring was performed. Next, development was performed to remove the uncured photoresist, and then the remaining photoresist was hardened (FIG. 5).
(E) After applying an etching protective film on the insulating support layer side, ferric chloride solution was sprayed to etch the wiring copper foil layer to form a wiring pattern (FIG. 6). The photoresist was peeled off by dipping in a sodium hydroxide solution.
(F) Solder resist (made by Asahi Chemical Research Laboratories) is screen-printed so that the wire bonding pad portion is exposed, and then the etching protective film is mechanically peeled and baked to expose the copper wiring portion of the wire bonding pad. A pattern was formed. (Fig. 9)
(G) Furthermore, after applying a plating-resistant protective film to the via pattern copper foil layer, nickel / gold plating was applied to the exposed portion of the copper wiring of the wire bonding pad. The plating-resistant protective film was peeled off. (Fig. 10)
(H) A semiconductor chip is mounted, the wire bonding pad portion plated on the wiring copper foil layer and the semiconductor chip are connected by wire bonding, molded with an epoxy-based sealing resin, and the via is filled with solder. BGA package product for semiconductor. When a cross section of the semiconductor device substrate was observed, small bubbles and gaps were formed in the solder. Further, in the heat cycle test, some BGA package substrates were warped and the solder material was pulled out of the vias, resulting in an open defect. Also, some BGA package substrates were found to have cracked solder at the via openings. Since the via surface is flat and the opening is not tapered as described above, there arises a problem that the connection reliability of the solder is lowered.

Plan view of semiconductor BGA package product of the present invention Sectional view of the semiconductor device substrate of the present invention Sectional view of the semiconductor device substrate of the present invention Sectional view of the semiconductor device substrate of the present invention Sectional view of the semiconductor device substrate of the present invention Sectional view of the semiconductor device substrate of the present invention Sectional view of the semiconductor device substrate of the present invention Sectional view of the semiconductor device substrate of the present invention Sectional view of the semiconductor device substrate of the present invention Sectional view of the semiconductor device substrate of the present invention Via formation surface of the semiconductor device substrate that floats on the metal layer and peels off Via formation surface of a semiconductor device substrate that floats on the metal layer and does not peel off

Explanation of symbols

10 Insulating support layer 20 Copper foil layer (wiring layer)
21 Wiring seed layer 22 Wiring copper plating layer 30 Copper foil layer (metal layer)
31 Metal layer seed layer 32 Metal layer plating layer 40 Photoresist 50 Protective film 60 Insulating film

Claims (8)

At least a wiring layer provided on one side of the substrate;
In a method of manufacturing a semiconductor device substrate having an insulating support layer and a via pattern that penetrates the insulating support layer and reaches the wiring layer, at least,
(A) providing a wiring layer on one side of the insulating support layer;
(B) providing a metal layer on the opposite surface of the insulating support layer to the wiring layer;
(C) laminating a photoresist on the wiring layer and the metal layer;
(D) exposing and developing a photoresist on the wiring layer and the metal layer to form a photoresist wiring pattern on the wiring layer, and forming a photoresist via pattern on the metal layer;
(E) etching the wiring layer and the metal layer using the photoresist wiring pattern and the photoresist via pattern as an etching mask, and peeling the photoresist wiring pattern and the photoresist via pattern;
(F) attaching a protective sheet on the wiring layer and forming a forward tapered via in the insulating support layer using the metal layer as a mask;
(G) mechanically peeling the metal layer;
A method for manufacturing a semiconductor device substrate, comprising: (F) A step of attaching a protective sheet on the wiring layer and forming a tapered via in the insulating support layer using the metal layer as a mask is either a wet etching method or a wet blast method, or both methods The method of manufacturing a semiconductor device substrate according to claim 1 , wherein the semiconductor device substrate is used in combination. (D) exposing and developing a photoresist on the wiring layer and the metal layer to form a photoresist wiring pattern on the wiring layer and a photoresist via pattern on the metal layer; the semiconductor device manufacturing method of the substrate according to claim 1 or 2 characterized in that it is a batch exposure. (A) providing a wiring layer on one side of the insulating support layer;
(A1) a step of depositing a wiring seed material on one side of the insulating support layer by sputtering to provide a wiring seed layer;
(A2) laminating a wiring material on the wiring seed layer by plating,
(B) providing a metal layer on the opposite surface of the insulating support layer to the wiring layer,
(B1) providing a metal layer seed layer by sputtering a metal layer seed material on one side of the insulating support layer;
(B2) laminating a metal layer material on the metal layer seed layer by plating,
The wiring seed material and the metal layer seed material are different metal materials, and
Adhesion strength between the wiring layer and the insulating support layer, a semiconductor device substrate according to claim 1, wherein greater than the adhesion strength between the insulating support layer and the metal layer Production method. The difference in the adhesion strength of the wiring layer and the insulating support layer wherein the insulating support layer adhesion strength and the metal layer of semiconductor according to claim 1 to 4, characterized in that at least 5% Device substrate manufacturing method. Adhesion strength between the wiring layer and the insulating support layer is
6. The method of manufacturing a semiconductor device substrate according to claim 1 , wherein the method is in a range of 0.4 kgf / cm to 0.7 kgf / cm. The method of manufacturing a semiconductor device substrate according to any one of claims 1 to 6, wherein the insulating support layer is a polyimide. The method of manufacturing a semiconductor device substrate according to any one of claims 1 to 7, characterized by using a copper plating material of the wiring layer or a metal layer.