JPS60180129A - Manufacture of semiconductor package - Google Patents

Abstract

PURPOSE:To stabilize quality and make easier management by laminating a thin film to the unmolding area before the molding as the burr eliminating process and coating the lead-requiring area with pasted external material and reflowing it as the external treatment processing. CONSTITUTION:Thin films 5, 5 are attached from both sides to the unmolding area at the front and rear surfaces. The attached surface is coated with a bonding agent. As the bonding material, a thermo-bonding type polymer which does not remain on the frame at the time of exfoliation is used. Resin molding is carried out from both sides to the region where thin films 5, 5 are not attached. The burrs 7, 7 do not adhere to an outer lead 8, do not flow the areas 9 between leads and all adhere to thin film 5, 5. Thereafter, as the external processing, the resion from where thin films 5, 5 are exfoliated is coated with the pasted solder by the print method in order to form a solder layer 10. It is then reflown by the reflow furnace in view of improving extendability and wetness of solder. Thereby, a solder film 11 can be formed in the uniform thickness at the external circumference of each outer lead 8.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a method for manufacturing a semiconductor package, and more specifically, a method for manufacturing a semiconductor package in which the assembly process of the semiconductor package can be completed in one line with high accuracy.

In recent years, manufacturing technology for semiconductor packages, including IC packages, has progressed to an unparalleled degree as demand for semiconductors has increased and their performance has improved, and efforts have been made to achieve in-house production and high precision. An outline of the semiconductor package assembly process that is currently commonly performed is as follows. That is, a semiconductor chip is pumped onto a partially plated lead frame, and molded with an epoxy resin for hermetic sealing. At this time, the resin is deposited even on the parts where no molding is required.
ash) is removed, and then the lead portion is covered with solder (tin), and the lead portion is wrapped or first cut or vented, then packaged, and then marked and packaged.

As semiconductors continue to become smaller and more sophisticated, it will be necessary to improve quality stability, productivity, and economy. Therefore, the assembly process mentioned above has been improved in precision and automation to meet this demand, but this only applies to the systems for each process, and the entire assembly process is rationally integrated into one line. The spider hasn't reached me yet.

The main reason for this is that among the above processes, the molding process, the associated paris removal process, and the exterior treatment process in particular have significantly different work content and atmosphere as compared to the processes before and after the molding process, and This is because it faces many technical issues.

That is, in the molding process, the semiconductor chip is molded with resin in order to hermetically seal the semiconductor, but at this time, the resin scatters or flows toward the leads, and the resin also adheres to areas where molding is not required. be. If even a small amount of paris is attached, the semiconductor will be defective because it will remain insulated even if the lead portion is subsequently coated with solder (tin).

Therefore, it is required that the frame be 100% completely free of debris. Therefore, it was considered to eliminate the occurrence of paris, but apart from simple and routine lead frames, it is impossible to eliminate the occurrence of paris when dealing with a complex and wide variety of products. .

Therefore, various methods are currently being proposed for removing paris, including chemical means using chemicals, electrical means using electrolytic stripping, mechanical means using high-pressure air or granule spraying, and manual methods using brushes. There are means etc. However, all of these methods have problems such as incomplete removal, and at present, it is finally possible to remove Paris by using several of these methods in combination. Furthermore, these methods require personnel to remove and inspect the paris, so economics is also an issue. As the miniaturization of semiconductors progresses further in the future, the spacing between the leads of the frame will become narrower, making this process of deburring even more difficult. Therefore, unless these problems are solved first, it is impossible to integrate the entire semiconductor package assembly process into one line.

On the other hand, there are also the following problems regarding the exterior treatment process using solder (tin). That is, in this process, solder (tin) plating or solder immersion method is performed, and although the former method is electroplating and can form a thin film uniformly, defective products may be produced if the deburring is incomplete. . Moreover, plating work differs in work content and level from other assembly processes, requires a unique atmosphere for plating work, and is accompanied by pollution treatment equipment. For this reason, many companies outsource the exterior treatment process to external plating specialists, but this poses problems in product management and makes line integration impossible.

The latter immersion method is aimed at streamlining the semiconductor package assembly process. However, this complicates the control of the film thickness, and the film thickness becomes too thick, making it difficult to insert each lead into the pole during chip machining onto a printed circuit board. However, this method will become unusable in the future as semiconductors become smaller and the lead direction becomes narrower. Furthermore, the solder bath is in a high-temperature atmosphere that often damages semiconductor circuits, and dipping requires a dual-in-line package that is cut and bent, so dipping equipment is required. It becomes complicated. Furthermore, with a flat package, it is not possible to immerse only the leads; if the entire package is immersed, there is a risk that the circuit will be damaged by heat.

In the manufacture of semiconductor packages, final quality and performance inspections are always carried out in addition to inspections at each step, but the main reason for this is that the above-mentioned problems remain in the mold/paris removal process and the exterior treatment process. Therefore, the entire semiconductor package assembly process cannot be integrated into one line with high precision and completely automatically unless the problems in the packaging process are solved in addition to the problem of removing paris.

The present invention is directed to a method of manufacturing a semiconductor package, and is an object of the present invention to solve the above-mentioned drawbacks of conventional methods. In other words, the purpose is to achieve high precision and complete automation of each assembly process in the manufacturing method of semiconductor packages, as well as to achieve high precision and fully automatic single line throughout the entire assembly process. The goal is to improve quality stability, productivity, and positive results in response to semiconductors that will become even smaller and more sophisticated in the future. Specifically, firstly, the dust generated during the molding process can be completely removed using a simple method unlike conventional methods, and secondly, the exterior treatment process can be done using simple means regardless of the shape of the package and regardless of the circuit. A uniform thin film can be formed without causing damage, and it can be done in one line.
An object of the present invention is to provide a method for manufacturing a semiconductor package.

The invention will be explained below by means of illustrated embodiments.

(1) is a lead frame with an island part (2) in the center as shown in Figure 1, and a large number of inner leads (3) around the periphery.
), and the necessary parts are partially plated. An IC chip (4) as a semiconductor on which a circuit is formed is bonded to this lead frame (11), that is, chip bonding and wire bonding of electrodes and leads (3).The above steps are performed automatically with high precision by known means. Just do it.

Next, a lamination process, which is one of the essential parts of the present invention, begins.

That is, in the lead frame +11, a thin film +5) is applied from both sides to the front and back parts where molding is not required, as shown in Figures 4 and 5.
Attach (5) accurately. This thin film (5) (5)V
i Copper, aluminum foil, or a heat-resistant plastic film is preferable, and an adhesive is applied to the surface to be attached to the lead frame ill. The adhesive is
A thermopressure-resistant polymer is used that can withstand the atmosphere at 170° C. for 2 minutes during molding and does not remain on the frame (1) ilII when peeled off.

Next, a molding process begins, in which a predetermined portion of the lead frame +11 centered around the IC chip (4), that is, the remaining portion where the thin film t51+5+ was not pasted during the previous lamination process, is molded with resin from both sides. .

At this time, resin molded part +61 (side fat scatters or flows around 61, resulting in pa IJ (7) (7). However, molded part +6] As mentioned above, a thin film is applied from both sides of the frame (1) other than t6+. +5) As shown in Figures 6 and 7, if +5+ is pasted, Paris (71+7
+ does not attach to the actor lead (8), and does not attach to the actor lead (8)
9) and all adhere to the thin film +51 (5).

The next step is a thin film peeling step, in which the thin films (5) (5) are peeled off from the lead frame (f+) as shown in FIG. That is, by peeling off this thin film +5) +5+, the thin film (5) (
5) 71 7+ +71 attached to the thin film (51 [5)
With this, all data will be removed from frame (1).

As a result, the actor-lead (8) surface and the lead-to-lead (9) K
As shown in FIG. 9, a lead frame (1) in which no particulate f7+ +7+ is stacked is obtained. Further, by selecting the adhesive as described above, the adhesive does not accumulate on the frame tl), and the thin film +5+ +51 is easily peeled off.

According to the above-mentioned paris removal process, unlike the conventional process, there is no need for a complicated paris removal process after the molding process or an inspection process thereof, and a semiconductor package with stable quality without any adhesion of paris can be obtained.

In the above embodiment, the laminating process is carried out immediately before the molding process, but the invention is not limited thereto. For example, thin films (5) (5) may be applied from both sides in the same way when partially plating the lead frame fl+. good. In this case, a thin film (
5) (5) is the lead frame +1) actor lead (
8) is held from both sides, and in addition to the above effect, it is also possible to prevent lead bending and other deformations that may occur during partial plating or bonding processes.

The next step is an exterior treatment with solder (tin), but it is not impossible to adopt conventional means after the steps described above. However, in order to achieve even higher precision and complete automation,
The present invention takes the following measures. That is, after the molding process, the parts of the lead frame fl+ that require exterior treatment, in other words, the parts where the thin films (5) and (5) have been peeled off, are coated with paste-like solder as an exterior material by printing and soldered. A layer (lO) is formed and reflowed in a reflow oven to increase the spreadability and wettability of the solder and form each actor lead (
8) A solder film (11
) to form.

For this application, for example, a pattern may be formed in advance and then screen printed using a roller-like coater. If a cleaning process is performed before or after the exterior treatment process by applying this paste solder, the accuracy will be further improved.

Unlike conventional methods, the above-mentioned exterior treatment process does not require particularly foreign working conditions and does not require special pollution prevention equipment, so it can be easily incorporated into the IC package assembly process line in a small space. This means that a thin and uniform film thickness can be formed.

Also, since paste solder is applied, unlike the dipping method, I
Regardless of the shape of the C-package, exterior treatment can be easily applied to not only dual-in-line packages but also flat packages and pond-shaped packages. Furthermore, even if ICs become further miniaturized in the future, a uniform and thin solder film can be formed on the leads, and the chip's circuitry will not be adversely affected by heat.

After this exterior treatment process, a marking process, a cutting process, a pending process if necessary, etc.
The assembly process of the C package is completed.

It should be noted that although the above embodiment has been described in the case of an IC package, it goes without saying that the present invention can be used in a wide range of other semiconductor packages as a process for removing paris and for packaging.

As is clear from the above, according to the method for manufacturing a semiconductor package according to the present invention, firstly, a step of laminating a thin film onto a lead frame is provided before the molding step, and a peeling step is provided after the molding. Although it has an extremely simple structure that differs from conventional ones, the paris that occurs during molding is completely removed, and no paris remains on the lead frame. Furthermore, even if semiconductors become more miniaturized in the future, this method will always ensure that Paris can be removed.

Second, by changing the packaging process to the application of a paste-like packaging material, it can be easily inserted into the semiconductor package assembly process line in a small space, unlike conventional packaging, and it can be applied uniformly regardless of the shape of the package. A thin exterior material coating can be formed.

In addition, semiconductor circuits will not be damaged by heat, and semiconductor leads, which are becoming increasingly finer, can be packaged with a thin film thickness.

Therefore, by using the deburring process and the exterior treatment process of the present invention, the various problems associated with these conventional processes can be reliably solved. Moreover, based on this, all lines for the semiconductor bag assembly process can be integrated into a highly accurate and fully automated line within a semiconductor manufacturing factory. the result,
This has the extremely beneficial effect of stabilizing the quality of semiconductors, making management easier, and improving productivity and economic efficiency.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, in which Fig. 1 is a process diagram thereof, Fig. 2 is a process diagram of another embodiment, Fig. 3 is a plan view of an IC lead frame, and Fig. 4 is a thin film after bonding. 5 is a partially enlarged vertical sectional view taken along line A-A in FIG. 4, FIG. 6 is a perspective view after molding, and FIG. 7 is a B-B in FIG. 6. Partially enlarged vertical cross-sectional view along the line,
Fig. 8 is a perspective view when the thin film is peeled off, Fig. 9 is a partially enlarged vertical cross-sectional view after the thin film is removed, Fig. 1o is a partially enlarged longitudinal cross-sectional view after the exterior material is applied, and Fig. 11 is a cross-sectional view after the beam flow. FIG. 12 is a perspective view after bending. Drawing code (1)...Lead frame, (3)...Inner lead, (4)...Semiconductor chip, (5)...
・Thin film, (6)...Mold part, (7)...Paris,
(8)...Actor-lead, (9)...Between leads,
(lO)...Solder layer, (11)...Solder film applicant Tetsuya Kitagi♀ = Transfer procedure amendment l Display of case Relationship to 1980 Patent Application No. 36765 Case Patent applicant 4 , Agent 8, Contents of the Amendment As shown in the attached sheet, the following sentence should be added next to "Adopted" on page 8, line 15 of the specification box.

Claims (1)

[Claims] The method includes the steps of bonding a semiconductor chip to a partially plated lead frame, molding it with resin, removing any particles adhering to the frame, and then externally treating the actuator leads with solder. In a method for manufacturing a semiconductor package, as a process for removing paris, a thin film is laminated on both sides of a part of the frame where molding is not required at the latest immediately before the molding process, and after molding, the thin film is peeled off together with the paris attached thereto,
Furthermore, the method for manufacturing a semiconductor package is characterized in that, as an exterior treatment step, a paste-like exterior material is applied to the necessary portions of the leads and then reflowed. (2) The method for manufacturing a semiconductor package according to claim 1, wherein the thin film lamination in the process of removing paris is performed before the lead frame is partially plated. ■Claim 1, in which lamination of the thin film in the process of removing paris is performed immediately before molding.
A method for manufacturing a semiconductor package as described in . (2) The method for manufacturing a semiconductor package according to claim 1, wherein in the exterior treatment step, paste solder as an exterior material is applied to necessary portions of the leads by screen printing.