JPS60173847A - Deburring method in assembly process for semiconductor package - Google Patents
Deburring method in assembly process for semiconductor packageInfo
- Publication number
- JPS60173847A JPS60173847A JP2889884A JP2889884A JPS60173847A JP S60173847 A JPS60173847 A JP S60173847A JP 2889884 A JP2889884 A JP 2889884A JP 2889884 A JP2889884 A JP 2889884A JP S60173847 A JPS60173847 A JP S60173847A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- molding
- thin
- semiconductor package
- assembly process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 239000010409 thin film Substances 0.000 claims abstract description 23
- 238000000465 moulding Methods 0.000 claims abstract description 20
- 229920005989 resin Polymers 0.000 claims abstract description 4
- 239000011347 resin Substances 0.000 claims abstract description 4
- 238000003475 lamination Methods 0.000 claims description 3
- 239000002245 particle Substances 0.000 claims description 3
- 101150034459 Parpbp gene Proteins 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000010030 laminating Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000010291 electrical method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000008187 granular material Substances 0.000 description 2
- 239000004519 grease Substances 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000010297 mechanical methods and process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 101100454194 Caenorhabditis elegans mei-1 gene Proteins 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 240000007049 Juglans regia Species 0.000 description 1
- 235000009496 Juglans regia Nutrition 0.000 description 1
- 235000016496 Panda oleosa Nutrition 0.000 description 1
- 240000000220 Panda oleosa Species 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920006267 polyester film Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 235000011121 sodium hydroxide Nutrition 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 238000013022 venting Methods 0.000 description 1
- 235000020234 walnut Nutrition 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体パッケージ組立工程において、ンンゾル
な手段でバ’、１（ｆｌａｓｈ） を完全に除去できる
方法に則するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention is based on a method for completely removing flash by a gentle means in a semiconductor package assembly process.
半導体パッケージの製造技術は、近年半堺俸ｒｆ’＋Ｔ
要、の増大と高性能化に伴なって自ＩＩｖＪ化と高粘度
化が図られ、比類のない程進歩してさ／ヒ。現在広く行
われているその製造手段は次のようなものである。即ち
、部分メッキされたリードフレームにパ１′導体チップ
をボンティングし、気密」］止のため例えはエボキシイ
句脂でモールティングし、その際にモールド不要部分に
壕で飛散・流入したわ（脂つまりパリを除去し、次いで
半田（錫）によるメッキまたは浸漬でリードに外装処理
し、その後にマーキング等を施こすものである。In recent years, semiconductor package manufacturing technology has improved
Along with the increase in water content and higher performance, it has been made to have a higher viscosity and a higher viscosity, resulting in unparalleled progress. The currently widely used manufacturing methods are as follows. In other words, a P1' conductor chip was bonded to a partially plated lead frame, and molded with epoxy resin to prevent airtightness. At that time, the molding was scattered and flowed into areas where molding was not required. Grease and dirt are removed, the leads are then coated with solder (tin) plating or immersion, and markings are then applied.
半導体は今後もより一層の微細化・高性能化か図られる
とともに、品質の安定性と生産性・経済性の向上か必要
となる。そこで上記の如く組立工程も高精度化・自ＷＪ
化が図られ、ボンティングの７［程までは時代の要求に
応えられる技術水準に達しつつあるといえる。しかしモ
ールティングに伴なうパリ除去に関しては、未だ不充分
な技術水準にある。この点を詳述すると、リードフレー
ムにノクリが残留した１捷では後工程に悪影響を与え、
次の外装処坤を行なっても絶縁状組になり、半導体（」
、その性能を損ない製品としての侶頼度を失なう。その
ためフレームにパリの月相°のないことが１００％の完
全さで要求される。そこでツクＩＪの発生をなくすこと
も考えられたが、簡単で定型的なリードフレームについ
てはｒｊＪ能であっても、複雑で多岐にわたる品種を扱
かう場合には、／クリ発生を皆無にすることは不可能で
ある。Semiconductors will continue to be made smaller and more sophisticated, and it will be necessary to improve quality stability, productivity, and economic efficiency. Therefore, as mentioned above, the assembly process is also highly accurate and our own WJ
It can be said that the technical level of bonding technology is reaching a level that can meet the demands of the times. However, the level of technology is still inadequate regarding the removal of paris associated with molding. To explain this point in detail, a single process that leaves scraps on the lead frame will have a negative impact on the subsequent process.
Even if the next exterior treatment is performed, it will become an insulator-like assembly and a semiconductor (
, it impairs its performance and loses its reliability as a product. Therefore, 100% perfection is required that the frame be free of Parisian moon phases. Therefore, it was considered to eliminate the occurrence of IJ, but even though RJJ is effective for simple and standard lead frames, when dealing with complex and wide variety of products, it is necessary to eliminate the occurrence of IJ at all. is impossible.
それゆえパリ除去手段として現在まで種々のものが提案
され、化学的方法・電気的方法・機械的方法等がある。Therefore, various methods have been proposed as means for removing paris to date, including chemical methods, electrical methods, mechanical methods, etc.
しかし化学的方法は強酸に浸漬するだめフレームが細る
とともに、モールド部分も゛変質させる。電気的方法は
苛性ソーダ液中での電Ｍ 剥ｔｆＪｌＦであるが、フレ
ームが細密なものでり」、充分に剥陣ｆ、できない。機
械的方法は高圧エアー呼たは粒体を吹付けるが、前者は
細密なフレームでに、除去が不充分となり、仮名は粒体
としてのビーズ−にやくるみ殻の摩耗が早くランニング
コストか高い上に、モールド部分の表向を荒してし丑っ
たり、粒体がリード向に挾甘って残留することかある。However, the chemical method requires immersion in strong acid, which causes the frame to thin and the mold to deteriorate. The electrical method is to strip the material in a caustic soda solution, but the frame is so minute that it cannot be stripped sufficiently. Mechanical methods involve blowing high-pressure air or granules, but the former uses a fine frame, which results in insufficient removal, and the kana is beads as granules, which results in faster wear of the walnut shells and higher running costs. In addition, the surface of the mold part may be roughened, or particles may remain stuck in the direction of the lead.
それゆえ、上記手段をいくつか併用したり、人手により
ブラシで１余去したりして、ようやくパリを完全に除去
しているのか現状である。このように従来手段は非効率
的であるとともにそれに伴なう設備か犬かかりとなり、
甘た多くの検査・１余去要員か必要である等、多くの問
題点を而している。Therefore, at present, it is only possible to completely remove the paris by using several of the above-mentioned methods in combination, or by manually removing some particles with a brush. In this way, conventional means are not only inefficient, but also require the necessary equipment.
There are many problems such as excessive number of inspections and the need for one extra person.
しかも、今後史に半導体が複雑化・微細化してリードフ
レームも細乱化すると、このパリ除去手段は半導体パッ
ケージ組立工程中で、より一層大きなａ題となってくる
。Moreover, as semiconductors become more complex and finer in the future and lead frames become more disorganized, this means for removing paris will become an even bigger problem during the semiconductor package assembly process.
本発明は半導体パッケージ組立工程におけるバＩ〕除去
方法に関し、従来手段が有する」二足問題点を解決しよ
うとするものである。即ちその目的とするところは、モ
ールド工程で生じたパリを従来と異なりシンプルな手段
で完全に除去でき、かつ今後リードフレームが細密化さ
れてもそれに対応てき、その結果生産性・品質の安定性
・経ｈ−ｒ性を一層回」二できるような、半導体パッケ
ージｎ」立エイ′１（におけるパリ除去方法を提供しよ
うとするものである。The present invention is directed to solving the two-pronged problem that conventional means have with respect to a method for removing oxides in a semiconductor package assembly process. In other words, the purpose is to be able to completely remove the paris generated during the molding process with a simple method unlike the conventional one, and to be able to cope with the future miniaturization of lead frames, resulting in improved productivity and quality stability.・It is an object of the present invention to provide a method for removing pars in a semiconductor package (n'1), which can further improve the durability over time.
以下に本発明を第１図で示す工程とした場合の実施例に
よって説明する。The present invention will be explained below using an example in which the steps shown in FIG. 1 are used.
（１）ｌ／″ｉリードフレームで、第３図の如く中火に
アイランド都（２］をイ」”し、その局部に多数のイン
ナーリード（３１を句°する。このリードフレームｆ１
）に、回路を形成された半導体としてのＩＣチップ（４
）をボンティング、即ちチップボンティングとワイヤボ
ンティングする。この工程は従来と同じ手段により、高
精度で自動的に行えばよい。(1) Using a l/''i lead frame, heat the island cap (2) over medium heat as shown in Figure 3, and place a large number of inner leads (31) on the local area.This lead frame f1
), an IC chip (4
), that is, chip bonding and wire bonding. This step may be performed automatically with high precision using the same conventional means.
次に本発明の要部であるラミネート工程になる。Next comes the lamination step, which is the essential part of the present invention.
ＩＪＩｊら、１］ｖ記フレーム（１）両面のモールド不
要部分に、第４図、第５図で示すユうに両面から抛）漢
（５） （５）をＰｒ’ｒ度よく貼付する。この薄膜＋
５） （５］には銅やアルミニツムの如き金Ｊｇｂ箔、
あるいは商１然性あるプラスデックフィルムを月１いる
ものとし、そのンυｒ１ｆ菓（５） ＋５）のフレーム
［＋）への貼Ｎ面には接ネ１剤を塗布しである。その接
着剤には、モールティング四の雰囲気（１７０°Ｃで２
分間）に■え得るとともに、剥離。IJIj et al., 1] On both sides of the frame (1), where no mold is required, paste the adhesive (5) from both sides as shown in FIGS. 4 and 5. This thin film +
5) For (5), gold JGB foil such as copper or aluminum,
Alternatively, assume that you need a plastic film with a good quality of 1 per month, and apply an adhesive 1 to the N side of the frame [+] of the 100% polyester film (5) +5). The adhesive has a molding temperature of 2 at 170°C.
It can be peeled off in minutes).
時にフレーム（＋）曲に残留せぬ性質の然圧眉性ポリマ
ーを１米用する。Sometimes a natural eyebrow polymer that does not remain on the frame (+) track is used.
脱いでモールド工程に入り、フレームｆｌｕ、のＩＣチ
ップ（・１）を中心とする所定１１１６分、換ンｊすれ
ば薄膜ｔ５） （５）を貼付しなかった部分に、両面か
ら樹脂でモールティングされる。この場合に、モールド
都（６）周辺に（聞（脂が飛散したり、１メＬれ出して
両面に７１月７＋ ［７）か生ずるか、１ｆＪ１妃の如
くフレーム（１）のモールド不要部分に両面から島１１
Ｑ （５１ｔｂ）を貼付しである。After taking off the molding process, molding is done with resin from both sides on the part where the thin film t5) (5) was not attached for a predetermined 1116 minutes centering on the IC chip (1) of the frame flu. be done. In this case, grease may be scattered around the mold capital (6), or oil may leak out on both sides, or the parts of the frame (1) where the mold is not needed. Island 11 from both sides
Q (51tb) is attached.
そのため第６図・第７図で示す如く、バ１，１ （７）
＋７）は全て薄膜（５） ＋５）ｌに付着し、アクク
ーリード（８）面に付層したりリード間（９） Ｋ流れ
込むことはない。Therefore, as shown in Figures 6 and 7, bar 1, 1 (7)
+7) are all attached to the thin film (5) +5)l, and do not form a layer on the surface of the aku lead (8) or flow between the leads (9).
その次は薄膜剥離工程であり、第８図のように前記薄膜
（５）（５）をフレーム［１）から剥ば１．する。この
薄膜（５） ＋５＋の剥離により、薄膜（５）（５）に
付着しだ７１月７）（７）は熱膜ｔ５＋ ＋５＋と共に
フレーム（１）から全て除去されることｅでなる。その
結果第９図で示す如く、アククーリード（８）而やリー
ド間（９）にパ１月７） （７）か全く行右しないリー
ドフレーム（ｌ］か得られる。壕だ接着剤も劫；１りｉ
５） ｆ５１と共に剥れるので、フレーム（１）に残留
することはない。剥削：された助Ｉｊ別５１ ｆ５）は
、それが金民箔の場合には回収して再資源として利１月
すればよい。The next step is a thin film peeling process, in which the thin film (5) (5) is peeled off from the frame [1] as shown in FIG. do. By peeling off this thin film (5) +5+, all of the thin film (5) (7) attached to the thin film (5) (5) is removed from the frame (1) together with the hot film t5+ +5+. As a result, as shown in Fig. 9, a lead frame (l) is obtained in which the lead (8) and between the leads (9) do not move at all. 1ri i
5) Since it peels off together with f51, it does not remain on the frame (1). If it is gold minpaku, it is sufficient to collect the scraped material and use it as a recycled resource.
なお」二足実施例では、薄１俟ｆ５＋ ＋５＋のラミネ
ートをボンティング工程後でモールド工程の直前に行な
ったか、これに限らす例えば第２図の如くリードフレー
ム（１）に部分メッキをする１ｉｉＪに、同様にしてモ
ールド不要Ｈ１ｓ分に両面から薄膜＋５） ＋５＋を貼
（＝ｔ してもよい。この場合には、へ９１ｊ央ｆ５１
．（５１かフレームｆｌ） ノアククーリード（８）を
両側から挾持することになるので、部分メッキ時やボン
ティング工程で起りｊ＋ｊ・るリード（８）の曲りやそ
の他のｙ形を防止する効果も併せ有する。In the two-leg example, the lamination with a thickness of 1 yen f5+ +5+ was carried out after the bonding process and immediately before the molding process. In the same way, a thin film +5) +5+ may be applied (=t) from both sides for H1s that does not require molding. In this case,
．． (51 or frame fl) Since the Noah lead (8) is held from both sides, it also has the effect of preventing bending of the lead (8) and other Y-shapes that occur during partial plating and bonding processes. Have both.
そして以後はアクタ−リード（８）に半１」」（錫）で
外装処理し、マーキング・カッティングおよび必要に応
じてベンティング等の工程を経て、半）心棒組立工程か
完了する。Thereafter, the actor lead (8) is coated with half-metal (tin), marking, cutting, and if necessary, venting, etc., to complete the semi-mandrel assembly process.
以上で明かな如く、本発明の半導体パッケージ組立工程
におけるパリ除去方法−１、リードフレームのモールド
不要１部分に、遅くともモールティングの１自１０に両
市ｊから戎ｉ４ ＩＩ央をラミネートし、モールティン
グ後にその劫１模をそこに付ｆｉ”’＋シたパリと共に
剥削するものである。それゆえこのＩｊＺ Ｉ模の１４
！ｉ付により、パリはフレームに付層せす全て薄膜」−
に付ヰ４するとともに、リード（＋４＋に７４シれ込む
こともない。そしてデ由膜の剥削によりパリは一緒に除
去され、フレームにはパリか全く伐らないものである。As is clear from the above, in the method for removing paris in the semiconductor package assembly process of the present invention - 1, a molding-free part of the lead frame is laminated with moldings from 1 to 10 of the molding at the latest. Later, that kalpa 1 model is to be removed along with the pari attached to it.Therefore, this IjZ I model 14
! With I, all thin films are attached to the frame.
In addition to attaching ッ4 to the lead (+4+), there is no 74 depression.And by scraping the membrane, the paris is removed along with it, and there is no paris cut on the frame at all.
したかって本発明によれば、従来と異なるきわめてシン
プルな手段でありながら、パリを完全に除去でき、リー
ドを害することもなく、かつ今後リードフレームか、ｆ
ｌＩＩ密化されても充分にそれに対応できるものである
。その結果、本発明のパリ除去方法は半導体の品質の安
定性と生産性・経済性の向上に大いに貢献するものであ
る。Therefore, according to the present invention, although it is an extremely simple means different from the conventional method, it is possible to completely remove the paris, without damaging the leads, and in the future, lead frames or f
Even if it becomes denser, it can fully cope with it. As a result, the method for removing paris of the present invention greatly contributes to improving the stability of semiconductor quality, productivity, and economic efficiency.
なお、上記実施例では半導体としてＩＣのパッケージの
場合を説明したが、それに限らず広く半導体パッケージ
でのパリ除去方法としても利用できるものである。In the above embodiment, the case of an IC package as a semiconductor was explained, but the present invention is not limited to this and can be used as a method for removing pars from a wide variety of semiconductor packages.
図（１１：本発明の実施例を示すものであり、第１図は
その工程図、第２図は他の実施例の工程図、第３図はＩ
ＣＩＪ−ドフレームの平面図、第４図はポジティング
後に薄膜をラミネートしだ状恵の平ｄＩＪ図、第５図は
第４図のＡ−Ａ線での−（３１＜拡大縦胃Ｔｉｊｎ図、
第６図はモールティング後の斜視図、第７図は第６区の
Ｂ−Ｂ線での一部拡大縦断面図、第８図は薄膜剥離時の
斜視図、第９図は薄）模剥離後の一部拡大縦断面図であ
る。
図由］省丁りｆｌｊ・・・リードフレーム、（３）・・
・インナーリード、（４）・・・半導体チップ、（６）
・・９専１模、（６）・・・モールＦ都、（７）−パリ
、（８）・・・アクタ−リード、（９）・・・リード１
０１
出願人 北城敵也
Ａ−４４１１人古’ｎｍ
第１図 第２図
手続補正書 明１
１゜５９４１Ｌ４□。８ 下０
”° ＩＴ （４′Ｏ９ｙｒ＜ カロ圧昭和５９年特
許 願第２８８９８号 等に２発明の名称
事件との関係 特許出願人
６二９″所 大阪府７暴１Ｗに習３丁３３番６号氏 名
（名称） ホウ
北 、城 徹 也
４、代理人
住 所 大阪府堺市向陵中町２丁４番２３号１１１書第
６頁第７行目「採用する。」の次に以幻章を補充する。Figure (11: Shows an embodiment of the present invention; Figure 1 is a process diagram thereof, Figure 2 is a process diagram of another embodiment, and Figure 3 is an I
A plan view of the CIJ frame, Figure 4 is a flat dIJ diagram of the laminated thin film after positing, and Figure 5 is an enlarged vertical stomach diagram taken along line A-A in Figure 4. ,
Fig. 6 is a perspective view after molding, Fig. 7 is a partially enlarged vertical sectional view taken along the line B-B of section 6, Fig. 8 is a perspective view when the thin film is peeled off, and Fig. 9 is a thin film pattern. FIG. 3 is a partially enlarged vertical cross-sectional view after peeling. Illustration] Shortcut flj...Lead frame, (3)...
・Inner lead, (4)...Semiconductor chip, (6)
...9th grade 1 model, (6)...Mall F city, (7)-Paris, (8)...actor lead, (9)...lead 1
01 Applicant Hokujo Eniya A-4411人古'nm Figure 1 Figure 2 Procedural Amendment Mei 1 1゜5941L4□. 8 Lower 0”° IT (4’O9yr< Caro Pressure 1984 Special
Relationship with the patent application No. 28898, etc. Patent applicant 629″ Osaka Prefecture 7-1W 3-33-6 Xi 3rd-33-6 Name Hou Kita, Tetsuya Jo 4, Agent Address: 111, 2-4-23 Kouryo Nakamachi, Sakai City, Osaka Prefecture, page 6, line 7, add the Igensho after ``Adopt.''
Claims (1)
チップをポジティングしてそれを椅脂でモールティング
し、フレームに付着のパリを除去した後、リードに外装
処」４１ジする工程をもつ半導体パッケージ組立工程に
おいて、パリ除去の工程として、遅くともモールディン
グの工程凸曲に、フレームのモールド不要部分へ両面か
ら薄１模をラミネートし、モールティング後にその薄ｌ
Ｉ欠をそこに細心したパリと共にＩＩＪ随するようにし
たことを特徴とする、半導体パンケージ組立工程におけ
るパリ除去力法。 ■リードフレームへの薄膜のラミネートを、リードフレ
ームＶこ部分メッキがなされる１ｆＪに行なうようにし
た、特許請求の範′１ｉ１１第１項に記載の半導体パッ
ケージ組立工程におけるパリ除去方法。 ■リードフレームへの４１１１０のラミネートを、モー
ルティングする＋１ ｎｆ；に行なうようにした、ｈ泊
著情求の範囲第１項に記載の半導体パッケージ組立工程
におけるパリ除去力法。[Claims] ■Position a semiconductor chip on a lead frame that has been plated for i and jis, mold it with resin, remove any particles adhering to the frame, and then apply an exterior coating to the leads.''41 In the semiconductor package assembly process, which involves molding, a thin film is laminated from both sides to the convex curve of the molding process at the latest, on the part of the frame that does not require molding, and the thin film is removed after molding.
A method for removing paris in a semiconductor package assembly process, characterized in that an I-missing part is accompanied by an IIJ along with a carefully placed paris therein. (2) A method for removing paris in a semiconductor package assembly process according to claim 111, wherein the thin film is laminated to the lead frame at 1 fJ where the V portion of the lead frame is plated. (2) The pari removal force method in the semiconductor package assembly process described in item 1 of the request by H Tomari, in which the lamination of 41110 to the lead frame is carried out at +1 nf;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2889884A JPS60173847A (en) | 1984-02-18 | 1984-02-18 | Deburring method in assembly process for semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2889884A JPS60173847A (en) | 1984-02-18 | 1984-02-18 | Deburring method in assembly process for semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60173847A true JPS60173847A (en) | 1985-09-07 |
Family
ID=12261215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2889884A Pending JPS60173847A (en) | 1984-02-18 | 1984-02-18 | Deburring method in assembly process for semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60173847A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4885837A (en) * | 1988-01-13 | 1989-12-12 | Mitsubishi Denki Kabushiki Kaisha | Apparatus for forming leads of semiconductor devices |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5662347A (en) * | 1979-10-26 | 1981-05-28 | Hitachi Ltd | Production of resin molded ic |
-
1984
- 1984-02-18 JP JP2889884A patent/JPS60173847A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5662347A (en) * | 1979-10-26 | 1981-05-28 | Hitachi Ltd | Production of resin molded ic |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4885837A (en) * | 1988-01-13 | 1989-12-12 | Mitsubishi Denki Kabushiki Kaisha | Apparatus for forming leads of semiconductor devices |
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