CN205582933U - Two -sided fan -out type wafer -level package structure - Google Patents
Two -sided fan -out type wafer -level package structure Download PDFInfo
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- CN205582933U CN205582933U CN201620076472.XU CN201620076472U CN205582933U CN 205582933 U CN205582933 U CN 205582933U CN 201620076472 U CN201620076472 U CN 201620076472U CN 205582933 U CN205582933 U CN 205582933U
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- wiring layer
- type wafer
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- sided fan
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model provides a two -sided fan -out type wafer -level package structure, including basement, a rewiring layer, the 2nd rewiring layer, through hole electrode, first device, first electrode lug, a solidified material, second device, second electrode lug and the 2nd solidified material, the through hole electrode connection is passed through on first, the 2nd rewiring layer, and each electrode exposes in the solidified material surface. The utility model discloses an interconnection of two -sided device is realized to preparation electrode through -hole to multilayer packaging structure's vertical interconnect can be realized, different electronic equipment functions are realized, the rewiring layer makeed before the chip adheres to, avoided the chip to shift, adhere the structure on the carrier, avoid the structure warpage, draw as the interconnection with the electrode lug, provide the assurance for the integration of multiple different devices, thickness through control solidified material comes drawing forth of control electrode lug, has saved solidified material's grinding technics, through two -sided fan -out type encapsulation, improve the integrated level of device greatly.
Description
Technical field
This utility model belongs to field of semiconductor package, particularly relates to a kind of two-sided fan-out-type wafer-level packaging method and encapsulating structure.
Background technology
Fan-out-type wafer-level packaging (Fan-out Wafer Level package, FOWLP) it is the embedded chip method for packing of a kind of wafer level processing, is a kind of one of input/output end port (I/O) motility more, integrated preferable Advanced Packaging method.The advantage that fan-out-type wafer-level packaging has its uniqueness compared to conventional wafer-level packaging: 1. I/O spacing is flexible, does not relies on chip size；The most only using effective die, product yield improves；3. there is 3D package path flexibly, i.e. can form the figure of General Cell at top；4. there is preferable electrical property and hot property；5. frequency applications；6. easily in re-wiring layer (RDL), high-density wiring is realized.
Existing fan-out-type wafer-level packaging method is generally: provide carrier, forms adhesive layer at carrier surface；Semiconductor chip is faced up and is mounted on adhesive layer surface；Dielectric layer；Photoetching, electroplate out re-wiring layer (RDL)；Use Shooting Technique by semiconductor chip plastic packaging in capsulation material layer；Plastic packaging grinds, opening；Photoetching, electroplate out ball lower metal layer；Carry out planting ball backflow, form welded ball array；Remove carrier.And, during the techniques such as moulding process and follow-up solder backflow, easily there is warpage, the defect such as ruptures, thus reduce the yield rate of encapsulating products in prior art.Chip can be packaged on two surfaces of same substrate by two-sided fan-out-type chip encapsulation technology simultaneously, can be greatly improved the integrated level of device, reduces cost.Simultaneously by the application of carrier, reduce warpage, improve yield rate for these reasons, it is provided that a kind of step is simple, low cost and be effectively improved integrated level, and the two-sided fan-out-type wafer-level packaging method of yield rate and encapsulating structure are necessary.
Utility model content
The feature of prior art in view of the above, the purpose of this utility model is to provide a kind of novel two-sided fan-out-type wafer-level packaging method and encapsulating structure, for improving the integrated level encapsulating finished product in prior art, reduces cost.
For achieving the above object and other relevant purposes, this utility model provides a kind of two-sided fan-out-type wafer-level packaging method, including step: step 1), it is provided that a substrate, make the first re-wiring layer in described substrate first surface；Step 2), the first device is attached to described first re-wiring layer, and realizes the first device and the electric connection of the first re-wiring layer；Step 3), on described first re-wiring layer, make the first electrode bumps；Step 4), the first device is shaped technique, after molding, exposes described first electrode bumps；Step 5), it is bonded in exposing the one side having the first electrode bumps on a carrier based on adhesive layer；Step 6), formed in described substrate through the through hole electrode between described first re-wiring layer and the second surface of substrate；Step 7), the second surface in described substrate makes the second re-wiring layer, and realizes each through hole electrode and the electric connection of the second re-wiring layer；Step 8), the second device is attached to described second re-wiring layer, and realizes the second device and the electric connection of the second re-wiring layer；Step 9), on described second re-wiring layer, make the second electrode bumps；Step 10), the second device is shaped technique, after molding, exposes described second electrode bumps；Step 11), remove described adhesive layer and carrier.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present utility model, described first re-wiring layer and the second re-wiring layer include patterned dielectric layer and patterned metal wiring layer.
Preferably, the material of described dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass, one or more combinations in fluorine-containing glass.
Preferably, one or more combinations during the material of described metal wiring layer includes copper, aluminum, nickel, gold, silver, titanium.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present utility model, described first device and the second device include one or both combinations in bare chip and packaged chip.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present utility model, step 3) including: step 3-1), on described first re-wiring layer, make copper post；Step 3-2), on described copper post, make nickel dam；Step 3-3), on described nickel dam, make solder metal, and carry out high temperature reflux formation solder ball, to complete the preparation of the first electrode bumps.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present utility model, step 4) and step 10) the curing materials that used of moulding process include the one in polyimides, silica gel and epoxy resin.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present utility model, the material of described carrier includes one or more the composite in silicon, glass, silicon oxide, pottery, polymer and metal.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present utility model, described adhesive layer comprises one layer of stratum disjunctum, step 10) in can be irradiated by UV or laser removes it so that device is detached from the carrier；Remaining adhesive layer is removed by chemical reagent so that adhesive layer and the first projection separate.
As a kind of preferred version of two-sided fan-out-type wafer-level packaging method of the present utility model, step 9) including: step 9-1), on described second re-wiring layer, make copper post；Step 9-2), on described copper post, make nickel dam；Step 9-3), on described nickel dam, make solder metal, and carry out high temperature reflux formation solder ball, to complete the preparation of the second electrode bumps.
This utility model also provides for a kind of two-sided fan-out-type wafer level packaging structure, including: substrate, the first surface of described substrate is formed with the first re-wiring layer, second surface is formed in the second re-wiring layer, and described substrate and is formed with described first re-wiring layer of connection and the through hole electrode of the second re-wiring layer；First device, is fixed on described first re-wiring layer, and with the electric connection of the first re-wiring layer；First electrode bumps, is formed on described first re-wiring layer；First curing materials, is covered in described first device surface, and exposes and have described first electrode bumps；Second device, is fixed on described second re-wiring layer, and with the electric connection of the second re-wiring layer；Second electrode bumps, is formed on described second re-wiring layer；Second curing materials, is covered in described second device surface, and exposes and have described second electrode bumps.
As a kind of preferred version of two-sided fan-out-type wafer level packaging structure of the present utility model, described first re-wiring layer and the second re-wiring layer include patterned dielectric layer and patterned metal wiring layer.
As a kind of preferred version of two-sided fan-out-type wafer level packaging structure of the present utility model, the material of described dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass, one or more combinations in fluorine-containing glass.
As a kind of preferred version of two-sided fan-out-type wafer level packaging structure of the present utility model, the material of described metal wiring layer includes one or more combinations in copper, aluminum, nickel, gold, silver, titanium
As a kind of preferred version of two-sided fan-out-type wafer level packaging structure of the present utility model, described first device and the second device include one or both combinations in bare chip and packaged chip.
As a kind of preferred version of two-sided fan-out-type wafer level packaging structure of the present utility model, described curing materials includes the one in polyimides, silica gel and epoxy resin.
As a kind of preferred version of two-sided fan-out-type wafer level packaging structure of the present utility model, described first electrode bumps and the second electrode bumps include copper post, the nickel dam being formed on described copper post and are formed at the solder ball on described nickel dam.
As it has been described above, two-sided fan-out-type wafer-level packaging method of the present utility model and encapsulating structure, have the advantages that
1) realizing the interconnection between double-sided device by making electrode through hole in substrate, this structure can realize the perpendicular interconnection of multilayer encapsulation structure, it is achieved different electronic functionalities；
2) before re-wiring layer is made in chip attachment, the chip in forming process can be avoided to shift, it is to avoid line is abnormal；
3) by structure bond on carrier, it is to avoid the structure curl that causes during making re-wiring layer and solder ball, the defect such as rupture；
4) using electrode bumps to draw as interconnection, integrated for multiple different components provides effective guarantee；
5) control the extraction of electrode bumps by controlling the thickness of curing materials, save the technique such as grinding of curing materials.
Accompanying drawing explanation
Fig. 1～Figure 15 is shown as the structural representation that the two-sided each step of fan-out-type wafer-level packaging method of the present utility model is presented, and wherein, Figure 15 is shown as the structural representation of two-sided fan-out-type wafer level packaging structure of the present utility model.
Element numbers explanation
101 substrates
102 first re-wiring layers
103 bare chips
104 packaged chips
105 first electrode bumps
106 first curing materials
107 adhesive layers
108 carriers
109 through hole electrodes
110 second re-wiring layers
111 packaged chips
112 bare chips
113 second electrode bumps
114 second curing materials
Detailed description of the invention
Below by way of specific instantiation, embodiment of the present utility model being described, those skilled in the art can be understood other advantages of the present utility model and effect easily by the content disclosed by this specification.This utility model can also be carried out by the most different detailed description of the invention or apply, and the every details in this specification can also carry out various modification or change based on different viewpoints and application under without departing from spirit of the present utility model.
Refer to Fig. 1～Figure 15.It should be noted that, diagram provided in the present embodiment illustrates basic conception of the present utility model the most in a schematic way, component count, shape and size when then only showing the assembly relevant with this utility model rather than implement according to reality in diagram are drawn, during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout kenel is likely to increasingly complex.
As shown in Fig. 1～Figure 15, the present embodiment provides a kind of two-sided fan-out-type wafer-level packaging method, including step:
As shown in Fig. 1～Fig. 2, first carry out step 1), it is provided that a substrate 101, make the first re-wiring layer 102 in described substrate 101 first surface.
As example, described substrate 101 can be that the materials such as silicon, silicon dioxide, BCB plate, pottery, glass, polymer are made.
As example, described first re-wiring layer 102 includes patterned dielectric layer and patterned metal wiring layer.The material of described dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass, the one in fluorine-containing glass.The material of described metal wiring layer includes one or more combinations in copper, aluminum, nickel, gold, silver, titanium.
As it is shown on figure 3, then carry out step 2), the first device is attached to described first re-wiring layer 102, and realizes the first device and the electric connection of the first re-wiring layer 102.
As example, described first device includes one or more combinations in bare chip and packaged chip.In the present embodiment, described first device includes two kinds of devices, and wherein, a kind of device is bare chip 103, and another kind of device is packaged chip 104, and described first device can be the device architecture realizing any function, however it is not limited to example recited herein.
As shown in Figure 4, then carry out step 3), on described first re-wiring layer 102, make the first electrode bumps 105.
As example, step 3) including:
Step 3-1), on described first re-wiring layer 102, make copper post；
Step 3-2), on described copper post, make nickel dam；
Step 3-3), on described nickel dam, make solder metal, and carry out high temperature reflux formation solder ball, to complete the preparation of the first electrode bumps 105.As example, described solder metal is silver ashbury metal.
As it is shown in figure 5, then carry out step 4), the first device is shaped technique, after molding, exposes described first electrode bumps 105.
As example, by controlling the thickness of the first curing materials of described moulding process, it is achieved exposing of described first electrode bumps 105, to save follow-up grinding with the technique the first electrode bumps exposed, it is greatly saved process costs.
As example, the first curing materials 106 that the moulding process of this step is used includes the one in polyimides, silica gel and epoxy resin.
As example, moulding process can include spin coating proceeding, Shooting Technique, compressing and forming process, typography, transfer modling technique, fluid sealant cure process and vacuum lamination process etc..As example, it is used herein as compressing and forming process.
As shown in Figure 6, then carry out step 5), it is bonded in exposing the one side having the first electrode bumps 105 on a carrier 108 based on adhesive layer 107.
As example, the material of described carrier 108 includes one or more the composite in silicon, glass, silicon oxide, pottery, polymer and metal.
As example, described adhesive layer 107 can be adhesive tape, epoxy resin, UV adhesive glue etc., and follow-up removal technique can be exposure method, laser ablation, solution corrosion etc..In the present embodiment, described adhesive layer 107 includes a stratum disjunctum, the step 10 follow-up) in, use laser ablation to remove stratum disjunctum, then separate with the first electrode bumps 105 to realize it with the chemical reagent remaining adhesive layer of removal.
As shown in Fig. 7～Figure 10, then carry out step 6), thinning described substrate 101, formed in described substrate 101 through the through hole electrode 109 between described first re-wiring layer 102 and the second surface of substrate 101.
Specifically, this step includes:
As it is shown in fig. 7, first carry out step 6-1), by the thinning described substrate 101 of Ginding process；
As shown in Figure 8, then carry out step 6-2), in described base, form through hole by photoetching-method such as etching or laser；
As it is shown in figure 9, then carry out step 6-3), in described through hole, deposit metal material, such as copper, aluminum etc.；
As shown in Figure 10, finally carry out step 6-4), remove the metal material of substrate 101 excess surface, polishing processes or etch etc. can be adopted as.
As shown in figure 11, then carry out step 7), the second surface in described substrate 101 makes and the second re-wiring layer 110, and realizes each through hole electrode 109 and the electric connection of the second re-wiring layer 110.
As example, described second re-wiring layer 110 includes patterned dielectric layer and patterned metal wiring layer.The material of described dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass, the one in fluorine-containing glass.The material of described metal wiring layer includes one or more combinations in copper, aluminum, nickel, gold, silver, titanium.
As shown in figure 12, then carry out step 8), the second device is attached to described second re-wiring layer 110, and realizes the second device and the electric connection of the second re-wiring layer 110.
As example, described second device includes one or more combinations in bare chip and packaged chip.In the present embodiment, described second device includes two kinds of different devices, one is bare chip 112, another kind is packaged chip 111, wherein, described second device and the first device can be identical chip, it is also possible to for different chips, can carry out integrated, to meet different application demands according to needing the device selecting difference in functionality.
As shown in figure 13, then carry out step 9), on described second re-wiring layer 110, make the second electrode bumps 113.
As example, step 9) including:
Step 9-1), on described second re-wiring layer 110, make copper post；
Step 9-2), on described copper post, make nickel dam；
Step 9-3), on described nickel dam, make solder metal, and carry out high temperature reflux formation solder ball, to complete the preparation of the second electrode bumps 113.In the present embodiment, described solder metal is silver ashbury metal.
As shown in figure 14, then carry out step 10), the second device is shaped technique, after molding, exposes described second electrode bumps 113.
As example, by controlling the thickness of the second curing materials of described moulding process, it is achieved exposing of described second electrode bumps 113, to save follow-up grinding with the technique the second electrode bumps exposed, it is greatly saved process costs.
As example, the second curing materials 114 that moulding process is used includes the one in polyimides, silica gel and epoxy resin.
As shown in figure 15, finally carry out step 11), remove described adhesive layer 107 and carrier 108.
As example, described adhesive layer 107 comprises one layer of stratum disjunctum, uses laser ablation to remove stratum disjunctum, then removes remaining adhesive layer with chemical reagent so that carrier and the first electrode bumps 105 separate.As shown in figure 15, the present embodiment also provides for a kind of two-sided fan-out-type wafer level packaging structure, including: substrate 101, the first surface of described substrate 101 is formed with the first re-wiring layer 102, second surface is formed with the second re-wiring layer 110, and is formed with described first re-wiring layer 102 and the through hole electrode 109 of the second re-wiring layer 110 of connection in described substrate 101；First device, is fixed on described first re-wiring layer 102, and with the electric connection of the first re-wiring layer 102；First electrode bumps 105, is formed on described first re-wiring layer 102；First curing materials 106, is covered in described first device surface, and exposes and have described first electrode bumps 105；Second device, is fixed on described second re-wiring layer 110, and with the electric connection of the second re-wiring layer 110；Second electrode bumps 113, is formed on described second re-wiring layer 110；Second curing materials 114, is covered in described second device surface, and exposes and have described second electrode bumps 113.
As example, described first re-wiring layer 102 and the second re-wiring layer 110 include patterned dielectric layer and patterned metal wiring layer.
As example, the material of described dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass, one or more combinations in fluorine-containing glass.
As example, the material of described metal wiring layer includes one or more combinations in copper, aluminum, nickel, gold, silver, titanium.
As example, described first device and the second device include one or both combinations in bare chip and packaged chip.
As example, described curing materials includes the one in polyimides, silica gel and epoxy resin.
As example, described first electrode bumps 105 and the second electrode bumps 113 include copper post, the nickel dam being formed on described copper post and are formed at the solder ball on described nickel dam.
As it has been described above, two-sided fan-out-type wafer-level packaging method of the present utility model and encapsulating structure, have the advantages that
1) realizing the interconnection between double-sided device by making electrode through hole in substrate 101, this structure can realize the perpendicular interconnection of multilayer encapsulation structure, it is achieved different electronic functionalities；
2) before re-wiring layer is made in chip attachment, the chip in forming process can be avoided to shift, it is to avoid line is abnormal；
3) by structure bond on carrier 108, it is to avoid the structure curl that causes during making re-wiring layer and solder ball, the defect such as rupture；
4) using electrode bumps to draw as interconnection, integrated for multiple different components provides effective guarantee；
5) control the extraction of electrode bumps by controlling the thickness of curing materials, save the technique such as grinding of curing materials.
So, this utility model effectively overcomes various shortcoming of the prior art and has high industrial utilization.
Above-described embodiment only illustrative principle of the present utility model and effect thereof, not for limiting this utility model.Above-described embodiment all can be modified under spirit and the scope of the present utility model or change by any person skilled in the art.Therefore, art has all equivalence modification or changes that usually intellectual is completed under without departing from the spirit disclosed in this utility model and technological thought such as, must be contained by claim of the present utility model.
Claims (7)
1. a two-sided fan-out-type wafer level packaging structure, it is characterised in that including:
Substrate, the first surface of described substrate is formed with the first re-wiring layer, and second surface is formed in the second re-wiring layer, and described substrate and is formed with described first re-wiring layer of connection and the through hole electrode of the second re-wiring layer；
First device, is fixed on described first re-wiring layer, and with the electric connection of the first re-wiring layer；
First electrode bumps, is formed on described first re-wiring layer；
First curing materials, is covered in described first device surface, and exposes and have described first electrode bumps；
Second device, is fixed on described second re-wiring layer, and with the electric connection of the second re-wiring layer；
Second electrode bumps, is formed on described second re-wiring layer；
Second curing materials, is covered in described second device surface, and exposes and have described second electrode bumps.
Two-sided fan-out-type wafer level packaging structure the most according to claim 1, it is characterised in that: described first re-wiring layer and the second re-wiring layer include patterned dielectric layer and patterned metal wiring layer.
Two-sided fan-out-type wafer level packaging structure the most according to claim 2, it is characterized in that: described dielectric layer is epoxy resin medium layer, silica gel dielectric layer, PI dielectric layer, PBO dielectric layer, BCB dielectric layer, silicon oxide dielectric layer, phosphorosilicate glass dielectric layer, the one in fluorine-containing glass medium layer.
Two-sided fan-out-type wafer level packaging structure the most according to claim 2, it is characterised in that: described metal wiring layer is the one in copper wiring layer, aluminum wiring layer, nickel wiring layer, gold wiring layer, silver wiring layer, titanium wiring layer.
Two-sided fan-out-type wafer level packaging structure the most according to claim 1, it is characterised in that: described first device and the second device include one or both combinations in bare chip and packaged chip.
Two-sided fan-out-type wafer level packaging structure the most according to claim 1, it is characterised in that: described curing materials is polyimides, a kind of formed curing materials in silica gel and epoxy resin.
Two-sided fan-out-type wafer level packaging structure the most according to claim 1, it is characterised in that: described first electrode bumps and the second electrode bumps include copper post, the nickel dam being formed on described copper post and are formed at the solder ball on described nickel dam.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620076472.XU CN205582933U (en) | 2016-01-26 | 2016-01-26 | Two -sided fan -out type wafer -level package structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620076472.XU CN205582933U (en) | 2016-01-26 | 2016-01-26 | Two -sided fan -out type wafer -level package structure |
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| CN205582933U true CN205582933U (en) | 2016-09-14 |
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| CN201620076472.XU Active CN205582933U (en) | 2016-01-26 | 2016-01-26 | Two -sided fan -out type wafer -level package structure |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |
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