JPS60167420U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS60167420U
JPS60167420U JP5416784U JP5416784U JPS60167420U JP S60167420 U JPS60167420 U JP S60167420U JP 5416784 U JP5416784 U JP 5416784U JP 5416784 U JP5416784 U JP 5416784U JP S60167420 U JPS60167420 U JP S60167420U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor device
insulated gate
gate transistor
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5416784U
Other languages
Japanese (ja)
Inventor
高橋　明憲
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP5416784U priority Critical patent/JPS60167420U/en
Publication of JPS60167420U publication Critical patent/JPS60167420U/en
Pending legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は可変利得型増幅器の回路図である。 Ｑｌ、　Ｇ２　：　ｐ型ＭＯ３ＦＥＴ、Ａ：演算増幅器
の反転電圧、Ｒ１？　Ｒ２ｔ　ＲＨ：抵抗、Ｇ□ｇ　Ｇ
２　：　Ｑｌ、　Ｇ２のゲート、■＋：電源電圧、■−
：最低電圧、ｖｌ：演算増幅器の、■ｐ：ドレン電圧。 第２図は従来のモノリシック集積回路のＰ　−ＭＯＳＦ
ＥＴの断面図である。 １：Ｐ型半導体基板、２：島状Ｎ型領域、３：Ｎ＋領領
域４：Ｐ＋絶縁領域、５ニドレイン、６：ソース、Ｃｊ
：Ｎ型領域とドレイン、ソースとの接合容量の和。 第３図は本考案の一実施例を示す断面である。 ７：定電圧源に接続された配線。FIG. 1 is a circuit diagram of a variable gain amplifier. Ql, G2: p-type MO3FET, A: operational amplifier inversion voltage, R1? R2t RH: resistance, G□g G
2: Ql, gate of G2, ■+: power supply voltage, ■-
: lowest voltage, vl: operational amplifier, ■p: drain voltage. Figure 2 shows a conventional monolithic integrated circuit P-MOSF.
It is a sectional view of ET. 1: P-type semiconductor substrate, 2: Island-like N-type region, 3: N+ region 4: P+ insulating region, 5 Nidrain, 6: Source, Cj
: Sum of junction capacitances between the N-type region, drain, and source. FIG. 3 is a cross-sectional view showing one embodiment of the present invention. 7: Wiring connected to a constant voltage source.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] バイポーラ型トランジスタで構成された増幅器とこの増
幅器の入力に接続された少なくとも一つの絶縁ゲート型
トランジスタとが集積回路化された半導体装置において
、前記絶縁ゲート型トランジスタが形成された島状領域
を入力電圧より高い定電圧源でバイアスしたことを特徴
とする半導体装置。In a semiconductor device in which an amplifier composed of bipolar transistors and at least one insulated gate transistor connected to an input of the amplifier are integrated into an integrated circuit, an island-like region in which the insulated gate transistor is formed is connected to an input voltage. A semiconductor device characterized in that it is biased with a higher constant voltage source.
JP5416784U 1984-04-13 1984-04-13 semiconductor equipment Pending JPS60167420U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5416784U JPS60167420U (en) 1984-04-13 1984-04-13 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5416784U JPS60167420U (en) 1984-04-13 1984-04-13 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS60167420U true JPS60167420U (en) 1985-11-07

Family

ID=30575682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5416784U Pending JPS60167420U (en) 1984-04-13 1984-04-13 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS60167420U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09135132A (en) * 1995-11-10 1997-05-20 Fujitsu Ltd Amplifier circuit
JP2001126492A (en) * 1999-10-27 2001-05-11 Agilent Technologies Japan Ltd Track-and-hold circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54107246A (en) * 1978-02-09 1979-08-22 Matsushita Electric Ind Co Ltd Analogue switch and sample hold circuit using it

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54107246A (en) * 1978-02-09 1979-08-22 Matsushita Electric Ind Co Ltd Analogue switch and sample hold circuit using it

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09135132A (en) * 1995-11-10 1997-05-20 Fujitsu Ltd Amplifier circuit
JP2001126492A (en) * 1999-10-27 2001-05-11 Agilent Technologies Japan Ltd Track-and-hold circuit

Similar Documents

Publication Publication Date Title
JPS6397248U (en)
JPS5948142U (en) MOS input buffer circuit with hysteresis characteristics
JPS60167420U (en) semiconductor equipment
JPH0328517Y2 (en)
JP3199857B2 (en) Conductivity modulation type MOSFET
JPS5856457U (en) semiconductor equipment
JPH0525234Y2 (en)
JPS59119045U (en) High power high frequency transistor
JPS61102057U (en)
JPH03148866A (en) Semiconductor device
JPS60193708U (en) Low input terminal voltage type current mirror circuit
JPS6047200U (en) sample hold circuit
JPS59119047U (en) High power high frequency transistor
JPS6197843U (en)
JPS6362901B2 (en)
JPS5885362U (en) semiconductor integrated device
JPS59176149U (en) semiconductor integrated circuit
JPH01123365U (en)
JPS6217154U (en)
JPS5883162U (en) semiconductor equipment
JPS61188366U (en)
JPS5952733U (en) D/A converter output buffer circuit
JPS6397913U (en)
JPS6144854U (en) CMOS output buffer
JPS6133455U (en) semiconductor equipment