JPS6047200U - sample hold circuit - Google Patents
sample hold circuitInfo
- Publication number
- JPS6047200U JPS6047200U JP12224384U JP12224384U JPS6047200U JP S6047200 U JPS6047200 U JP S6047200U JP 12224384 U JP12224384 U JP 12224384U JP 12224384 U JP12224384 U JP 12224384U JP S6047200 U JPS6047200 U JP S6047200U
- Authority
- JP
- Japan
- Prior art keywords
- field effect
- effect transistor
- sampling field
- sampling
- hold circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図ａ、 ｂおよび第２図は従来のサンプルホールド
回路の例を示す回路図、第３図および第４ 。
図は本考案の実施例を示す回路図、第５図は該実施例に
おけるトランジスタめレイアウトを示す概略平面図であ
る。
図面で１０は入力端子、１２は出力端子、１６は電界効
果トランジスタ、１８はコンデンサ、２２は１／２の大
きさの電界効果トランジスタ、２４．２６．２８はソー
ス、ドレイン拡散領域、３０はゲート電極、３２．３４
は同拡散領域、３６ ゛はゲート電極である。。FIGS. 1a, b and 2 are circuit diagrams showing examples of conventional sample-and-hold circuits, and FIGS. 3 and 4 are circuit diagrams showing examples of conventional sample-and-hold circuits. The figure is a circuit diagram showing an embodiment of the present invention, and FIG. 5 is a schematic plan view showing the layout of transistors in the embodiment. In the drawing, 10 is an input terminal, 12 is an output terminal, 16 is a field effect transistor, 18 is a capacitor, 22 is a field effect transistor of 1/2 size, 24, 26, 28 is a source, drain diffusion region, 30 is a gate electrode, 32.34
36 is the diffusion region, and 36 is the gate electrode. .
Claims (1)
と、ホールド電圧を出力する出力端子と、これらの人、
出力端子間に接続されたサンプリング用電界効果トラン
ジスタと、該出力端子と接地間に接続されそして該サン
プリング用電界効果トランジスタによりサンプリングさ
れた該入力電圧を保持するコンデンサとを備える妄ンプ
ルホールド回路において、該出力端子にソース、ドレイ
ンを接続され、ゲートには該サンプリング用電界効果ト
ランジスタのゲート電圧の反転信号を与えられかつ該サ
ンプリング用電界効果トランジスタのほぼ１ン２の大き
さの電界効果トランジスタを設け、且つ該サンプリング
用電界効果トランジスタが同じ間隔し、幅Ｗのチャネル
部を形成するように間隔をおいて連続して形成されたソ
ース、ドレイン拡散領域３つと、その２つのチャネル部
を覆うゲート電極とにより形成された２つの電界効果ト
ランジスタよりなり、該サンプリング用電界効果トラン
ジスタの１／２の大きさを持つ電界効果トランジスタが
該拡散領域２つとそれらの間のチャネル部を覆うゲート
′電極とにより形成された前記サンプリング用電界効果
トランジスタと同特性を有する１つの電界効果トランジ
スタよりなることを特徴とするサンプルホールド回路。An input terminal to which a continuously changing input voltage is applied, an output terminal to which a hold voltage is output, and these people.
A random sample hold circuit comprising a sampling field effect transistor connected between output terminals, and a capacitor connected between the output terminal and ground and holding the input voltage sampled by the sampling field effect transistor, A field effect transistor is provided whose source and drain are connected to the output terminal, whose gate is supplied with an inverted signal of the gate voltage of the sampling field effect transistor, and whose size is approximately 1×2 of the sampling field effect transistor. , and the sampling field effect transistor has three source and drain diffusion regions successively formed at equal intervals so as to form a channel portion having a width W, and a gate electrode covering the two channel portions. A field effect transistor having a size 1/2 of the sampling field effect transistor is formed by the two diffusion regions and a gate electrode covering the channel portion between them. A sample hold circuit comprising one field effect transistor having the same characteristics as the formed sampling field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12224384U JPS6047200U (en) | 1984-08-09 | 1984-08-09 | sample hold circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12224384U JPS6047200U (en) | 1984-08-09 | 1984-08-09 | sample hold circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6047200U true JPS6047200U (en) | 1985-04-03 |
Family
ID=30279494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12224384U Pending JPS6047200U (en) | 1984-08-09 | 1984-08-09 | sample hold circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6047200U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4075509A (en) * | 1976-10-12 | 1978-02-21 | National Semiconductor Corporation | Cmos comparator circuit and method of manufacture |
-
1984
- 1984-08-09 JP JP12224384U patent/JPS6047200U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4075509A (en) * | 1976-10-12 | 1978-02-21 | National Semiconductor Corporation | Cmos comparator circuit and method of manufacture |
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