JPS59149702U - semiconductor phase shifter - Google Patents

semiconductor phase shifter

Info

Publication number
JPS59149702U
JPS59149702U JP4451383U JP4451383U JPS59149702U JP S59149702 U JPS59149702 U JP S59149702U JP 4451383 U JP4451383 U JP 4451383U JP 4451383 U JP4451383 U JP 4451383U JP S59149702 U JPS59149702 U JP S59149702U
Authority
JP
Japan
Prior art keywords
field effect
line
effect transistors
electrodes
phase shifter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4451383U
Other languages
Japanese (ja)
Inventor
誠 松永
伊山 義忠
武田 文雄
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP4451383U priority Critical patent/JPS59149702U/en
Publication of JPS59149702U publication Critical patent/JPS59149702U/en
Pending legal-status Critical Current

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Landscapes

  • Waveguide Switches, Polarizers, And Phase Shifters (AREA)
  • Bipolar Transistors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体移相器の構造の一例を示す図、第
2図は第1図の動作説明図、第3図はこの考案による半
導体移相器の構造の一例を示す図、第4図は第3図に示
した半導体移動器の動作説明図、第5図は、この考案に
よる半導体移相器の他の実施例の構造図である。 図中1は半導体基板、2は地導体、3はストリップ導体
、4は第1の5PDTスイツチ、5は第2の5PDTス
イツチ、6はFETのドレイン電極、7はFETのゲー
ト電極、8はFETのソース電極、9は高インピーダン
ス線路、10は低インピーダンス線路、11はバイアス
回路、12はバイアス端子、13は主線路、14は第1
の分岐線路、15は第2の分岐線路、16は5PSTス
イツチ、17は電気長θのマイクロストリップ線路であ
る。 なお、図中同一あるいは相当部分には同一符号を付して
示しである。 毅   ・ 121 13   〒  /j 4
FIG. 1 is a diagram showing an example of the structure of a conventional semiconductor phase shifter, FIG. 2 is an explanatory diagram of the operation of FIG. 4 is an explanatory diagram of the operation of the semiconductor phase shifter shown in FIG. 3, and FIG. 5 is a structural diagram of another embodiment of the semiconductor phase shifter according to this invention. In the figure, 1 is the semiconductor substrate, 2 is the ground conductor, 3 is the strip conductor, 4 is the first 5PDT switch, 5 is the second 5PDT switch, 6 is the drain electrode of the FET, 7 is the gate electrode of the FET, and 8 is the FET 9 is a high impedance line, 10 is a low impedance line, 11 is a bias circuit, 12 is a bias terminal, 13 is a main line, and 14 is a first line.
15 is a second branch line, 16 is a 5PST switch, and 17 is a microstrip line with an electrical length θ. Note that the same or equivalent parts in the figures are indicated by the same reference numerals. Tsuyoshi ・ 121 13 〒 /j 4

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体基板に構成したマイクロストリップ線路から成る
入力および出力側各線路の一端に、上記半導体基板と同
一の半導体基板に構成した第1、第2の電界効果トラン
ジスタのドレイン電極ヲ接続し、上記入力側線路にドレ
イン電極を接続した第1および第2の電界効果トランジ
スタそれぞれのソース電極と、上記出力側線路にドレイ
ン電極を接続した第3および第4の電界効果トランジス
タのそれぞれのソース電極を異なる長さのマイクロスト
リップ線路から成る第1および第2の分岐線路で接続し
、上記第1および第2の分岐線路には、それぞれ1個以
上の電界効果トランジスタのトレイン電極を接続し、上
記電界効果トランジスタのソース電極には先端開放のマ
イストリップ線路を接続し、さらに、上記電界効果トラ
ンジスタおよび、第1〜第4の電界効果トランジスタそ
れぞれのゲート電極にバイアス電圧を印加する手段を具
備したことを特徴とする半導体移相器。
Drain electrodes of first and second field effect transistors formed on the same semiconductor substrate as the semiconductor substrate are connected to one end of each line on the input and output sides consisting of a microstrip line formed on a semiconductor substrate, and the input side The source electrodes of the first and second field effect transistors having their drain electrodes connected to the line and the source electrodes of the third and fourth field effect transistors having their drain electrodes connected to the output line have different lengths. are connected by first and second branch lines consisting of microstrip lines, and train electrodes of one or more field effect transistors are connected to the first and second branch lines, respectively. A MyStrip line with an open end is connected to the source electrode, and further includes means for applying a bias voltage to the gate electrodes of the field effect transistor and each of the first to fourth field effect transistors. Semiconductor phase shifter.
JP4451383U 1983-03-28 1983-03-28 semiconductor phase shifter Pending JPS59149702U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4451383U JPS59149702U (en) 1983-03-28 1983-03-28 semiconductor phase shifter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4451383U JPS59149702U (en) 1983-03-28 1983-03-28 semiconductor phase shifter

Publications (1)

Publication Number Publication Date
JPS59149702U true JPS59149702U (en) 1984-10-06

Family

ID=30175043

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4451383U Pending JPS59149702U (en) 1983-03-28 1983-03-28 semiconductor phase shifter

Country Status (1)

Country Link
JP (1) JPS59149702U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208307A (en) * 1985-03-13 1986-09-16 Mitsubishi Electric Corp Semiconductor phase shifter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208307A (en) * 1985-03-13 1986-09-16 Mitsubishi Electric Corp Semiconductor phase shifter

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